Week 5 Assignment 5:
QUESTION 1:
Which of the following is/are true for the spider leg clock distribution network?
a. A separate wire is laid out from the clock source to each of the destinations.
b. Use separate drivers on each of the wires.
c. Sometime a wire is shared from the clock source to multiple destinations.
d. Use a single powerful driver to drive all the output lines.
QUESTION 2:
What of the following are the main purposes of using buffers in a clock tree network?
a. To reduce the overall area requirements.
b. To reduce the jitter.
c. To reduce the delay.
d. To amplify the current source.
QUESTION 3:
What is true for CMOS transmission gate?
a. One nMOS and one pMOS transistors are connected in parallel where both of the
transistors are either turned on or turned off at any given time.
b. Two nMOS and a pMOS transistors are connected in parallel where exactly one of
them conducts at any given time.
c. One nMOS and one pMOS transistors are connected in series.
d. None of these
QUESTION 4:
Which of the following statement(s) is/are false for CMOS circuits?
a. An nMOS transistor passes logic 0 signal without any degradation.
b. An nMOS transistor passes logic 1 signal without any degradation.
c. A pMOS transistor passes logic 0 signal without any degradation.
d. A pMOS transistor passes logic 1 signal without any degradation.
QUESTION 5:
Which of the following techniques can mitigate the clock skew problem in a circuit?
a. Increase the frequency of the clock.
b. Make the maximum delays of each combinational circuit block between pairs of
register stages equal.
c. Equalize the delays of all the critical paths.
d. Make the delay from the clock source to all the clock sink points equal.
QUESTION 6:
Which of the following strategies can reduce the propagation delay of a long
interconnection line?
a. Reduce the width of the line.
b. Increase the width of the line.
c. Insert one or more buffers along the line.
d. All of these.
QUESTION 7:
Which of the following statements are true?
a. The X‐tree topology has better crosstalk effects as compared to the H‐tree
topology.
b. The H‐tree topology has better crosstalk effects as compared to the X‐tree
topology.
c. In power routing, the widths of various segments of the wires may vary.
d. In H‐tree the distance from clock source to each of the clock sink is same.
QUESTION 8:
For a H‐tree clock network connecting 16 points, the Manhattan distance from the
center point of the tree to any of the terminal points in units of grid cells will be
__________ units.
QUESTION 9:
When the target clock nodes are located in arbitrary locations all around a chip, which
of the following strategies is/are undesirable?
a. A pure H‐tree or X‐tree topology.
b. A two‐level structure with a clock mesh being driven by a regular H‐tree.
c. A spider leg network.
d. A two‐level structure with a clock mesh being driven by a regular X‐tree.
QUESTION 10:
Which of the following clock routing algorithm follows top‐down approach?
a. Method of Means and Medians (MMM) algorithm.
b. H‐tree based algorithm.
c. Recursive Geometric Matching (RGM) algorithm.
d. All of these.