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Timing Driven Routing and Analysis Insights

The document contains a series of questions related to timing-driven routing, delays in VLSI chips, static timing analysis, controlling values, Boolean functions, path sensitization, SAT-based false path analysis, and slack values. It tests knowledge on the principles and applications of these topics in the context of VLSI design. The questions cover both theoretical concepts and practical implications in circuit analysis and design.

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I.Vivek Anand ECE
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12 views2 pages

Timing Driven Routing and Analysis Insights

The document contains a series of questions related to timing-driven routing, delays in VLSI chips, static timing analysis, controlling values, Boolean functions, path sensitization, SAT-based false path analysis, and slack values. It tests knowledge on the principles and applications of these topics in the context of VLSI design. The questions cover both theoretical concepts and practical implications in circuit analysis and design.

Uploaded by

I.Vivek Anand ECE
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Week 6:

1. What is the main purpose of timing‐driven routing?


a. Minimize the signal delays when selecting routing topologies and specific
routes.
b. Minimize the signal delays when the cells are assigned locations on the layout
area.
c. Minimize the skew and jitter of all the signal lines.
d. None of these.
2. Which of the following delays dominate in modern‐day VLSI chips?
a. Clock delay.
b. Gate delay.
c. Interconnection delay.
d. All of these.
3. Which of the following statements are true for static timing analysis?
a. Propagates actual arrival times (AAT) to the terminals of every gate or cell.
b. Can quickly identify timing violations.
c. Cannot model propagation of signal transitions with the worst possible delay.
d. The process includes false paths from the analysis.
4. Which of the following are not instances of controlling values?
a. Logic 0 at the input of an XOR gate.
b. Logic 1 at the input of an OR gate.
c. Logic 0 at the input of an AND gate.
d. Logic 0 at the input of an OR gate.
5. The Boolean difference of a Boolean function X with respect to another function Y
defines the conditions where:
a. The logic values of X and Y are always different.
b. The logic values of X and Y are always same.
c. Any change in the logic value of X will also cause the logic value of Y to
change.
d. Any change in the logic value of Y will also cause the logic value of X to
change.
6. When we want to sensitize a path from a primary input to one of the primary
outputs, we have to:
a. Apply controlling values to the side inputs of all gates in the path.
b. Ensure that there is no skew or jitter in the path.
c. Apply non‐controlling values to the side inputs of all gates in the path.
d. None of these.
7. Static timing analysis is applicable to asynchronous subsystems. True or False?

8. Which of the following statements is/are true for SAT based false path analysis?
a. Modern SAT solvers cannot handle large number of variables.
b. Modern SAT solvers can handle large number of variables.
c. A SAT solver tries to find some assignments of the variables for which F=1,
where F is in sum‐of‐products form.
d. A SAT solver tries to find some assignments of the variables for which F=1, where
F is in product‐of‐sums form.
9. If the RAT and AAT values for line x are RAT(x) = 17 and AAT(x) = 14, which of the
following is/are true?
a. The Slack value on line x is +3.
b. The Slack value on line x is ‐3.
c. The timing constraint has been met.
d. The Slack value on line x is ‐4.
10. Which of the following is/are used to speed up the process of static timing analysis?
a. All the timing violations are eliminated before starting the process.
b. All the false paths in the circuit are excluded from the analysis.
c. The RAT and AAT values of all the lines are made equal.
d. All of these.

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