Physical Aware Synthesis

Lab Manual

Learning Objectives:

After completing the lab, you will be able to,

● Setup the project path and specify the file directories.

● Understand link, target libraries and design files.
● Load RTL design, SDC and read the physical constraint (DEF) file.
● Synthesize into optimized and technology dependent gate-level netlist.
● Check for the reports if the design has met timing, area, power, and
constraints after synthesis.
● Write out the Netlist and Synopsys design constraints (SDC) files.

Copy the lab database to your home directory.

linux > cp –rf /home/****/ChipTop/synth/ ./

Note:(Actual path will be provided by Trainers)

Go through the directory structure & files

RTL -> Directory for RTL files.

inputs -> Directory for inputs file.
logs -> Directory for log files

reports -> Directory to save all reports

scripts -> Directory for script files

outputs -> Directory to save output files

work -> Directory to run the tool

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In the scripts directory, open “synth_physical.tcl” using “vi” or “gvim”
editor command from the scripts directory and go through the file contents.
linux > gvim synth_physical.tcl

From a different linux shell, Invoke the Design Compiler (DC) in topographical
mode tool using “dc_shell-t -topographical” from the work directory by
following steps,
linux > cd ChipTop/synth
linux:synth> cd work
linux:work > tcsh
linux:work > dc_shell-t -topographical_mode -output_log_file\
../logs/synth_physical.log
Now copy the commands from the “synth_physical.tcl” file and paste each
command one by one in the “dc_shell -topo” command prompt to start the physical
synthesis lab as shown below.

Set the current project path, link library path , target library path for the design.
Now specify directories that the tool searches for files, by using the below command.

dc_shell-topo >source ../scripts/common_setup.tcl

Above command sets the link library to be used by the DC to resolve references which are
instantiated in the RTL. These could be either PLL, Memory, standard cell, or any other
macro for which there is no module definition present in the RTL. For example,

BUF uBUF (.FIN(clk), .FOUT(clkout));

The “BUF” module shall be resolved from the link library. That is, the DC compiler
investigates the link library in order to get the characteristic information of the BUF
like timings etc.

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Specify the list libraries used in the design, by using the " link_library" command.

dc_shell-topo >set link_library $LINK_LIBRARY_FILES_CLG

Specify the list of technology libraries, by using the “ target_library” command.

dc_shell-topo >set target_library $TARGET_LIBRARY_FILES_CLG

Above command specifies the target library to be used by the DC for synthesizing the
RTL and mapping the logic to appropriate standard cells. For example,

assign Z = A && B;

DC synthesizes to AND gate which is inferred from the target library.

“saed32hvt_ss0p95v125c.db ”

Exclude the below set of Target libraries during optimization using below
“set_dont_use” command.

This command Sets the dont_use attribute on library cells, modules, and
implementations. Library objects with the dont_use attribute is excluded from the
target library during optimization.

dc_shell-topo >set_dont_use [get_lib_cells \

-quiet */SAEDRVT14_AO21_U_0P5]
dc_shell-topo >set_dont_use [get_lib_cells */SAED*_EO2_V1_0P75]
dc_shell-topo >set_dont_use [get_lib_cells */SAED*_AO221_2]
dc_shell-topo >set_dont_use [get_lib_cells */SAED*_AO221_0P5]
dc_shell-topo >set_dont_use [get_lib_cells */SAED*_OAI22_0P5]

Note : Create newLIB directory inside the work directory before executing
create_mw_lib command

dc_shell-topo >sh mkdir newLIB

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Observe the physical library specification using the command create_mw_lib. It
creates the milky-way library with the technology file saed32nm_p9m_mw.tf and the
reference physical library of standard cells.
Note: Milky-way library myLIB have been created inside the directory newLIB

dc_shell-topo > create_mw_lib -technology

${DESIGN_REF_PATH}/tech/new_tf/saed14nm_1p9m_mw.tf \
-bus_naming_style {[%d]} \
-mw_reference_library { \
/home/tools/14nm/stdcell_hvt/milkyway/saed14nm_hvt_1p9m \
/home/tools/14nm/stdcell_lvt/milkyway/saed14nm_lvt_1p9m\
/home/tools/14nm/stdcell_rvt/milkyway/saed14nm_rvt_1p9m \
/home/tools/14nm/stdcell_slvt/milkyway/saed14nm_slvt_1p9m} \
-open newLIB/myLIB

Once the library database is created, attach the TLU+ files by specifying it using the
command set_tlu_plus_files

dc_shell-topo > set_tlu_plus_files -max_tluplus

${DESIGN_REF_PATH}/tech/star_rc/max/saed14nm_1p9m_Cmax.tluplus \
-min_tluplus
\ ${DESIGN_REF_PATH}/tech/star_rc/min/saed14nm_1p9m_Cmin.tluplus
\
-tech2itf_map
\ ${DESIGN_REF_PATH}/tech/star_rc/saed14nm_tf_itf_tluplus.map

Analyze the specified HDL source files by using below command.

dc_shell-topo > analyze -library WORK -format verilog
\ {../RTL/top_odyssey.v \

../RTL/srff.v \
../RTL/power_controller.v \
../RTL/mult3232.v \
../RTL/MemXHier.v \
../RTL/MemYHier.v \
../RTL/InstructionDecoder.v \
../RTL/gpr.v \
../RTL/genpp32.v \

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 ../RTL/csa.v \
../RTL/cla.v \
../RTL/address_gen.v \
../RTL/addpp32.v \
}
Check for any errors / Warnings? _______________

This command reads the RTL files and analyses the RTL code and stores the resulting
templates into the specified library in a format ready to elaborate to form link-able cells
of a full design.
analyze - It translates specified HDL files and stores the intermediate format in
the specified library.
Read the Top Module design by using the command “read_file”.

dc_shell-topo > read_file -format Verilog

{../RTL/top_odyssey.v}

Set the design variable Top module name “ChipTop” as specified in the netlist file.
dc_shell-topo > set design ChipTop

Check for design problems in current design, by using the “ check_design”

command.
dc_shell-topo > check_design

Now, just to see what has happened after the analyze/elaborate, let’s write the Verilog
using the below command.
dc_shell-topo > write_file -hierarchy -format verilog -output \
../outputs/chiptop_generic.vs

The above command generates the intermediate technology independent (GTECH)

design. To view the file, Open the file “chiptop_gtech.vs” and analyze it. You shall
see that behavioural design is translated to some intermediate form and investigate
each of the components which is instantiated.

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Read Synopsys Design Constraints (SDC) file from below path.
dc_shell-topo > source -echo ../inputs/chiptop+_s0.sdc

Specifies a list of registers in the current design to be included for clock gating.
dc_shell-topo > set_clock_gating_registers \
-include_instances [remove_from_collection \
[all_registers -clock clock] \
[get_cells "MemYHier/MemXb MemYHier/MemXa \
MemXHier/MemXb MemXHier/MemXa"]]

Define the operating conditions for the current design using below command.
dc_shell-topo > set_operating_conditions -min ff0p88v125c \
-max ss0p6v125c

Now link the design with libraries by using link command

The link command uses the link_library and search_path variables along with the
local_link_library design attribute to resolve design references.
dc_shell-topo > link

dc_shell-topo > set_fix_multiple_port_nets -all \

-buffer_constants [get_designs ChipTop]

Once the design environment & constraint have been defined, it can now be
synthesized.

Now after constraining design, do check_timing

dc_shell-topo > check_timing

Now bypass the unified power format file, by using the below command.
dc_shell-topo > set dc_allow_rtl_pg true

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The above command allows Design Compiler to read RTL containing a limited set
of PG (power/ground) nets and pin connections.

Extract physical constraints file [Link] for doing physical aware synthesis

dc_shell-topo
>extract_physical_constraints\ ../inputs/[Link]

Modify all names in the design hierarchy. By default, the tool changes only objects in the
current design.
dc_shell-topo > change_names -rules verilog -verbose -hier

Set the fix_hold attribute on clocks in the current design.

dc_shell-topo > set_fix_hold [all_clocks]

The above command sets the fix_hold attribute on the specified clock objects in the
current design. The fix_hold attribute informs optimization that hold time violations of
the specified clocks should be fixed.

Perform a high effort compile on the current design for the better quality of results
(QoR), by using the “compile” command.

dc_shell-topo >compile_ultra

Now after compiling the design, do check_timing again.

dc_shell-topo > check_timing

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After synthesis, check if the design meets timing, area, power constraints using
following report commands and redirect it to the reports directory.
dc_shell-topo > report_timing > ../reports/[Link]

dc_shell-topo > report_constraint -all_violators > \

../reports/all_violators.rpt

dc_shell-topo > report_area > ../reports/[Link]

dc_shell-topo > report_power > ../reports/[Link]

dc_shell-topo > report_qor > ../reports/[Link]

Now write out the design netlist to a file, by using the below command.
dc_shell-topo > write_file -hierarchy -format verilog -output \
../outputs/chiptop_phy.vg

Check the Netlist file by using below command syntax.

dc_shell-topo > sh gvim ../outputs/chiptop_phy.vg &

Write out a Synopsys Design Constraints (SDC) file by using below command for
physical design.
dc_shell-topo > write_sdc ../outputs/chiptop_phy.sdc

Check the SDC file by using below command.

dc_shell-topo > sh gvim ../outputs/chiptop_phy.sdc &

Close the DC shell.

dc_shell-topo > exit

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