Static Timing Analysis

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Why Timing Analysis ?

Why am I here & listening this??

Is the Timing Analysis, very critical??

 Yes, It is critical, because, timing is one among the

three important design constraints for any chip.
 The Three important design constraints are
 Timing
 Power Consumption
 Area of Silicon chip.

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Why Timing Analysis ?

 How fast can I run the

design?!!!
 Does the design meet a given
timing requirement?!!

2.8 GHz 3.0 GHz

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What is Timing Analysis?

 Timing analysis is the methodical analysis of a digital circuit to determine if the

timing constraints defined in specifications are met.

I want to, But,

3.0 GHz 2.8 GHz

Expectation Reality

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Summary

 Timing analysis is the methodical analysis of a digital circuit to determine if the

timing constraints defined in specifications are met.

 Performing Timing Analysis is critical to decide, whether to go ahead with

design or any modifications to be done in the design.

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Types of timing analysis

There are two main techniques available to do so

 Dynamic timing analysis – Verifies timing in the functional context by applying

stimulus

 Static timing analysis – Verifies timing in each path of the logic circuit without
applying stimulus

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Dynamic Timing Analysis

Test Bench

Stimulus Output
generation Monitoring
Outputs
Inputs

Top Level
of Design

Clock with desired

frequency

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Dynamic Timing Analysis

Advantages:
 Can be very accurate (spice-level)
 Simulator calculates the logic value and delays

Disadvantages:
 Vector creation takes too long, slow
 Incomplete timing coverage
 Analysis quality depends on stimulus vectors
 Requires more memory and CPU resources over STA

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Static Timing Analysis

 STA is an exhaustive method of analyzing, debugging and validating the timing

performance of a design.
 STA is capable of verifying every path.
50 ns
50 ns
200 ns 0 200 ns 0
o/p

100 ns 1 100 ns 1

sel 10 ns

 The main goal of static timing analysis is to verify that, all signals will arrive
neither too early nor too late, and hence proper circuit operation can be assured.

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Static Timing Analysis

Advantages:
 Much faster than timing-driven, gate-level simulation
 Exhaustive timing coverage
 Does not require input vectors
 More efficient than DTA in memory and CPU resources
 Capacity for millions of gates

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Static Timing Analysis

Limitations:
 Works best with synchronous (not asynchronous) logic
 Complex to learn
 Must define timing requirements / exceptions
 Difficulty in handling:
 Multiple clocks
 false paths
 Multicycle paths

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Summary

Timing Analysis

DTA STA

 Dynamic Timing Analysis is extension to functional verification and it will be

done by driving stimulus to the design.

 Static Timing Analysis ensures that, all the paths in the logic circuit are free of
timing violations.

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False Path

50 ns
50 ns
200 ns 0 200 ns 0
o/p 500 ns
300 ns
100 ns 1 100 ns 1 400 ns

sel 10 ns

False Path

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Controlling/Non-Controlling Values

Controlled value of AND

0 0 1

Controlling value of AND Non-Controlling value of AND

Controlled value of OR
1 1 0

Controlling value of OR
Non-Controlling value of OR

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Path sensitization
0
0
w2 = 1
1
w3 = 0
1
w4 = 1

1
1
w2 = 1
0
w3 = 0
0
w4 = 1

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Multicycle path

♦ Paths which intentionally require more than one clock cycle to propagate.

D
Comb D

Clk
Clk
D

Clk

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Summary

False Paths
 Paths that physically exist in a design but are not logic /functional paths
 Paths that may not be excited
 Circuit delay = Length of longest path ?
 Not a good enough bound (too pessimistic)
 Circuit delay = Time of last output change

Multicycle Paths
 Paths which intentionally require more than one clock cycle to propagate.

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STA in Digital design flow

Specification Floor Planning

Architecture Placement

Behavioral Model Clock Tree Synthesis Timing

Not OK
RTL Coding Routing
Bugs
Verification Static Timing Analysis

Synthesis Physical Layout

Gate Level Simulation Design Rule Check

DFT Insertion Layout Vs Schematic

GDSII
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STA Tools and Vendors

Primetime  Synopsys (gate-level)

PathMill  Epic (Synopsys, transistor-level)
Motive  ViewLogic
Velocity  Mentor Graphics
ETS  Cadence
Goldtime  ExtremeDA
EinsTimer  IBM (Gate-level)
EinsTLT  IBM (transistor-level)
Timecraft  INCENTA

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Inputs & outputs of STA Tools

Netlist
SDF & Model Lib
(or) STA Tool Reports
Net delays & SPEf

Constraints

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Sample Reports

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Summary

 Static Timing Analysis can be performed on Gate Level Netlist or Routed Netlist.

 STA Tool is going to perform timing analysis by using netlist, delay

informations, and constraints and generates a detailed report by which, we can
understand if there are any timing violations in the design.

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Clock

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Clock

♦ The clock is a periodic synchronization signal used as a time reference for data
transfers in synchronous digital systems

T (Clock Period)

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Slew

♦ Amount of time it takes for a signal transition to occur

♦ Accounts for uncertainty in Rise and fall times of the signal
♦ Slew rate is measured in volts/sec

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Types of Clocks

 Gated Clock

 Virtual Clock

 Generated (Derived) Clock

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Gated clock

♦ Clock gating reduces power consumption by switching off the clock to flipflops
when the value of those flipflops does not change.

♦ It is mainly used in Low Power Applications.

clock
Gated_clock
clk_enb

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Gated clock

Results on 32bit
RISC Architecture

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Virtual clock

♦ Virtual clock has no sources.

♦ Not connected to any port or pin within the current design
♦ Mainly used to model the I/O timing specification
♦ Serves as a reference for input or output delays

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 Generated Clock

♦ A design might include clock dividers or other structures that produce a new
clock from a master source clock.

Generated
Master Clock
Clock

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Clock domain

 Single Clock Domain

 Multi Clock Domain

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Synchronizing clock domain

Any two systems are considered

asynchronous to each other:
When they operate at two different
frequency

When they operate at same

frequency, but at two different clock
phase angles

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Synchronizing clock domain

Two common methods for

synchronizing data between clock
domains are:

Use handshake signals to pass data

between clock domains or,

Use fIfOs (first In first Out

memories) to store data using one
clock domain and to retrieve data
using another clock domain.

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Clock Variations (Uncertainty)

♦ The possible Uncertainties in clock are

 Latency
 Skew
 Jitter

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Latency

♦ Clock Source latency time it takes for a clock signal to propagate from its
actual ideal waveform origin point to the clock definition point in the design.
♦ Clock Network latency time it takes for a clock signal to propagate from the
clock definition point to a register clock pin.

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Clock skew

♦ Difference between arrival times of the clock at different devices is called clock
skew

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Positive skew

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Negative skew

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Local and Global skew

♦ Local skew
 Local skew is the difference in the arrival of clock signal at the clock pin of
related flops.
♦ Global skew
 Global skew is the difference in the arrival of clock signal at the clock pin
of non related flops

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Strategies to minimize clock skew

♦ Distribute clock signals in general direction of data flow.

♦ Wires carrying clock between communicating components should be as short as
possible.
♦ Make all wires from the clock source the same length.

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Jitter

♦ Frequency variation in the clock source

♦ Difference between the actual clock period and ideal clock period
♦ Power supply noise and variations in the temperature are the main sources of
jitter

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Skew and Jitter

♦ Skew is permanent variation in clock arrival times

• variation in when the same clock edge is seen by two different flip-flops
♦ Jitter is temporary variation in clock arrival times
• variation in when two successive clock edges are seen by the same flip-flop

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Clock

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Summary

♦ The clock is a periodic synchronization signal used as a time reference for data
transfers in synchronous digital systems.
♦ Slew: Amount of time it takes for a signal transition to occur.

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Timing parameters in STA

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Arrival time

♦ Arrival time - An arrival time defines the instant of time, at which a proper
value will arrive at a particular node.

90 nSec
A
70 nSec Y = A.B
B
20 nSec

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Required time

♦ Required time - Required time defines the instant of time, at which a proper
value is expected to arrive at a particular node.

A 85 nSec - Expectation
70 nSec Y = A.B
B
15 nSec - Expectation
90 nSec – Arrival Time
85 nSec – Required Time

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Slack and Critical Path

♦ Slack
• It is the difference between the required (constraint) time and the arrival time
(inputs and delays).
• Negative slack indicates that constraints have not been met, while positive
slack indicates that constraints have been met.
• Slack analysis is used to identify timing critical paths in a design by the static
timing analysis tool

♦ Critical path
• Any logical path in the design that violates the timing constraints
• Path with a negative slack

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Slack Analysis

Wire delay is 1ns. Tpd (Actual) = 84 – 5 = 79nS

Input Arrival Time is 5ns.
Output Required time is 65 Tpd (Expected) = 60nS

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Timing met ?

Timing is met when slack is greater than or equal to zero

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Delays in Combinational Circuits

Contamination Delay ( Tcd ) Propagation Delay ( Tpd )

The amount of time needed for a The amount of time needed for a
change in a logic input to result in an change in a logic input to result in a
initial change at an output. permanent change at an output.

I/P O/P

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Delays in Sequential Circuits

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Delays in Sequential Circuits

D2Q Delay : A change in input D cannot bring a change in the output of the
flipflop. So, D2Q delay is not valid.

Clk2Q Delay : It is the time it takes for the flipflop output to be in a stable state
after a clock edge occurs.

S2Q Delay : It is the time taken by flipflop to come to SET state after the
application of asynchronous PRESET input.

R2Q Delay : It is the time taken by flipflop to come to RESET state after the
application of asynchronous CLEAR input.

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Setup time and Hold time

Synchronous inputs (e.g. D) have Setup, Hold time specification with respect to
the CLOCK input.
Setup Time (tsu): is the minimum time interval for which the input signal must
be stable (unchanging) prior to the sampling event of the clock for the input signal
to be recognized correctly.

Hold Time (th): is the minimum time interval for which the input signal must be
stable (unchanging) following the sampling event of the clock for the input signal
to be recognized correctly.

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Setup time and Hold time

Setup/Hold measured around active clock edge.

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Setup time and Hold time Violations

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Setup time

Tclk

Tclk-Q Tinv
1

Tclk – Tsetup ≥ Tclk_Q + Tinv Tclk ≥ Tclk_Q + Tinv + Tsetup

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Hold time

0
Tclk-Q T
inv

If Tclk-Q >Thold, then, there will

Tclk-Q + Tinv ≥ Thold be no hold violations for all
the values of Tpd-inv
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Example 1

Determine the Maximum frequency of operation of the given circuit.

T (pd-inv) = 3ns

Tclk ≥ Tclk_Q + Tinv + Tsetup

Tclk ≥ 5 + 3 + 2
Tclk ≥ 10ns
T (Clk-Q) = 5 nS
T (setup) = 2 nS fmax = 1 / Tclk
T (Hold) = 1 nS
fmax = 1 / 10ns = 100MHz
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Timing Analysis

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Calculation of Setup time Const without CLK Skew

Tclk

Tclk-Q Tpd

Tclk - Tsetup

Tclk – Tsetup ≥ Tclk_Q(max) + Tpd(max) Tclk ≥ Tclk_Q(max) + Tpd(max) + Tsetup

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 Calculation of Hold time Const without CLK Skew

Tclk

Tclk-Q

Tpd

Tclk-Q(min) + Tpd(min) ≥ Thold Thold ≤ Tclk-Q(min) + Tpd(min)

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Calculation of Setup time Const with +ve Skew

Tclk

Tclk-Q Tpd

Tclk + Tskew - Tsetup

Tclk
Tskew

Tclk + Tskew - Tsetup ≥ Tclk_Q(max) + Tpd(max) Tclk + Tskew ≥ Tclk_Q(max) + Tpd(max) + Tsetup
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 Calculation of Hold time Const with +ve Skew

Tclk

Tclk-Q

Tpd

Tskew
Tclk-Q(min) + Tpd(min) ≥ Thold + Tskew Thold ≤ Tclk-Q(min) + Tpd(min) - Tskew
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Calculation of Setup time Const with -ve Skew

Tclk

Tclk-Q Tpd Tskew

Tclk - Tskew - Tsetup

Tskew

Tclk - Tskew - Tsetup ≥ Tclk_Q(max) + Tpd(max) Tclk - Tskew ≥ Tclk_Q(max) + Tpd(max) + Tsetup
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Calculation of Hold time Const with -ve Skew

Tclk

Tclk-Q

Tpd

Tskew

Tclk-Q(min) + Tpd(min) ≥ Thold - Tskew Thold ≤ Tclk-Q(min) + Tpd(min) + Tskew

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Example 2

In the below circuit the setup and hold times of the flipflops are 5 ns and 1 ns
respectively. The propagation delay of the flipflops may vary between 4 and 7 ns
while the propagation delay of the gates may vary between 2 and 6 ns. Determine
the Maximum clock frequency and identify the hold time violations. (if any)

-ve skew

Tclk - Tskew ≥ Tclk_Q(max) + Tpd(max) + Tsetup

Tclk - 6 ≥ 7 + 0 + 5
Tclk ≥ 7 + 0 + 5 + 6 Tclk ≥ 18ns f < 55MHz
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Example 2

In the below circuit the setup and hold times of the flipflops are 5 ns and 1 ns
respectively. The propagation delay of the flipflops may vary between 4 and 7 ns
while the propagation delay of the gates may vary between 2 and 6 ns. Determine
the Maximum clock frequency and identify the hold time violations. (if any)

-ve skew

Tclk-Q(min) + Tpd(min) ≥ Thold - Tskew

4- 0 ≥ 1 - 2
6≥1 No Hold Violation
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External Setup time & Hold time

External inputs are buffered through pad drivers and may go through
combinational logic before they reach a synchronous input. This buffering adds
propagation delay.

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 External Setup time

Tsetup (ext) Tsetup (ext)

Tpd(d-in)

Tpd(clk) Tpd(clk)

Tsetup (int) Tsetup (int)

Tsetup(ext) + Tpd(clk) - Tsetup(int) ≥ Tpd(d-in) Tsetup(ext) ≥ Tpd(d-in) + Tsetup(int) - Tpd(clk)

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External Hold time

Thold (ext) Thold (ext)

Tpd(d-in)

Tpd(clk) Tpd(clk)

Thold (int) Thold(int)

Tpd(d-in) ≥ Tpd(clk) + Thold(int) - Thold(ext) Thold(ext) ≥ Tpd(clk) + Thold(int) - Tpd(d-in)

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 Summary

Slack : It is the difference between the required (constraint) time and the arrival
time (inputs and delays).
Critical path: Any logical path in the design that violates the timing constraints.
Setup Time (tsu): is the minimum time interval for which the input signal must be
stable (unchanging) prior to the sampling event of the clock for the input signal to
be recognized correctly.
A setup time violation, when a signal arrives too late, and misses the time when it
should advance.
Hold Time (th): is the minimum time interval for which the input signal must be
stable (unchanging) following the sampling event of the clock for the input signal
to be recognized correctly.
A hold time violation, when a input signal change too quickly, after the clock's
active transition

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Summary (Contd..)

Scenario Setup time Hold time

No Skew Tclk ≥ Tclk_Q(max) + Tpd(max) + Tsetup Thold ≤ Tclk-Q(min) + Tpd(min)

+ve Skew Tclk + Tskew ≥ Tclk_Q(max) + Tpd(max) + Tsetup Thold ≤ Tclk-Q(min) + Tpd(min) - Tskew

-ve Skew Tclk - Tskew ≥ Tclk_Q(max) + Tpd(max) + Tsetup Thold ≤ Tclk-Q(min) + Tpd(min) + Tskew

External Set up time and Hold time Calculation:

Tsetup(ext) ≥ Tpd(d-in) + Tsetup(int) + Tpd(clk)

Thold(ext) ≥ Tpd(clk) + Thold(int) - Tpd(d-in)

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 STA Procedure

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Three Steps in Static Timing Analysis

Break the design into sets of timing paths

Calculate the delay of each path
Check all path delays to see if the given timing constraints are met

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Types of timing path

Primary input to register path

Register to Primary output path

Register to register path

Primary input to primary output

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Timing Path

A Timing Path is a point-to-point path in a design which can propagate data from
one flip-flop to another.
Each path has a start point and an end point
Start points: Input ports, Clock pins of flip-flops.
Endpoints: Output ports, Data input pins of flip-flops.

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Example - 3

Determine Maximum clock frequency.

Tclk ≥ Tclk_Q(max) + Tpd(max) + Tsetup

Tclk ≥ 10 + 5 + 2 Tclk ≥ 10
Tclk ≥ 17 ns
f = 1/17 ns = 58.8MHz
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Example - 4
Path P1 P2 P3 P4 P5 P6 P7
Determine Maximum clock frequency.
Dealy 16 12 11
P1

P3

P2

P1 – i/p to o/p combinational path – U7, U5, U6 → Tcomb = 1+9+6 = 16nSec

P2 – Primary input to register path – U7, U3, U1 → Tcomb + Tsu = 1+8+3 = 12nSec
P3 – Primary input to register path – U7, U4, U2 → Tcomb + Tsu = 1+7+3 = 11nSec
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 Example - 4
Path P1 P2 P3 P4 P5 P6 P7
Determine Maximum clock frequency.
Dealy 16 12 11 15 16

P4 P5

P4 - Register to register path – U1, U4, U2 → Tclk-q + Tcomb + Tsu = 5+7+3 = 15nSec

P5 - Register to register path – U2, U3, U1 → Tclk-q + Tcomb + Tsu = 5+8+3 = 16nSec
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Example - 4
Path P1 P2 P3 P4 P5 P6 P7
Determine Maximum clock frequency.
Dealy 16 12 11 15 16 20 20
P7

P6

T = 20nSec
f = 1/20n = 50MHz
P6 - Register to Primary output path – U2, U5, U6 → Tclk-q + Tcomb = 5+9+6 = 20nSec

P7 - Register to Primary output path – U1, U5, U6 → Tclk-q + Tcomb = 5+9+6 = 20nSec
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 Methods to improve timing

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Methods to improve timing

Pipelining

Retiming

Time borrowing

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 Pipelining

25+23+2= 50 3+2+14+14+2 = 35 3+20+17 = 40

25+23+2=3+23+2
50 = 28 3+2+14+14+2 = 35 3+20+17 = 40
3+20+2 = 25 3+17 = 20
25+2 = 27

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Retiming

3+2+14+14+2 = 35
3+23+2 = 28 3+14+14+2 = 33 3+20+2 = 25 3+17 = 20
25+2 = 27 3+2+2 = 7

3+14+2 = 33
19 3+20+2 = 25 3+17 = 20
25+2 = 27 3+23+2 = 28 3+2+2 = 7 = 213+14+14+2
3+2+14+2

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Advantages and Disadvantages

Advantages:
 Higher throughput than combinational system
 Different parts of the logic work on different parts of the problem. So easy
to debug.

Disadvantages:
 Generally, increases latency
 More Silicon Area and More power consumption

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Time Borrowing

T pd = 24 nSec

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Time Borrowing

T pd = 19 nSec

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Summary

Pipelining, Retiming and time borrowing are the techniques available for
improving the timing of the circuits.

All these methods have both advantages and disadvantages as well.

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Thank You

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