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FPGA Lab Setup Guide for EE5332

The document outlines the setup process for the EE5332-2025 FPGA Lab, including steps for initial simulation setup, troubleshooting common errors, and programming the FPGA. It provides commands for cloning simulation files, generating bitstreams, and opening the Vivado project. Additionally, it offers guidance on resolving issues related to the Vivado executable and cable drivers.

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422-Singam setti Dharani
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14 views5 pages

FPGA Lab Setup Guide for EE5332

The document outlines the setup process for the EE5332-2025 FPGA Lab, including steps for initial simulation setup, troubleshooting common errors, and programming the FPGA. It provides commands for cloning simulation files, generating bitstreams, and opening the Vivado project. Additionally, it offers guidance on resolving issues related to the Vivado executable and cable drivers.

Uploaded by

422-Singam setti Dharani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

ee5332-2025 FPGA Lab Setup

13 March 2025

1 Initial Simulation Setup


Step 1: Procure the simulation files by executing the following command on your shell.

git clone [Link]


Step 2: Change directory to where the scripts are located.
cd ee5332-2025/labs/fpga/scripts

Step 3: Generate the synthesize the design and generate the bitstream.
make bitfile
NOTE: You’re encouraged to explore the scripts written by the professor which make this process as simple as it is.

If you encounter any errors, please refer to section 2. If not, you can move to section 3. Please connect with
one of the TAs to use one of the FPGAs.

2 Troubleshooting
NOTE: This section only lists the most common set of errors one might face. If the issue you face isn’t already listed
here, please connect with the TAs.

1: vivado: No such file or directory


This basically means your machine can’t find the vivado executable. Ensure that your machine’s PATH lists the
Vivado’s bin directory in it.

echo $PATH // to check if Vivado/.../bin is in the PATH


export PATH=$PATH:/opt/Xilinx/Vivado/2021.1/bin
2: Auto-connect doesn’t recognize the device. This probably means that the cable drivers are not installed, or
the cable/board have an issue. The latter is unlikely.

cd /opt/Xilinx/Vivado/2021.1/data/xicom/cable_drivers/lin64/install_script/install_drivers
./install_drivers

3 Programming the FPGA


Step 4: Open the Vivado project. The script we executed earlier would have created a Vivado project file that you
can simply open. To do so, execute the following command.
vivado ../build/fpga/counter_top.xpr

You should see a screen that looks something like this.

1
Step 5: Connect the FPGA over USB and power it on. Within Vivado, select the ”Open Target” option and select
”Auto Connect”.

Step 6: Ensure that the devices are recognized. You will need to setup cable drivers for this.

2
Step 7: Program the FPGA with the generated bitstream. Right clock on the device and say ”Program”.

Step 8: Ensure you see the following screen.

3
Step 9: Switch to the Virtual IOs (hw vios) and insert all signals into the VIO.

4
You’re all setup!

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