S1BCA DIGITAL FUNDAMENTALSSEQUENTIAL LOGIC CIRCUITS

MODULE 4
UNIT 4-Sequential Logic Circuits: Flip flops- RS, JK, T, D, Triggering of flip flops, Concept of
Registers

Introduction
A sequential circuit is a logic circuit that consists of a memory element to store history of past
operation of the circuit. Therefore, the output of a sequential circuit depends on present inputs as well
as past outputs of the circuit. The previous output is treated as the present state. So, the sequential
circuit contains the combinational circuit and its memory storage elements. A sequential circuit
doesn't need to always contain a combinational circuit. So, the sequential circuit can contain only the
memory elementThe block diagram of a typical sequential circuit is shown in the following figure
−

Fig: Sequential Logic Circuits

Types of Sequential Circuits

 Asynchronous sequential circuits: The clock signals are not used by the Asynchronous sequential
circuits. The asynchronous circuit is operated through the pulses. So, the changes in the input can
change the state of the circuit. The asynchronous circuits do not use clock pulses. The internal state is
changed when the input variable is changed. The un-clocked flip-flops or time-delayed are the
memory elements of asynchronous sequential circuits. The asynchronous sequential circuit is similar
to the combinational circuits with feedback.
 Synchronous sequential circuits: In synchronous sequential circuits, synchronization of the
memory element's state is done by the clock signal. The output is stored in either flip flops or latches
(memory devices). The synchronization of the outputs is done with either only negative edges of the
clock signal or only positive edges.

Latches and Flip-flops

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Latches and flip-flops are the basic elements for storing information. One latch or flip- flop can
store one bit of information. The main difference between latches and flip-flops is that for latches,
their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other
words, when they are enabled, their content changes immediately when their inputs change.
Flip-flops, on the other hand, have their content change only either at the rising or falling edge
of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling
edge of the clock, the flip-flop content remains constant even if the input changes.
There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major
differences in these flip-flop types are the number of inputs they have and how they change state. For

each type, there are also different variations that enhance their operations.
A latch may be an active-high input latch or an active –LOW input latch. Active –HIGH
means that the SET and RESET inputs are normally resting in the low state and one of them will be
pulsed high whenever we want to change latch outputs.
Basic Bistable Element
Fig. 1 shows a basic bistable element. It has two inputs and two outputs as shown. The output of one
NOT gate is connected to the input of the other. In this case, the outputs 𝑄 and Q will have a stable
value complementary to each other, but cannot be controlled. To control the bistable element, we use
latches.

SR latch:
The latch has two outputs Q and Q‘. When the circuit is switched on the latch may enter into
any state. If Q=1, then Q‘=0, which is called SET state. If Q=0, then Q‘=1, which is called RESET state.
Whether the latch is in SET state or RESET state, it will continue to remain in the same state, as long as
the power is not switched off. But the latch is not an useful circuit, since there is no way of entering
the desired input. It is the fundamental building block in constructing flip-flops, as explained in the

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following sections

NAND latch (Active-Low)

NAND latch is the fundamental building block in constructing a flip-flop. It has the property of
holding on to any previous output, as long as it is not disturbed. The operation of NAND latch is the
reverse of the operation of NOR latch. If 0‘s are replaced by 1‘s and 1‘s are replaced by 0‘s .

Operation

1) If 𝑹 =𝑺 = 𝟏
The inputs are Rand 𝑆. Hence there are four conditions:

 Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1). So its output
is 𝑄 = 0. The inputs to the gate 2 are (0,1). So its output is 𝑄̅ = 1. (The output does not change).
 Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (1,0). So its output
is 𝑄 = 1. The inputs to the gate 2 are (1,1). So its output is 𝑄̅ = 0. (The output does not change).
That is, if 𝑅= 𝑆= 1, there is no change in the output.

2) If 𝑹 =𝟏,𝑺 =𝟎
 Let the previous state output be 𝑄=0 (𝑄=1).̅ The inputs to the gate 1 are (0,1). So its output
is 𝑄=1. The inputs to the gate 2 are (1,1). So its output is 𝑄=0.
̅
 Let the previous state output be 𝑄=1 (𝑄=0).̅ The inputs to the gate 1 are (0,0). So its output
is 𝑄=1. The inputs to the gate 2 are (1,1). So its output is 𝑄=0.
̅
That is, if 𝑅=1,=0, the output is set (𝑄=1)

3) If 𝑹 =𝟎,𝑺 =𝟏
 Let the previous state output be 𝑄=0 (𝑄=1). ̅ The inputs to the gate 1 are (1,1). So its output is
𝑄=0. The inputs to the gate 2 are (0,0). So its output is 𝑄=1.
̅
 Let the previous state output be 𝑄=1 (𝑄=0). ̅ The inputs to the gate 2 are (1,0). So its output is
𝑄=1.
̅ The inputs to the gate 1 are (1,1). So its output is 𝑄=0.
That is, if 𝑅=0,=1, the output is reset (𝑄=0).

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4) If 𝑹 =𝑺 =𝟎
 Let the previous state output be 𝑄=0 (𝑄=1).
̅ The inputs to the gate 1 are (0,1). So its output is
𝑄=1. The inputs to the gate 2 are (1,0). So its output is 𝑄=1.
̅ Here 𝑄=1 and 𝑄=1, ̅ which is not
possible. So the output is not valid.
 Let the previous state output be 𝑄=1 (𝑄=0). ̅ The inputs to the gate 1 are (0,0). So its output is
𝑄=1. The inputs to the gate 2 are (1,0). So its output is 𝑄=1.̅ Again 𝑄=1 and 𝑄=1,
̅ which is not
possible. So the output is not valid.
That is, if 𝑅=
̅ 𝑆=0, the output is not valid. Hence this is forbidden.

Considering all the four cases, the truth table is written as below
Truth Table:

� � 𝑸𝒏 𝑸𝒏+𝟏 State � S 𝑸𝒏+𝟏 State

� � �
1 1 0 0 1 1 No change
No change 𝑄𝑛
1 1 1 1
1 0 1 Set
1 0 0 1
Set 0 1 0 Reset
1 0 1 1
Forbidden
0 1 0 0 0 0 ?
Reset (Illegal)
0 1 1 0
0 0 0 ? Forbidden
0 0 1 ? (Illegal)

Qn: Present state output Qn+1: Next state output

NOR latch(Active –High)

Operation:
The inputs are 𝑅 and 𝑆. Hence there are four conditions:

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i. If 𝑹 = 𝑺 = 𝟎
 Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (0,1). So its output
is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
 Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (0,0). So its output
is 𝑄 = 1. The inputs to the gate 2 are (1,0). So its output is 𝑄̅ = 0.
That is, if 𝑅 = 𝑆 = 0, there is no change in the output.
ii. If 𝑹 = 𝟎, 𝑺 = 𝟏
 Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 2 are (0,1). So its output
is 𝑄̅ = 0. The inputs to the gate 1 are (0,0). So its output is 𝑄 = 1.
 Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (0,0). So its output
is 𝑄 = 1. The inputs to the gate 2 are (1,1). So its output is 𝑄̅ = 0.
That is, if 𝑅 = 0, 𝑆 = 1, the output is set (𝑄 = 1).
iii. If 𝑹 = 𝟏, 𝑺 = 𝟎
 Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1). So its output
is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
 Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (1,0). So its output
is 𝑄 = 0. The inputs to the gate 2 are (0,0). So its output is 𝑄̅ = 1.
That is, if 𝑅 = 1, 𝑆 = 0, the output is reset (𝑄 = 0).
iv. If 𝑹 = 𝑺 = 𝟏
 Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 1 are (1,1). So its output
is 𝑄 = 0. The inputs to the gate 2 are (0,1). So its output is 𝑄̅ = [Link] 𝑄 = 0 and 𝑄̅ = 0, which
is not possible. So the output is not valid.
 Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 1 are (1,0). So its output
is 𝑄 = 0. The inputs to the gate 2 are (0,1). So its output is 𝑄̅ = [Link] 𝑄 = 0 and 𝑄̅ = 0,
which is not possible. So the output is not valid.
That is, if 𝑅 = 𝑆 = 1, the output is not valid. Hence this is forbidden

Considering all the four cases, the truth table is written as below.
Truth Table:

𝑸𝒏+𝟏
� 𝑺 𝑸 State 𝑹 � 𝑸𝒏+𝟏 State
� 𝒏 �
0 0 0 0 0 0 No change
No change 𝑄𝑛
0 0 1 1
0 1 1 Set
0 1 0 1
0 1 1 1 Set 1 0 0 Reset
1 0 0 0
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1 0 1 0
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1 1 0 ? Forbidden
1 1 1 ? (Illegal)
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Forbidden
1 1 ? (Illegal)

𝑄𝑛 - Present state output

𝑄𝑛+1 - Next state output

Flip-Flops
A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are fundamental
building blocks of digital electronics systems used in computers, communications, and many other
types of systems. Flip-flops and latches are used as data storage elements. It is the basic storage
element in sequential logic.

SR FLIP FLOP
The S-R flip-flop is the basic flip-flop among all the flip-flops. All the other flip flops are
developed after [Link] flip flop is represented as shown below

Fig. Clocked SR Flip-Flop (Gated SR Flip-Flop)

Operations:
The inputs are S and R. The gates 3 and 4 form a NAND gate latch.
When the clock is HIGH, the outputs of gates 1 and 2 are 𝑆and 𝑅 respectively. So the latch
operates normally.
When the clock is LOW, the output of the gates 1 and 2 are (1,1), which implies that the
output does not change and the latch is said to be disabled.

If 𝑪𝑳𝑲 = 𝟏 and 𝑹 = 𝑺 = 𝟎
The operation can be analyzed for the following conditions:
i.
In this case, the outputs of gates 1 and 2 are (1,1) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (1,1). So its output is 𝑄 =
0. The inputs to the gate 4 are (0,1). So its output is 𝑄̅ = 1. (The output does not change).

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Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (1,0). So its output is 𝑄 =
1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0. (The output does not change).
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 𝑆 = 0, there is no change in the output.
ii. If 𝑪𝑳𝑲 = 𝟏 𝐚𝐧𝐝 𝑹 = 𝟎, 𝑺 = 𝟏
In this case, the outputs of gates 1 and 2 are (0,1) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (0,1). So its output is 𝑄 =
1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (0,0). So its output is 𝑄 =
1. The inputs to the gate 4 are (1,1). So its output is 𝑄̅ = 0.
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 0, 𝑆 = 1, the output is set (𝑄 = 1).
iii. If 𝑪𝑳𝑲 = 𝟏 𝐚𝐧𝐝 𝑹 = 𝟏, 𝑺 = 𝟎
In this case, the outputs of gates 1 and 2 are (1,0) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (1,1). So its output is 𝑄 =
0. The inputs to the gate 4 are (0,0). So its output is 𝑄̅ = 1.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 4 are (1,0). So its output is 𝑄̅ =
1. The inputs to the gate 3 are (1,1). So its output is 𝑄 = 0.
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 1, 𝑆 = 0, the output is reset (𝑄 = 0).
iv. If 𝑪𝑳𝑲 = 𝟏 𝐚𝐧𝐝 𝑹 = 𝑺 = 𝟏
In this case, the outputs of gates 1 and 2 are (0,0) respectively.
Let the previous state output be 𝑄 = 0 (𝑄̅ = 1). The inputs to the gate 3 are (0,1). So its output is 𝑄 =
1. The inputs to the gate 4 are (1,0). So its output is 𝑄̅ = 1.
Here 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
Let the previous state output be 𝑄 = 1 (𝑄̅ = 0). The inputs to the gate 3 are (0,0). So its output is 𝑄 =
1. The inputs to the gate 4 are (1,0). So its output is 𝑄̅ = 1.
Again 𝑄 = 1 and 𝑄̅ = 1, which is not possible. So the output is not valid.
That is, if 𝐶𝐿𝐾 = 1 and 𝑅 = 𝑆 = 1, the output is not valid Hence this is forbidden.
v. If 𝑪𝑳𝑲 = 𝟎
In this case, the output of the gates 1 and 2 are (1,1), which implies that the output does not change and
the latch is said to be disabled.
Considering all the cases, the truth table is written as below.
Truth Table:
𝑪𝑳 𝑹 𝑺 𝑸 𝑸𝒏+𝟏
𝑪𝑳 � 𝑄 - Present
� 𝑸𝒏+
𝑲 𝒏
State
𝑛
𝑲 �
state outputState
𝟏
𝑄𝑛+1-
�
𝑄
1 0 Next0state output
0 0
𝑛
No change 1 0 0 No change
1 0 0 1 1
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0 1 Applications
1 Set
1 0 1 0
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1 0 1 1 1 Set 1 1 0 0 Reset

1 1 0 0 0 Forbidden
1 1 0 1 0 Reset 1 1 1 ? (Illegal)

1 1 1 0 ? Forbidden 0 X X 𝑄𝑛 No change
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X – Don’t care(May be 0 or 1)

JK Flip-Flop
The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a universal
flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the shortened abbreviated
letters for Set and Reset, but J and K are not. The J and K are themselves autonomous letters which
are chosen to distinguish the flip flop design from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J' and 'K' flip
flop instead of 'S' and 'R'. The only difference between JK flip flop and SR flip flop is that when both
inputs of SR flip flop is set to 1, the circuit produces the invalid states as outputs, but in case of JK flip
flop, there are no invalid states even if both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry. The invalid or
illegal output condition occurs when both of the inputs are set to 1 and are prevented by the addition
of a clock input circuit. So, the JK flip-flop has four possible input combinations, i.e., 1, 0, "no change"
and "toggle".

 When J=0 and K=0: The output (Q) remains the same as its previous state, maintaining the
current state (No change).
 When J=0 and K=1: The output (Q) becomes 0, regardless of its previous state (Reset).
 When J=1 and K=0: The output (Q) becomes 1, regardless of its previous state (Set).
 When J=1 and K=1: The output (Q) toggles to its complement (Complement).
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The key feature of the JK flip-flop is its ability to toggle when both J and K are set to 1. This is not
present in other types of flip-flops like the SR flip-flop. This makes the JK flip-flop very versatile and
useful in various applications including counters, shift registers, and memory storage circuits.

D Flip-Flop

In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and RESET = "0" is
forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input remains "0" by which
the resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter between the Set and
Reset inputs for producing another type of flip flop circuit called D flip flop, Delay flip flop, D-type
Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures that at the same
time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-flop is designed using a gated SR
flip-flop with an inverter connected between the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-type or D flip flop is
constructed from a level-sensitive SR flip flop. So, here S=D and R= ~D(complement of D)

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In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set
to 1, the flip flop would be set, and when it is set to 0, the flip flop would change and become
reset.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip flop's
latching circuitry. When the clock input is set to true, the D input condition is only copied to the
output Q. This forms the basis of another sequential device referred to as D Flip Flop.

Working

 D flip flop will work depending on the clock signal.

 When the clock is low there will be no change in the output of the flip flop i.e. it remembers the
previous state.

 When the clock signal is high and if it receives any data on its data pin, it Changes the state of output.
 When data is high Q reset to 0,while Q is set to 0 if data is low.

T Flip-Flop

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single input called
"Toggle" or "Trigger" input to avoid an intermediate state occurrence. Now, this flip-flop work as a
Toggle switch. The next output state is changed with the complement of the present state output.
This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip Flop" has only
one input, which is constructed by connecting the input of JK flip flop. This single input is called T. In
simple words, we can construct the "T Flip Flop" by converting a "JK Flip Flop". Sometimes the "T
Flip Flop" is referred to as single input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK defines the
clock signal input.

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Operations of T-Flip Flop

The operation of the T flip flop is explained below:

1. When the T input is low, then the next sate of the T flip – flop is same as the present
state i.e. it holds the current state.
 T = 0 and present state = 0 then the next state = 0.
 T = 0 and present state = 1 then the next state = 1.
2. When the T input is high, then the next sate of the T flip – flop is toggled i.e. it is same as
the complement of present state on clock transition.
 T = 1 and present state = 0 then the next state = 1.
 T = 1 and present state = 1 then the next state = 0.
Input Previous Output Statement Next Output Statement
Clk T QN QN QN+1 QN+1
0 1 0 Set 1 0 Set
0 0 1 Reset 0 1 Reset
1 1 0 Set 0 1 Reset
1 0 1 Reset 1 0 Set

Comparison between Latches and Flip-Flops

LATCH FLIP- FLOP

[Link] do not require clock signal [Link] – flops have clock signals
2. A latch is an asynchronous device. 2.A flip-flop is a synchronous device
3. Latches are transparent devices i.e. 3. A transition from low to high or high to low
when they are enabled, the output of the clock signal will cause the flip-flop to
changes immediately if the input either change its output or retain it depending
changes. on the input signal.
4. A latch is a level sensitive device. 4.A flip-flop is an edge sensitive device (Edge
(Level triggering is involved) triggering is involved)
5. Latches are simpler to design as there 5. When compared to latches, flip flops are
is no clock signal (no careful routing of more complex to design as they have clock
clock signal is required). signal and it has to be carefully routed. This is
because all the flip flops in a design should have
a clock signal and the delay in the clock
reaching each flip-flop must be minimum or
negligible.
6. The operation of a latch is faster as 6. Flip – flops are comparatively slower than
they do not have to wait for any clock latches due toclock signal.
signal.
7. The power requirement of a latch is 7. Power requirement of flip-flop is more.
less.
8. A latch works based on the enable 8. A flip-flop works based on the clock signal.
signal.
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Clock Signal and Triggering

What is a clock pulse?

A clock pulse is a continuously changing signal that oscillates between a high state and a low state.
The common type of clock signal is a square type, which has 50% duty cycle with a fixed and constant
frequency. A clock pulse is shown below.

The pattern repeats with some time period. In this case, the time period will be equal to either
twice of ON time or twice of OFF time. The reciprocal of the time period of clock signal is known as
the frequency of the clock signal.

All sequential circuits are operated with clock signal. So, the frequency at which the sequential circuits
can be operated accordingly the clock signal frequency has to be chosen.

Types of Triggering

Following are the two possible types of triggering that are used in sequential circuits.

Level triggering
Edge triggering

Level triggering

There are two levels, namely logic High and logic Low in clock signal. Following are the two types of
level triggering.
 Positive/High level triggering
 Negative/Low level triggering

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 If the sequential circuit is operated with the clock signal when it is in Logic High, then that
type of triggering is known as Positive/High level triggering. It is highlighted in below
figure

 If the sequential circuit is operated with the clock signal when it is in Logic Low, then that type
of triggering is known as Negative/Low level triggering. It is highlighted in the following
figure.

Edge triggering
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There are two types of transitions that occur in clock signal. That means, the clock signal transitions
either from Logic Low to Logic High or Logic High to Logic [Link] are the two types of edge
triggering based on the transitions of clock signal.

 Positive edge triggering

 Negative edge triggering

 If the sequential circuit is operated with the clock signal that is transitioning from Logic
Low to Logic High, then that type of triggering is known as Positive edge triggering. It is
also called as rising edge triggering. It is shown in the following figure.

 If the sequential circuit is operated with the clock signal that is transitioning from Logic
High to Logic Low, then that type of triggering is known as Negative edge triggering. It is
also called as falling edge triggering. It is shown in the following figure.

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Registers
A group of flip-flips connected together forms a register. A register is used solely for storing
and shifting data which is in the form of 1's and 0's entered from an external source. The Binary
information in a register can be moved from stage to stage within the register or into or out of the
register upon application of clock pulses. This type of bit movement or shifting essential for certain
arithmetic and logic operations used in microprocessors. This gives rise to a group of registers
called Shift Registers. They are very important in applications involving the storage and transfer of
data in a digital system.
Shift Registers:
Shift register is a sequential logic circuit whose output is depends on present input as well
as past [Link] register consists of group of same type of [Link] register is used to store
group of binary data and also used to shift the binary [Link] total number of flip-flop present in
shift register are depends on the total number of binary bits stored in shift register.
If we have to store two bit binary data i.e 00,01,10,11 then shift register require two flip-
[Link] we have to store three bit binary data i.e 000,001,010,011 upto 111 then shift register
require three [Link] we have to store four bit binary data i.e 0000, 0001, 0010, 0011 upto
1111 then shift register require four flip- [Link] according to the logic, if we have to store „N‟
bit binary data then shift register require „N‟ no of flip-flops.
Shift Registers consists of a number of single bit "D-Type Data Latches" connected together
in a chain arrangement so that the output from one data latch becomes the input of the next latch
and so on, thereby moving the stored data serially from either the left or the right direction.
The number of individual Data Latches used to make up Shift Registers are determined by
the number of bits to be stored with the most common being 8-bits wide. Shift Registers are
mainly used to store data and to convert data from either a serial to parallel or parallel to serial
format with all the latches being driven by a common clock (Clk) signal making them Synchronous
device.

Generally, Shift Registers operate in one of four different modes:

 Serial-in to Parallel-out (SIPO)
 Serial-in to Serial-out (SISO)
 Parallel-in to Parallel-out (PIPO)
 Parallel-in to Serial-out (PISO)
Functions of Shift Register
Shift register is used to store group of binary data and also used to shift the binary data. Or
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Data Storage and Data Movement.

Modes of Shift Register

Left shift mode and Right shift mode

 Serial Input /Serial Output Shift Register(SISO)

This shift register allows serial input and produces a serial output. As there is only one output, it
delivers 1 bit at a time in a serial pattern. A 4-bit shift register using D flip-flops is illustrated below,
with all flip flops connected in a serial manner and synchronized by the same clock signals.

 Initially, all flip flops are in a reset condition (Q3=Q2=Q1=Q0=0). If the input data series is 1111,
the first LSB bit (1) is considered as Din and is applied to the input of the first flip flop (D3). The
output of the first flip flop is connected to the input of the second flip flop, and so on. The stored
word in the register is updated on each falling edge of the clock signal, resulting in a sequential
output.

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 Before applying the clock signal, the output is initialized to Q3Q2Q1Q0=0000. Upon applying the
clock signal, during the first falling edge of the clock, Flip-Flop 3 (FF3) is triggered, updating the
stored word in the register to Q3Q2Q1Q0=1000.

 Subsequently, at the next negative edge of the clock, Flip-Flop 2 (FF2) is set, leading to a
modification of the stored word to Q3 Q2 Q1 Q0=1100.

 Upon the occurrence of the third negative clock edge, Flip-Flop 1 (FF1) is activated, resulting in
an output modification to Q3 Q2 Q1 Q0=1110.

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 Finally, with the arrival of the fourth negative clock edge, the stored word in the register
becomes Q3 Q2 Q1 Q0=1111.

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Truth Table:

Clock Data Q3 Q2 Q1 Q0 Data

Pulse Input Output
0 0 0 0

1 1 0 0 0

1 1 1 0 0

1 1 1 1 0

1 1 1 1 1 1

0 1 1 1 1

0 0 1 1 1

0 0 0 1 1

 Serial Input/Parallel Output Shift Register(SIPO)

The Serial-In-Parallel-Out (SIPO) shift register facilitates serial input and generates a parallel output.
Illustrated below is a 4-bit SIPO shift register utilizing D flip-flops, where each flip- flop is
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interconnected in a serial fashion and synchronized by identical clock signals The output of one flip-
flop is linked to the input of the subsequent flip-flop, forming a serial chain.

 Initially, all flip-flops are reset to Q3=Q2=Q1=Q0=0. Taking a 4-bit input data series, such as
1011, the first Least Significant Bit (LSB) bit (0) is considered as “Din” and is applied to the
input of the initial flip-flop. Each flip-flop’s output is connected to a parallel output. The
register’s stored word is updated with each falling edge of the clock signal, resulting in a
parallel output.

 To commence, all flip-flops are set to a reset state: Q3 Q2 Q1 Q0 = 0000. Applying the first
serial input bit (1) to the first flip-flop’s input, on the falling edge of the clock, the first flip- flop
is triggered, latching the data. The shift register now holds Q3 Q2 Q1 Q0 = 1 0 0 0.

 Subsequently, applying the second serial input bit (1) to the first flip-flop’s input, the first flip-
flop is triggered again on the falling edge of the clock, and the data is latched. The shift register
now holds Q3 Q2 Q1 Q0 = 1 1 0 0.

 Continuing the process for the third and fourth serial input bits (0 and 1), after each clock edge,
the shift register holds:
Clock Edge 3: Q3 Q2 Q1 Q0 = 0 1 1 0.
Clock Edge 4: Q3 Q2 Q1 Q0 = 1 0 1 1.

 After all four clock edges, the final parallel output is Q3 Q2 Q1 Q0 = 1011. This iterative process
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ensures that the parallel output consistently represents the entire serial input data stream

 SIPO shift registers find common application when there is a need to convert a serial data stream
into a parallel format for subsequent processing in a digital system.

 Parallel Input/Serial Output Shift Register(PISO)

The Parallel-In-Serial-Out (PISO) shift register is a digital circuit that accepts parallel input data and
produces a serial output. In contrast to the Serial-In-Parallel-Out (SIPO) shift register, the PISO
configuration is useful when data needs to be shifted out serially while being presented in parallel at the
input. Consider a 4-bit PISO shift register using D flip-Flop.

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 Initially, all flip-flops are reset (Q3=Q2=Q1=Q0=0). If the parallel input data is 1011, each bit is
simultaneously applied to the corresponding flip-flop inputs. Illustrated below is a 4-bit SIPO
shift register utilizing D flip-flops. Here, Output of previous Flip Flop is connected to the input of
the next one via a combinational circuit. Here we also have shift/Load bar terminal in the circuit
digaram.

 In Parallel-In-Serial-Out (PISO) shift registers, there are two primary modes of operation: the
“load” mode and the “shift” mode. These modes determine how data is handled in the shift
register.

 Let’s consider a 4-bit PISO shift register in both load and shift modes:

1. Load Mode:
In the load mode, the PISO shift register accepts parallel input data. During this mode, the
parallel input data is loaded into the flip-flops simultaneously. Each flip-flop stores one bit of
the parallel input data. This mode is typically activated by a control signal (e.g., Load/Shift
control). Initialize all flip-flops to a reset state: Q3 Q2 Q1 Q0 = 0000. Apply parallel input data
(e.g., 1011) to the flip-flop [Link] the load control signal. On the rising or falling edge of the
clock, the parallel input data is loaded into the flip-flops.
Result after load: Q3 Q2 Q1 Q0 = 1011.
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2. Shift Mode:
In the shift mode, the PISO shift register shifts the stored data out serially. The stored parallel
data is shifted out bit by bit, starting from the Most Significant Bit (MSB) to the Least Significant
Bit (LSB).This mode is activated by a different control signal or the absence of a load signal. The
shifting occurs on each clock edge, either rising or falling, depending on the [Link]
the load control signal (or activate the shift control signal). On each subsequent clock edge, the
stored data is shifted out serially. Result after shift: Serial output = 1011.

 Now, let’s delve into the operational transition of the combinational circuit as it switches from
the load mode to the shift mode.

 In the configuration, there is a Shift/Load bar terminal with two lines, one of which is
connected to a NOT gate, providing inverse inputs to both lines A circuit, comprising one OR
gate and two AND gates, is interlinked. Pay close attention to the connections: notice how the
output of the first flip-flop is linked to the input of an AND gate, and how the Shift/Load lines
are connected to the AND gates, along with input lines B3, B2, B1, and B0. Initially, the shift
register operates in load mode to load the data. For the Parallel-In-Serial- Out (PISO) shift
register to function in load mode, the Shift/Load bar input must be 0, and for it to operate in
shift mode, it must be 1.
 Refer to the diagram below, where the AND gates receive input values based on the shift/load
input. Following the logic of AND gates, if any input is 0, the output is 0. Consequently, the
output of AND gates 1, 3, 5 will be 0. Conversely, if any input is 1, the other terminal serves as
the output. Thus, the output of AND gates 2, 4, 6 will be B2, B1, B0, respectively. Following the
logic of the OR gate, the output of OR gate 1, 2, 3 will be B2, B1, B0, respectively. This output is
then fed into the input of the flip-flop. Flip-flop 1 directly takes the input B3. This process
facilitates loading the input B3B2B1B0 into the flip-flops Subsequently, after the clock input,
the input data is available at the output, resulting in Q3Q2Q1Q0 = B3B2B1B0

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 During shift mode, the Shift/Load bar terminal is set to 1. The diagram illustrates how the AND
gates receive inputs based on the shift/load line inputs. According to the AND gate’s operation,
the output of AND gates 2, 4, 6 will be 0, and the output of AND gates 1, 3, 5 will be Q3Q2Q1.
Following the OR gate’s logic, the output of OR gate 1, 2, 3 will be Q3Q2Q1, respectively. This
output is then connected to the input of the flip-flop, facilitating the shift of data in the PISO shift
register.

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 Parallel Input/Parallel Output Shift Register(PIPO)

A Parallel-In-Parallel-Out (PIPO) shift register is a type of digital shift register that allows
parallel input data to be loaded into the register and simultaneously produces parallel output data.
Unlike Serial-In-Serial-Out (SISO) or Parallel-In-Serial-Out (PISO) shift registers, a PIPO shift register
enables parallel transfer of data both at the input and output.
Here’s a brief overview of how a 4-bit PIPO shift register works:

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 Initially, all flip-flops in the PIPO shift register are set to a reset state (Q3 Q2 Q1 Q0 = 0000).
Apply the parallel input data (D3 D2 D1 D0) to the respective inputs of each flip-flop. Each flip-
flop stores one bit of the parallel input data. On the rising or falling edge of the clock signal
(depending on the design), the parallel input data is latched into the flip-flops simultaneously.

 The data in all flip-flops are available simultaneously at the parallel outputs (Q3 Q2 Q1 Q0). The
PIPO shift register retains the parallel data until new parallel data is provided and clocked in.

 A key characteristic of the PIPO shift register is its ability to perform parallel transfers at both
the input and output stages. This makes it suitable for applications where parallel data needs to
be maintained and processed concurrently.

 Bidirectional Shift Register:

A bidirectional shift register is a sequential logic circuit that can shift data in both directions
left and right, depending on the control signals. A 4-bit Bidirectional shift register using D flip-flops is
illustrated below. This versatile circuit adapts its behavior based on the value of “M,” where M=1
designates operation as a Shift Right Register, and M=0 configures it as a Shift Left Register.

Examine the connections closely, particularly focusing on the intricate relationship between the
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output of the first flip-flop and the input of an AND gate. Additionally, observe how the control signal
lines, denoted by “M,” intricately interface with the AND gates. These connections are meticulously
designed to ensure precise control over the bidirectional shift register’s functionality
 M=1 (Shift Right Register):

When the control signal, denoted as “M,” is set to 1, the bidirectional shift register operates as a
Shift Right Register.

Refer to the diagram above, where the AND gates receive input values based on the control signal
“M.” Applying the logic of AND gates, if any input is 0, the output is 0. Consequently, the outputs of
AND gates 2, 4, 6, and 8 will be 0. Conversely, if any input is 1, the opposite terminal serves as the
output. Thus, the outputs of AND gates 1, 3, 5, and 7 will be DR, Q3, Q2, and Q1, respectively.
Following the logic of the OR gate, the outputs of OR gates 1, 2, 3, and 4 will be DR, Q3, Q2, and Q1,
respectively. This collective output is then directed into the input of the flip- flop. Consequently, the
data undergoes a rightward shift, effectively realizing the functionality of a Shift Right Register.

 M=0 (Shift Left Register):

Conversely, when the control signal “M” is set to 0, the bidirectional shift register transforms into a
Shift Left Register.

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Refer to the diagram above, where the AND gates once again receive input values based on the
control signal “M.” Employing the AND gate logic, if any input is 0, the output is [Link], the
outputs of AND gates 1, 3, 5, and 7 will be 0. Conversely, if any input is 1, the opposite terminal
becomes the output. Thus, the outputs of AND gates 2, 4, 6, and 8 will be Q2, Q1, Q0, and DL,
respectively. Following the logic of the OR gate, the outputs of OR gates 1, 2, 3, and 4 will be Q2, Q1,
Q0, and DL, respectively. Subsequently, this combined output is fed into the input of the flip-flop. In
this manner, the data experiences a leftward shift, effectively embodying the characteristics of a Shift
Left Register

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DIGITAL FUNDAMENTALS

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