DIGITAL DESIGN
ASSIGNMENT-1
NAME: - [Link]
ROLL NO: -B24EC208L
1. Develop and simulate TTL Logic NOR circuit for yielding high speed using OrCAD/ PSpice
simulator.
ANS:
Step-by-Step Procedure in OrCAD/PSpice
1. Components Required
• 2 × NPN transistors (e.g., Q2N2222)
• 2 × Input voltage sources
• 2 × Base resistors (1kΩ)
• 1 × Pull-up resistor (1kΩ)
• 1 × Ground (GND)
• 1 × VCC (5V)
2. Circuit Connection Overview
• Inputs (A & B) go through resistors to base of each transistor (Q1 and Q2).
• Emitters of both transistors are connected to ground.
• Collectors are joined and pulled to VCC (5V) via a resistor.
• Output is taken from the joined collectors.
[Link]
* TTL NOR Gate Simulation
VCC 1 0 DC 5V
VIN1 2 0 PULSE (0 5 0ns 1ns 1ns 10ns 20ns)
VIN2 3 0 PULSE (0 5 0ns 1ns 1ns 20ns 40ns)
R1 2 4 1k
R2 3 5 1k
Q1 6 4 0 Q2N2222
Q2 6 5 0 Q2N2222
RL 1 6 1k
. model Q2N2222 NPN (IS=1E-14 BF=100)
.tran 0.1ns 100ns
. control
run
plot V (2) V (3) V (6)
. endc
. end
[Link]
• Output will show HIGH (5V) only when both inputs are LOW.
• When either A or B is HIGH, transistor conducts → output pulled LOW → NOR
behavior.
2. Model and simulate RTL Logic 2- input NAND gate circuit for yielding low power using
OrCAD/ PSpice simulator.
Ans:
1. Components Required
• 2 × Resistors for input bias (10kΩ typical)
• 1 × Pull-up resistor (10kΩ typical)
• 1 × NPN transistor (e.g., Q2N2222)
• 2 × Input pulse sources
• 1 × Ground
• 1 × VCC (5V)
2. Circuit Description
This design uses two input resistors tied to one transistor:
• Inputs A and B go through resistors and are wired together to the base of the NPN
transistor.
• The emitter goes to GND.
• The collector is pulled up to Vcc through a resistor.
• Output is taken from the collector.
• NAND behavior is achieved because:
• If both inputs are HIGH → base gets enough current → transistor turns ON → output
is LOW.
• Otherwise → transistor OFF → output pulled HIGH.
[Link]
* RTL NAND Gate Simulation
VCC 1 0 DC 5V
VIN1 2 0 PULSE(0 5 0ns 1ns 1ns 10ns 20ns)
VIN2 3 0 PULSE(0 5 0ns 1ns 1ns 20ns 40ns)
R1 2 4 10k
R2 3 4 10k
Q1 5 4 0 Q2N2222
RL 1 5 10k
.model Q2N2222 NPN(IS=1E-14 BF=100)
.tran 0.1ns 100ns
.control
run
plot V(2) V(3) V(5)
.endc
.end
4. Output
• HIGH output (5V) if either input is LOW.
• LOW output (0V) only when both A and B are HIGH.
3. Inspect and plot the dynamic characteristics of 2-input NAND/NOR based on CMOS
static logic using EDA Tools.
Ans:
CMOS NAND / NOR Gate Basics
• CMOS NAND: 2 PMOS in parallel + 2 NMOS in series
• CMOS NOR: 2 PMOS in series + 2 NMOS in parallel
the plot shows the dynamic characteristics of CMOS NAND and NOR gates:
• Top Plot: Input signals A and B as pulse waveforms
• Middle Plot: Output of a 2-input CMOS NAND gate (only LOW when both A and B are HIGH)
• Bottom Plot: Output of a 2-input CMOS NOR gate (only HIGH when both A and B are LOW)
4. Consider the following logic families
(i) Standard TTL Logic family
(ii) ECL Logic family
(iii)CMOS logic family
(iv)RTL logic family
Make use of MATLAB/Python/C-language program to characterize the logic
families in the order of decreasing power dissipation.
Ans:
# Power dissipation values in milliwatts (mW)
logic_families = {
"ECL": 25,
"TTL": 10,
"RTL": 5,
"CMOS": 0.01 # Very low, dynamic power only
# Sort logic families by power dissipation in descending order
sorted_families = sorted(logic_families.items(), key=lambda x: x[1], reverse=True)
# Print the result
print("Logic families ranked by decreasing power dissipation:\n")
for family, power in sorted_families:
print(f"{family}: {power} mW")
output:
Logic families ranked by decreasing power dissipation:
ECL: 25 mW
TTL: 10 mW
RTL: 5 mW
CMOS: 0.01 mW
5. a) Examine the average power dissipation for the gate supplied by a 5V
power supply using with I(OH)=0.8mA and I(OL)=2.8mA using
MATLAB/Python/C-language program
b) The gate of above has propagation delay times of tPHL=1ns and tPLH=2.8ns.
Examine the power-delay product for this gate using MATLAB/Python/Clanguage program.
Ans:
# Given values
Vcc = 5 # volts
I_OH = 0.8e-3 # 0.8 mA to A
I_OL = 2.8e-3 # 2.8 mA to A
# Part (a) - Average Power Dissipation
P_avg = Vcc * (I_OH + I_OL) / 2
print(f"(a) Average Power Dissipation: {P_avg:.6f} Watts")
# Part (b) - Power-Delay Product
tPHL = 1e-9 # seconds
tPLH = 2.8e-9 # seconds
tpd_avg = (tPHL + tPLH) / 2
PDP = P_avg * tpd_avg
print(f"(b) Power-Delay Product (PDP): {PDP:.15f} Joules")
output
(a) Average Power Dissipation: 0.009500 Watts
(b) Power-Delay Product (PDP): 0.000000000042750 Joules
6. Model and simulate a program to calculate the total number of fuses required to implement a
given Boolean function on PLA using a MATLAB/python/C program (as per the user specifications).
[Hint: read the required data through the input from the user]
Ans:
def get_input():
# Get the number of variables in the Boolean function
num_variables = int(input("Enter the number of variables: "))
# Get the Boolean expression in Sum-of-Products (SOP) form
print(f"Enter the Boolean function as a sum of products (SOP) for {num_variables} variables:")
boolean_expr = input("Example: A'B + AB' + ABC (each product term separated by +): ")
return num_variables, boolean_expr
def calculate_fuses(num_variables, boolean_expr):
# Split the Boolean expression into individual product terms
product_terms = boolean_expr.split('+')
# The number of fuses in the AND plane is equal to the number of variables in each term.
# Each term represents an AND gate in the AND plane.
and_fuses = 0
or_fuses = len(product_terms)
for term in product_terms:
and_fuses += len([Link]("'", "")) # Count the number of variables in the term (ignoring
negations)
# Calculate the total number of fuses: fuses in AND plane + fuses in OR plane
total_fuses = and_fuses + or_fuses
return and_fuses, or_fuses, total_fuses
def main():
num_variables, boolean_expr = get_input()
and_fuses, or_fuses, total_fuses = calculate_fuses(num_variables, boolean_expr)
# Display the results
print("\nFuses required:")
print(f"Fuses in AND plane: {and_fuses}")
print(f"Fuses in OR plane: {or_fuses}")
print(f"Total fuses required: {total_fuses}")
if __name__ == "__main__":
main()
output
Enter the number of variables: 3
Enter the Boolean function as a sum of products (SOP) for 3 variables:
Example: A'B + AB' + ABC (each product term separated by +): A'B + AB' + ABC
Fuses required:
Fuses in AND plane: 6
Fuses in OR plane: 3
Total fuses required: 9
7. Model an additional logic required to give a no-match result for a word in an associative
memory when all key bits are zeros using a MATLAB/python/Cprogram.
Ans:
def check_zero_key(key):
# Check if all bits in the key are zeros
if all(bit == '0' for bit in key):
return True
return False
def associative_memory_match(memory, key):
# Check if the key is all zeros
if check_zero_key(key):
return "No Match (key is all zeros)"
# Otherwise, try to match the key with stored memory
for i, stored_key in enumerate(memory):
if stored_key == key:
return f"Match found at index {i}"
# If no match is found
return "No Match"
def main():
# Input memory keys and the query key
memory = input("Enter the memory keys (comma separated): ").split(',')
key = input("Enter the key to search: ")
# Perform the matching
result = associative_memory_match(memory, key)
print(result)
if __name__ == "__main__":
main()
output
Enter the memory keys (comma separated): 101, 110, 011
Enter the key to search: 000
No Match (key is all zeros)
8. Examine the following using a MATLAB/python/C-program.
A computer uses RAM chips of 2048x1 capacity.
a. How many chips are needed, and how should their address lines be
connected to provide a memory capacity of 2048 bytes?
b. Inspect the number of chips is needed to provide a memory capacity of 8K
bytes?
Ans:
import math
def calculate_chips(memory_needed_bytes, chip_capacity_bytes):
# Calculate the number of chips needed
num_chips = memory_needed_bytes // chip_capacity_bytes
if memory_needed_bytes % chip_capacity_bytes != 0:
num_chips += 1 # Round up if there's a remainder
return num_chips
def calculate_address_lines(memory_size):
# Calculate the number of address lines needed
address_lines = int(math.log2(memory_size))
return address_lines
def main():
# Part (a)
chip_capacity_bytes = 256 # Each chip stores 256 bytes (2048 bits)
memory_needed_bytes_a = 2048 # 2048 bytes
num_chips_a = calculate_chips(memory_needed_bytes_a, chip_capacity_bytes)
address_lines_per_chip_a = calculate_address_lines(2048) # 2048 locations per chip
chip_select_lines_a = int(math.log2(num_chips_a)) # Number of chip select lines
print(f"Part (a):")
print(f"Number of chips needed for 2048 bytes: {num_chips_a}")
print(f"Address lines required per chip: {address_lines_per_chip_a}")
print(f"Chip selection lines required: {chip_select_lines_a}")
# Part (b)
memory_needed_bytes_b = 8192 # 8K bytes = 8192 bytes
num_chips_b = calculate_chips(memory_needed_bytes_b, chip_capacity_bytes)
print(f"\nPart (b):")
print(f"Number of chips needed for 8K bytes: {num_chips_b}")
if __name__ == "__main__":
main()
Output
Part (a):
Number of chips needed for 2048 bytes: 8
Address lines required per chip: 11
Chip selection lines required: 3
Part (b):
Number of chips needed for 8K bytes: 32
9. Examine the following using a MATLAB/python/C-program.
a. The number of 128x8 RAM chips are needed to provide a memory capacity
of 1024 bytes
b. The number of lines the address bus must be used to access 1024 bytes of
memory and lines common to all chips
c. Number of lines needed to decode for chip select and size of the decoders
Ans:
import math
def calculate_chips(memory_needed_bytes, chip_capacity_bytes):
# Calculate the number of chips needed
num_chips = memory_needed_bytes // chip_capacity_bytes
if memory_needed_bytes % chip_capacity_bytes != 0:
num_chips += 1 # Round up if there's a remainder
return num_chips
def calculate_address_lines(memory_size):
# Calculate the number of address lines needed
address_lines = int(math.log2(memory_size))
return address_lines
def main():
# Part (a)
chip_capacity_bytes = 128 # Each chip stores 128 bytes (128x8 bits)
memory_needed_bytes_a = 1024 # 1024 bytes
num_chips_a = calculate_chips(memory_needed_bytes_a, chip_capacity_bytes)
print(f"Part (a):")
print(f"Number of chips needed for 1024 bytes: {num_chips_a}")
# Part (b)
address_lines_needed_b = calculate_address_lines(memory_needed_bytes_a) # Address lines for
1024 bytes
address_lines_per_chip_b = calculate_address_lines(128) # Address lines per chip for 128 bytes
print(f"\nPart (b):")
print(f"Address lines needed to access 1024 bytes: {address_lines_needed_b}")
print(f"Address lines common to all chips: {address_lines_per_chip_b}")
# Part (c)
chip_select_lines_c = int(math.log2(num_chips_a)) # Chip select lines for 8 chips
decoder_size_c = chip_select_lines_c # Size of the decoder
print(f"\nPart (c):")
print(f"Chip select lines needed: {chip_select_lines_c}")
print(f"Size of the decoder: {decoder_size_c} lines")
if __name__ == "__main__":
main()
output
Part (a):
Number of chips needed for 1024 bytes: 8
Part (b):
Address lines needed to access 1024 bytes: 10
Address lines common to all chips: 7
Part (c):
Chip select lines needed: 3
Size of the decoder: 3 lines
10. Identify the transfer rate of an eight-track magnetic tape using MATLAB/python/C-program
whose speed is 150 inches per second and whose density is 1400 bits per inch.
Ans:
def calculate_transfer_rate(tape_speed, density, num_tracks):
# Calculate the transfer rate
transfer_rate = tape_speed * density * num_tracks
return transfer_rate
def main():
tape_speed = 150 # inches per second
density = 1400 # bits per inch
num_tracks = 8 # number of tracks
transfer_rate = calculate_transfer_rate(tape_speed, density, num_tracks)
print(f"Transfer rate of the eight-track magnetic tape: {transfer_rate} bits per second")
if __name__ == "__main__":
main()
Output:
Transfer rate of the eight-track magnetic tape: 1680000 bits per second