Digital Systems II Chapter I
Latches, Flip-flops, and Timers
INTRODUCTION
-In this chapter, we will cover the fundamentals of sequential
logic, Bistable, Monostable, and Astable logic devices called
multivibrators.
- Two categories of bistable devices are the Latches and the flip
flops, which have two stable state called set and reset
- They're useful storage devices since they can hold either state
continuously.
- Latches and flip-flops differ in how they change states.
-The flip-flop is a basic building block for counters, registers, and
other sequential control logic and is used in certain types of
memories.
-The astable multivibrator has no stable state and is used primarily
as an oscillator.
-Pulse oscillators are used as the sources for timing waveforms
in digital systems.
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1. LATCHES
-Latch, a temporary storage device with two stable states
(bistable), is usually classified separately from flip-flops.
- Latches are bistable devices that use feedback to switch
between two states like flip-flops.
A. S – R Latch
S-R (Set-Reset) latches are the most basic type. It can be built
from either NOR or NAND gates. With NOR gates, the latch
responds to inputs that are active-HIGH; with NAND gates, it
responds to inputs that are active-LOW.
Observe that the output of each gate is connected to the input of
the opposing gate. This produces the characteristic regenerative
feedback of all latches and flip-flops.
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Negative-OR below is equivalent to the S - R latch of the
NAND gate
logic symbol
Active High S – R Latch
The active-HIGH S-R latch is in a stable (latched) condition when
both inputs are LOW.
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• Assume the latch is initially RESET (Q = 0) and the
inputs are at their inactive level (0). To SET the latch
(Q = 1), a momentary HIGH signal is applied to the S
input while the R remains LOW.
• To RESET the latch (Q = 0), a momentary HIGH signal
is applied to the R input while the S remains LOW.
Input Output Comments
S R Q Q
0 0 NC NC No change latch remain on the present state
1 0 1 0 Latch set, Q = 1
0 1 0 1 Latch reset, Q = 0
1 1 ? ? Invalid
Active low 𝑆 − 𝑅 Latch
The active-low 𝑆 − 𝑅 latch is in a stable (latched) condition
when both inputs are HIGH.
• Suppose that the latch is initially RESET (Q = 0) and the
inputs are at their inactive level (1). To SET the latch (Q =
4
1), a transient LOW signal is applied to 𝑆 while 𝑅 remains
HIGH.
• To RESET the latch, a transient LOW signal is applied to 𝑅
input while 𝑆 remains HIGH.
-Never apply an active set and reset at the same time (invalid).
-Below is the truth table for an active LOW input 𝑆𝑅 ־latch.
The active-LOW 𝑆 − 𝑅 latch is available as the 74LS279A IC.
It has four internal latches, two of which have two 𝑆 inputs. To
SET a latch, the S line must be pulsed low. It is available in a
variety of packaging.
𝑆 − 𝑅 latches are frequently used for switch debounce circuits as
shown:
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An application
Mechanical switch contact "bounce" can be eliminated with 𝑆 −
𝑅 latch. When a switch closes, the pole hits the contact multiple
times before forming a firm contact. Although these bounces are
transient, they cause voltage spikes that are generally
unacceptable in digital systems.
The 𝑆 − 𝑅 latch used to eliminate switch contact bounce.
If the S and R waveforms (a) below are applied to the inputs of
the latch in Figure (b) logic symbol below, determine the
waveform that will be observed on the Q output. Assume that Q
is initially LOW.
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The waveform (b) shows the Q output
*Related problem
If the waveforms in Figure (a) above are inverted and applied to
the inputs, determine the Q output of an active-HIGH input S-R
latch. Draw the S-R latch logic symbol as well.
B. The Gated S-R Latch
-A gated latch requires an enable input, EN. The logic diagram
and logic symbol for a gated S-R latch are shown below.
-The S and R inputs control the state to which the latch will go
when a HIGH level is applied to the EN input.
-The latch will not change until EN is HIGH; but as long as it
remains HIGH, the output is controlled by the state of the S and
R inputs.
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-In this circuit, the invalid state occurs when both S and R are
simultaneously HIGH and EN is also HIGH.
Gated S-R latch
Determine the Q output waveform if the inputs presented in
waveform (a) are applied to a gated S-R latch that is initially
RESET.
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*Related problem
Determine the Q output of a gated S-R latch if the S and R inputs
are inverted in waveform (a).
C. The Gated D Latch
D latches are gated latches. It has one input besides EN, unlike
the S-R latch. D (data) input
When the D input is HIGH and the EN input is HIGH, the latch
will set. When the D input is LOW and EN is HIGH, the latch
will reset. Stated another way, the output Q follows the input D
when EN is HIGH.
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Determine the Q output waveform if the inputs shown below are
applied to a gated D latch, which is initially RESET.
*Related problem
Determine the Q output of the gated D latch if the D input in
waveform (a) above is inverted.
Implementation of D Gated latch
-The logic symbol below represents the gated D latch 74HC75 as
well as the truth table.
-The device has four latches. Notice that each active-HIGH EN
input is shared by two latches and is designated as a control input
(C).
-The X in the truth table represents a “don’t care” condition. In
this case, when the EN input is LOW, it does not matter what the
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D input is because the outputs are unaffected and remain in their
prior states.
The 74HC75 quad D latch.
2. FLIP – FLOPS
-Flip-flops are synchronous bistable multivibrators. In this
situation, synchronous implies that the output changes state only
at a predetermined point (leading or trailing edge) on the
triggering input, the clock (CLK), which is a control input, C.
-Flip-flops are edge-triggered or edge-sensitive whereas gated
latches are level-sensitive.
- The active edge can be positive or negative.
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Negative edge – triggered (b)
Positive edge- triggered (a)
D flip - flop Edge-Triggered logic symbols
The D input of the D flip-flop is a synchronous input because data
on the input are transferred to the flip-flop’s output only on the
triggering edge of the clock pulse. When D is HIGH, the Q output
goes HIGH on the triggering edge of the clock pulse, and the flip-
flop is set.
-The truth table for a negative-edge triggered D flip-flop is
identical except for the direction of the arrow.
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Logic symbol and waveform of D Flip -flop
-Determine the Q and Q output waveforms of the flip-flop in
Figure above for the D and CLK inputs waveform. Assume
that the positive edge-triggered flip-flop is initially RESET.
The J-K Flip flops
The J-K flip-flop is more versatile than the D flip flop. In addition
to the clock input, it has two inputs, labeled J and K. When both
J and K = 1, the output changes states (toggles) on the active clock
edge (in this case, the rising edge).
1. When J is HIGH and K is LOW, the Q output goes HIGH on
the triggering edge of the clock pulse, and the flip-flop is
SET.
2. When J is LOW and K is HIGH, the Q output goes LOW on
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the triggering edge of the clock pulse, and the flip-flop is
RESET.
3. When both J and K are LOW, the output does not change
from its prior state.
4. When J and K are both HIGH, the flip-flop changes state.
This is called the toggle mode.
The waveforms below are applied to the J, K, and clock inputs as
indicated. Determine the Q output, assuming that the flip-flop is
initially RESET.
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D Flip – flop Edge-Triggered Operation
-A toggle mode is not available on a D-flip-flop like it is on a J-K
flip flop, but you can hardwire one by wiring 𝑄 back to D. As you
will see in the counter discussion, this is useful in several
counters.
-For instance, if Q is LOW, Q is HIGH, and the flip-flop toggles
on the next clock edge. Because the flip-flop only changes on the
active edge, the output changes just once each clock pulse.
-The only difference between the basic D flip-flop and the gated
D latch is that the basic D flip-flop has a pulse transition detector.
The basic type of a transition pulse detector
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Given the waveform (a) below for the D input and the clock,
determine the Q output waveform if the flip-flop starts out
RESET.
The Q output goes to the state of the D input at the time of the positive-going clock
edge.
*Related Problem
Determine the Q output for the D flip-flop if the D input in
waveform (a) above is inverted.
J – K Flip flops
The Q output is connected back to the gate G2 input, while the Q
output is connected back to the gate G1 input. In honor of Jack
Kilby, who created the integrated circuit, the two control inputs
are named J and K. A J-K flip-flop can also be negative edge-
triggered, which means that the clock input is inverted.
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A simplified logic diagram for a positive edge-triggered J-K flip-flop.
Asynchronous Preset and Clear Inputs
-Synchronous inputs are transferred in the triggering edge of the
clock (for example the D or J-K inputs). Most IC flipflops have
other inputs that are asynchronous, meaning they affect the output
independent of the clock.
-Two such inputs are normally labeled preset (PRE) and clear
(CLR). These inputs are usually active LOW. A D flip flop with
active LOW preset and CLR is shown.
-For synchronous operation, both the preset and clear inputs must
be held HIGH. Preset and clear cannot be LOW at the same time
in normal operation.
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Logic symbol and diagram of active - LOW D flip flop with PRE & CLR
For the positive edge-triggered D flip-flop with preset and clear
inputs in waveforms below, determine the Q output for the inputs
shown in the timing diagram in part (a) if Q is initially LOW.
For an active low, both preset and clear bar are low, when the
CLR bar is low the output Q will be low, when the preset bar is
low the output Q will be high, when both preset and clear bar are
high, the Q output will follow D on the next CLK
*Related problem
If you interchange the 𝑃𝑅𝐸 and 𝐶𝐿𝑅 waveforms above, what will
the Q output look like
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The 1J, 1K, 1CLK, 1𝑃𝑅𝐸, and 1𝐶𝐿𝑅 waveforms above are
applied to one of the negative edge – triggered flip flops in a
74HC112 package. Determine the 1Q output waveform
For an active low both inputs are low, when the CLR bar is low
the output is low, when the PRE bar is low the output is high, when
both CLR & PRE bar are high, the J&K are considered, *note
when J&K are high the output togglezs.
Flip – flop Characteristics
Propagation delay time is specified for the rising and falling
outputs. It is measured between the 50% level of the clock to the
50% level of the output transition.
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Propagation delays, clock to output.
Another propagation delay time specification is the time
required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The 74AHC
family has specified delay times under 5 ns.
Propagation delays, preset input to output and clear input to output.
The set-up time (𝒕𝒔 ) refers to the minimum duration necessary
for the input logic levels (J and K, or D) to remain constant before
the clock pulse’s triggering edge. This duration ensures that the
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levels can be accurately captured by the flip-flop. The interval is
shown below.
The hold time (𝑡ℎ ) refers to the minimum duration necessary for
the logic levels on the inputs to be maintained after the triggering
edge of the clock pulse, ensuring that the levels are accurately
captured by the flip-flop.
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Maximum Clock Frequency – A flip-flop can reliably activate
at 𝑓𝑚𝑎𝑥 . At clock frequencies over the maximum, the flip-flop
would not respond quickly enough, impairing its functionality.
Pulse Widths – Manufacturers typically specify minimum pulse
widths (𝑡𝑤 ) for clock, preset, and clear inputs in order to ensure
reliable operation. Typically, the clock is specified by its minimal
HIGH time and minimum LOW time.
Power Dissipation – The power dissipation of any digital circuit
is the total power consumption of the device
Comparison of Specific Flip-Flops
An advantage of CMOS is that it can operate over a wider range of dc supply
voltages (typically 2 Vto 6 V) than bipolar and, therefore, less expensive power
supplies that do not have precise regulation can be used. Also, batteries can be used
as secondary or primary sources for CMOS circuits. In addition, lower voltages
mean that the IC dissipates less power. The drawback is that the performance of
CMOS is degraded with lower supply voltages. For example, the guaranteed
maximum clock frequency of a CMOS flip-flop is much less at VCC = 2 V than at
VCC = 6 V.
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Parallel data storage
Digital systems often need to store numerous bits of data from
parallel lines in a set of flip-flops. Four flip-flops demonstrate this
procedure. A flip-flop’s D input is linked to each of the four
parallel data lines.
Flip-flops are triggered by the same clock pulse because their
clock inputs are coupled. Positive edge-triggered flip-flops store
data on the D inputs simultaneously on the clock’s positive edge,
as shown in the timing waveform below.
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Example of flip-flops used in a basic register for parallel data storage.
Frequency Division
For frequency division, it is simple to use a flip-flop in the toggle
mode or to chain a series of toggle flip flops to continue to divide
by two.
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One flip-flop will divide 𝑓𝑖𝑛 by 2, two flip-flops willdivide 𝑓𝑖𝑛 by
4 (and so on). A side benefit of frequency division is that the
output has an exact 50% duty cycle.
Example of two D flip-flops used to divide the clock frequency by 4.
Develop the 𝑓𝑜𝑢𝑡 waveform for the circuit in in figure below when
an 8 kHz square wave input is applied to the clock input of flip-
flop A.
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*Related problem
How many flip-flops are required to divide a frequency by thirty-
two?
Counting
Both flip-flops are initially RESET. Flip-flop A toggles on the
negative-going transition of each clock pulse. The Q output of
flip-flop A clocks flip-flop B, so each time QA makes a HIGH-to-
LOW transition, flip-flop B toggles. The resulting QA and QB
waveforms are shown in the figure.
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Determine the output waveforms in relation to the clock for QA,
QB, and QC in the circuit of Figure below and show the binary
sequence represented by these waveforms.
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*Related problem
-How many flip-flops are required to produce a binary sequence
representing decimal numbers 0 through 15?
One -shots
-The one-shot or monostable multivibrator is a device with only
one stable state. When triggered, it goes to its unstable state for a
predetermined length of time, then returns to its stable state.
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-The time that the device stays in its unstable state determines the
pulse width of its output.
-For most one-shots, the length of time in the unstable state (tW)
is determined by an external RC circuit as shown below
A simple one shot Circuit
One short circuit above depicts a simple one-shot (monostable
multivibrator) that is built of a logic gate and an inverter. Gate
output is triggered by a pulse at the trigger input. G1 falls. This
HIGH-to-LOW transition is coupled to the input by the capacitor
of inverter G2. G2's output rises due to its apparent LOW. This
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HIGH connects back into G1, suppressing its output. The trigger
pulse has caused up to this point. Q to go HIGH on the one-shot.
From its unstable condition to its stable state, a nonretriggerable
one-shot will not respond to any trigger pulses. Thus, it ignores
trigger pulses before timeout. The output pulse width is the
duration of the one-shot unstable.
Nonretriggerable one-shot action.
A re-triggerable one-shot can be triggered before it times out. The
result of retriggering is an extension of the pulse width as
illustrated in the waveform below
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-An application for a re-triggerable one-shot is a power failure
detection circuit. Triggers are derived from the ac power source,
and continue to retrigger the one shot. In the event of a power
failure, the one-shot is not triggered and an alarm can be initiated.
-74121 is a nonretriggerable IC one-shot. Figure below shows
external R and C. Gated trigger inputs A1, A2, and B.
𝑅𝐼𝑁𝑇 goes to a 2 kꭥ internal timing resistor.
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Logic symbols for the 74121 nonretriggerable one-shot.
Setting the Pulse Width
-As illustrated in Figure (a) below, the internal timing resistor
(𝑅𝐼𝑁𝑇 ) coupled to 𝑉𝑐𝑐 produces a pulse width of roughly 30 ns
without external timing components. External components set
pulse width between 30 ns and 28 s.
-Figure (b) illustrates the internal resistor (2kꭥ) and external
capacitor setup.
-Figure (c) shows the configuration using an external resistor and
an external capacitor.
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Three ways to set the pulse width of a 74121.
The Schmitt-Trigger Symbol
-Inputs uses a special threshold circuit that produces hysterisis
that prevents erratic switching between states.
A threshold circuit with hysteresis avoids chaotic switching
between states when a slow-changing trigger voltage hangs
around the crucial input level. This permits dependable triggering
at 1 volt/second input changes.
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Logic symbol for the 74LS122 retriggerable one-shot.
➢ Has CLR input
➢ EXT R & C
➢ Inputs A1, A2, B1 & B2 are Gates trigger I/P
➢ Min 45 𝜇𝑠 pulse width with no ext components
0.7
➢ 𝑡𝑤 = 0.32R𝐶𝐸𝑋𝑇 (1 + )
𝑅
➢ 0.32 = Constant. determined by particular type of OS
➢ R= kΩ = INT/EXT
➢ 𝐶𝐸𝑋𝑇 = 𝑝𝐹 & 𝑡𝑤 = 𝑛𝑆
➢ Internal Resistor R =10kΩ
A certain application requires a one-shot with a pulse width of
approximately 100 ms. Using a 74121, show the connections and
the component values.
randomly select (𝑅𝐸𝑋𝑇 = 39kꭥ and calculate the necessary
capacitance.
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𝑡𝑤 =0.7𝑅𝐸𝑋𝑇 𝐸𝐸𝑋𝑇
𝑡𝑤
𝐶𝐸𝑋𝑇 =
0.7𝑅𝐸𝑋𝑇
where 𝐶𝐸𝑋𝑇 is in pF, 𝑅𝐸𝑋𝑇 is in kꭥ, and tW is in n. Since 100 ms
= 1𝑥108 ns,
1𝑥108
𝐶𝐸𝑋𝑇 = 0.7(39) = 3.66𝑥10−6 pF = 3.66𝜇F
A standard 3.3 μF capacitor will give an output pulse width of 91
ms. The proper connections are shown. To achieve a pulse width
closer to 100ms, other combinations of values for (𝑅𝐸𝑋𝑇 and
(𝐶𝐸𝑋𝑇 can be tried. For example, (𝑅𝐸𝑋𝑇 = 68kΩand (𝐶𝐸𝑋𝑇 =
2.2μF gives a pulse width of 105 ms.
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*Related problem
Use an external capacitor in conjunction with (𝑅𝐼𝑁𝑇 ) to produce
an output pulse width of 10 ms from the 74121.
Determine the values of 𝑅𝐸𝑋𝑇 and 𝐶𝐸𝑋𝑇 that will produce a pulse
width of 1𝜇s when connected to a 74LS122.
0.7
𝑡𝑤 = 0.32𝑅𝐸𝑋𝑇 𝐶𝐸𝑋𝑇 (1 + )
𝑅
𝑅𝐸𝑋𝑇 =4.88kꭥ Use a standard value of 4.7kꭥ
*Related Problem
Show the connections and component values for a 74LS122 one-
shot with an output pulse width of 5 𝜇s. Assume 𝐶𝐸𝑋𝑇 = 560 pF.
Application
A sequential timing circuit using three 74LS122 one-shots.
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TIMERS
The 555 timer is a highly adaptable and extensively employed
integrated circuit (IC) component due to its ability to operate in
two distinct modes: monostable multivibrator (also known as a
one-shot) and astable multivibrator (often referred to as a pulse
oscillator).
Internal functional diagram of a 555 timer (pin numbers are in parentheses).
Comparator: High to Low o/p, depending on input levels
Voltage divider:
➢ 3x5kΩ
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➢ trigger level of 1/3 Vcc
➢ threshold level of 2/3 Vcc
Control Voltage: Ext adjust the trigger and threshold value to
other values if necessary
Normally high trigger goes belwo 1/3 Vcc - o/p comp B- LOW
to HIGH & sets the S-R latch4O//P 34HIGH 3 Q1 (discharge
transistor) goes off.
-O/P 3 stays HIGH initial normally LOW threshold input goes
about 2/3Vcc 3 causes the O/P comparator A to switch from LOW
to HIGH
-This RESETs the latch, causing the O/P to go back LOW and
turning the discharge transistor ON
EXT reset input: used to reset the latch independent of the
threshold circuit.
Trigger and threshold INPUT: Are controlled by external
components connected to produce either monostable or astable
action
The 555 Timer as a One-Shot
-The pulse width is determined by 𝑅1 𝐶1 and is approximately
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𝑡𝑊 = 1.1𝑅1 𝐶1 .
The 555 timer connected as a one-shot.
39
What is the output pulse width for a 555 monostable circuit with
𝑅1 = 2.2 kꭥ and 𝐶1 = 0.01 µF?
*Related Problem
For 𝐶1 = 0.01µF, determine the value of 𝑅1 for a pulse width of
1 ms.
-Determine the pulse width for the circuit shown
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The 555 Timer as an Astable Multivibrator
The 555 timer connected as an astable multivibrator (oscillator).
➢ Astable multi-vibrator
➢ Non sinusoidal oscillator
➢ Thresh I/P is connected to Trig
➢ R1, R2 & C1 3 timing network that sets the frequency of
oscillation .
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➢ uF - C2 - Control input for decoupling and has no effect on
theoperation. It can be left off.
Operation of the 555 timer in the astable mode.
Operation of the 555 timer in the astable mode
-When power = ON, C1 is uncharged → trigger voltage (Pin2)
= 0 Volt
This causes Comp B→ H & COMP A →L
➢ Forcing O/P of latch & base of Q1→ LOW & transistor is
OFF.
➢ C1 charges thru R1 & R2,
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➢ When the C1 voltage reaches 1/3Vcc
➢ COMP B →LOW and when C142/3Vcc COMP A →HIGH
➢ The latch is reset→ Base of Q1→ HIGH →Transistor ON
➢ →C1 discharges these R2 & Q1
➢ C1 discharges COMP A → LOW 3C1 → 1/3Vcc → COMP
B →H→Latch →SET →Q1 base → LOW →Q1 → OFF
➢ Another charging cycle begins and the entire process repeats
results in Qo
➢ rectangular waves
➢ duty cycle depends on R1 & R2
➢ Frequency of oscillators
-The 555 can be configured as a basic astable multivibrator with
the circuit shown. In this circuit 𝐶1 charges through 𝑅1 and 𝑅2
and discharges through only 𝑅2 . The output frequency is given
1.44
by: 𝑓 = (𝑅
1 +2𝑅2 )𝐶1
-Given the components, you can read the frequency from the
chart. Alternatively, you can use the chart to pick components for
a desired frequency.
-Duty cycle of output can be adjusted by choosing R1 and R2.
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50% Duty cycle is achieved if R2 > R1
→Changing time = discharging time
Duty cycle
𝑡𝐻 →time O/P is HIGH 3 Time it takes C1 to charge from 1/3Vcc
to 2/3Vcc.
𝑡𝐻 = 0.7(R1+R2)C1
𝑡𝐻 4 time O/P is LOW ² Time it takes C1 to discharge from 2/3Vcc
to 1/3Vcc.
𝑡𝐿 = 0.7R2 C1
T=period of O/P wave form =sum of tH & tL= reciprocal of f.
T=𝑡𝐻 + 𝑡𝐿 = 0,7(R1+2R2)C1
𝑡𝐻 𝑡𝐻
Therefore duty cycle = 𝑇
=𝑡
𝐻 +𝑡𝐿
Duty cycle = (R1+R2)/(R1+2R2) x100%
To achieve duty cycle < 50%.
Modify the circuit so that C1 discharges thru R1 and discharges
thru R2.
Achieve this with a diode, For 50% duty cycle R1 < R2.
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Therefore, duty cycle = (R1)/(R1+2R2) x100%
A 555 timer configured to run in the astable mode (pulse
oscillator) is shown below. Determine the frequency of the output
and the duty cycle.
f = 1.44 /(R1 = 2R2)C1 = 1.44 /(2.2kΩ +9.4kΩ)0.22μF =
5.64kHz.
Duty Cycle = [(R1 + R2)/(R1 + 2R2)] 100%
= [(2.2kΩ + 4.7kΩ)/2.2kΩ + 9.4kΩ] 100% = 59.5%
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Frequency of oscillation as a function of 𝐶1 and 𝑅1 + 2𝑅2 . The sloped
Applications of Monostable Multivibrator
-Generating timing Delays
-frequency Division
-Pulse Width Modulation (PWM)
-Switching the relay
Digital system application
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