Roll No.

: USN:

Sri Bhagawan Mahaveer Jain Educational & Cultural Trust’s

Jain College of Engineering, Belgaum

Department of Electronics & Communication Engineering

This is to certify that Mr./Ms.

has satisfactorily completed the course of experiments in VLSI Design & Testing

Laboratory (BECL606)as partial fulfillment of the requirements of the 6th Semester

of Bachelor of Engineering Degree prescribed by the Visveswaraya Technological

University ( VTU ) Belgaum, during the academic year 2024-25.

Continuous Evaluation (30M)

Practical
Average marks of Total
Journal & Test
Conduction of each (50M)
Attendance(20M) (20M)
experiment (10M)

Faculty In-charge H.O.D E&C

 INDEX

SI Experiments CO’s Page Date Marks Sign

No. No.

Write verilog code for 4-bit adder and verify its functionality
using test bench. Synthesize the design by setting proper
1 constraints and obtain the netlist. From the report generated
identity critical path, maximum delay, total number of cells,
power requirement and total area required. Change the
constraints and obtain optimum synthesis results

Write verilog code for 32-bit ALU supporting 4-logical and

four arithmetic operations, using case and if statement for
ALU behavioral modeling. Synthesize the design targeting
2
suitable library and by setting area and timing constraints.
Tabulate the area, power and delay for the synthesized netlist.
Identity critical path.

Flip-Flops ( D,SR and JK ) Write the Verilog description

Verify the Functionality using Test-bench. Synthesize the design
by setting proper constraints and obtain the gate level netlist.
3 From the report gate level netlist identify Critical path, Maximum
delay, Total number of cells, Power requirement and Total area
[Link] the functionality using Gate level netlist and
compare the results at RTL and gate level netlist.

Four bit Synchronous MOD-N counter with Asynchronous reset

4
Write Verilog [Link] functionality using Test-bench
Synthesize the design targeting suitable library and by setting area
and timing [Link] the Area, Power and Delay for the
Synthesized netlist Identify Critical path.
 a) Capture the schematic of CMOS inverter with load
5
capacitance of 0.1pFandset the widths of inverter with Wn=Wp,
Wn=2Wp, Wn=Wp/2 and length at selected technology. Carry
out the following:
i. Set the input signal to a pulse with rise time, fall time of 1ns
and pulse width of 10ns and time period of 20ns and plot the
input voltage and output voltage of designed inverter?
ii. From the simulation results compute tpHL, tpLH and td for all
three geometric settings of width?
Tabulate the results of delay and find the best geometry for
minimum delay for CMOS inverter?
b) Draw layout of inverter with Wp/Wn =40/20, use optimum
layout methods. Verify for DRC and LVS, extract parasitic and
perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
a) Capture the schematic of 2-input CMOS NOR gate having
6
similar delay as that of CMOS inverter computed in experiment 1.
Verify the functionality of NAND gate and also find out the delay
td for all four possible combinations of input vectors. Table the
results. Increase the drive strength to 2X and 4X and tabulate the
results.

Construct the schematic of the Boolean Expression

7
Y= AB+CD+E using CMOS Logic. Verify the functionality of
the expression find out the delay td for some combination of input
vectors. Tabulate the results
a) Capture schematic of Common Source Amplifier with PMOS
8
Current Mirror Load and find its transient response and AC
response? Measures the Unity Gain Bandwidth (UGB),
amplification factor by varying transistor geometries, study the
impact of variation in width to UGB.
b) Draw layout of common source amplifier, use optimum layout
methods. Verify for DRC and LVS, extract parasitic and perform
post layout simulations, compare the results with pre-layout
simulations. Record the observations.
a) Capture schematic of two-stage operational amplifier and
9
measure the following:
i. UGB dB bandwidth Gain margin and phase margin with and
without coupling capacitance/ Use the op-amp in the inverting and
non-inverting configuration and verity its functionality
v. Study the UGB, 3dB bandwidth, gain and power requirement
in op-amp by varying the stage wise transistor geometries and
record the observations
 Demonstration Experiment

10 Write verilog code for UART and verify its functionality using
test bench. Synthesize the design targeting suitable library and by
setting area and timing constraints. Tabulate the area, power and
delay for the synthesized netlist. Identity critical path.
 VISION
To achieve excellence in education and research for developing globally competent, ethically
sound electronics and communication engineers

MISSION

1. To provide a conducive environment for learning through structured student centric,

teaching -learning process
2. To nurture needs of society by infusing scientific temper in students and to grow as a center
of excellence with efficient industry-institute interaction.
3. To inculcate self learning skills, entrepreneurial ability and professional ethics.

PROGRAMSPECIFICOUTCOMES (PSO's)

Graduates in the UG program in electronics and Communication engineering will be able to:
PSO1:Design,verify and develop analog and digital systems by using state of the art
technology to contribute to the societal needs.

PSO2:Apply the knowledge in various domains of IOT, real time systems, communication systems,
VLSI and Embedded systems, image and signal processing using hardware and software tools.

PROGRAMEDUCATIONALOBJECTIVES (PEO's)
Graduates will be able to:

[Link] real-time social problems and deliver efficient solutions.

PEO2. Lead and succeed in professional careers.
[Link] through research and entrepreneurship.
 PROGRAMOUTCOMES (POs)

Electronics Engineering Graduates will be able to achieve the following:

1. Engineering knowledge: Apply the knowledge of mathematics, science, and engineering fundamentals to
the solution of Electronics engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and
engineering sciences.
3. Design/development of solutions: Design solutions for engineering problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health
and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering
and IT tools including prediction and modeling to complex engineering activities with an understanding of
the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and teamwork: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change
 L1:RememberingL2:UnderstandingL3:ApplyingL4:AnalyzingL5:EvaluatingL6:Creating

Course Bloom’s Cognitive

Description
Outcomes level
BECL606.1 Design and simulate combinational and L3
sequential digital circuits using Verilog
HDL.
BECL606.2 Understand the synthesis process of digital L3
circuits using EDA tool.
Perform ASIC design flow and understand
the process of synthesis, synthesis
BECL606.3 L3
constraints and evaluating the synthesis
reports to obtain
Optimum gate level netlist.
Design and simulate basic CMOS circuits
BECL606.4 like inverter, common source amplifier and L3
differential amplifier, SRAM
Perform RTL-GDSII flow and understand
BECL606.5 L3
the stages in ASIC design.

Strength of CO Mapping to PO/PSOs with Justification

1:Slight(Low)2:Moderate(Medium) 3:Substantial(High)
 CO->PO/PSO Justification
 Moderately mapped as these programming fundamentals help to design and simulate
combinational and sequential digital circuits using Verilog HDL.
CO1 -> PO1(2) ● Moderately mapped as only some of the problems analysis skills to design and simulate
combinational and sequential digital using Verilog HDL
CO1 -> PO2(2)
CO1 -> PO3(2)
● Moderately mapped as students learn to design/ develop solutions combinational and
CO1 -> PO4(2) sequential digital circuits using Verilog HDL methods.
CO1 -> PO5(2)
CO1 -> PO8(2) ● Moderately mapped as the students will be able to design experimental set up
and analyze information.
CO1 -> PO9(2)
CO1->PO10(2)  Moderately mapped as the students will be able to implement appropriate engineering
CO1->PO12(2) concepts of combinational and sequential digital circuits using EDA( cadence Tool).
CO1->PSO1(2)  Moderately mapped as the students will be able to apply ethical principles and commit to
professional ethics.
CO1->PSO2(2)
 Moderatelymappedasthestudentswillbeabletoworkasateamandjointlyfinda solution for
the problem.
 Moderatelymappedasthestudentswillbeabletoeffectivelycommunicatethrough
Writing reports of design circuits and programs delivered in the lab.
 Moderately mapped as the students will be able to engage in lifelong learning
 Moderately mapped as Student will apply Verilog HDL program development technique
in embedded system design.
 Moderately mapped as Student will apply Verilog HDL program development technique
in communication system design.
CO2 -> PO1(2)  Moderately mapped as Student will apply engineering knowledge and understand
CO2 -> PO2(2) synthesis process of digital circuits using EDA tool (cadence Tool).
CO2 -> PO3(2)  ModeratelymappedasStudentswilldevelopproblemanalysisskillsforunderstanding the
synthesis process of digital circuits using EDA tools.
CO2 -> PO4(2)
 Moderately mapped as students gaining the knowledge of the synthesis process of digital
CO2 -> PO5(2)
circuits, students can develop solutions for engineering problems.
CO2 -> PO8(2)
CO2 -> PO3(2)  Moderately mapped as the students will be able to design experimental set up
CO2 > PO10(2) and analyze information.
CO2-> PO12(2)  StronglymappedasStudentwillusecadencetooltosynthesisofdigitalcircuits
CO2->PSO1(2)  Moderately mapped as the students will be able to apply ethical principles and commit to
CO2->PSO2(2) professional ethics.
 Moderatelymappedasthestudentswillbeabletoworkasateamandjointlyfinda solution for
the problem.
 Moderatelymappedasthestudentswillbeabletoeffectivelycommunicatethrough
writingsynthesisreportsofdesigncircuitsandprogramsdeliveredinthelab.
 Moderately mapped as the students will be able to engage in lifelong learning
 ModeratelymappedasStudentwillapplyVerilogHDLprogramdevelopmentand cadence
tool technique in embedded system design.
 ModeratelymappedasStudentwillapplyVerilogHDLprogramdevelopmentand cadence
tool technique in communication system design
CO3 -> PO1(2)  Moderately mapped as Student will apply engineering knowledge to understand ASIC
CO3 -> PO2(2) design flow and synthesis constraints and generate report for gate level netlist
CO3 -> PO3(2)  ModeratelymappedasStudentwilluseproblemanalysisskillstounderstandASIC design flow
CO3 -> PO4(2) and synthesis constraints and generate report for gate level netlist
 Moderately mapped as Student will develop solutions for different synthesis constraints
CO3 -> PO5(2)
in ASIC design flow
CO3 -> PO8(2)
 Moderatelymappedasthestudentswillbeabletodesignexperimentalsetupand analyze
CO3 -> PO9(2) information.
CO3->PO10(2)  Strongly mapped as Student will use cadence tool to understand ASIC design flow and
CO3->PO12(2) synthesis constraints and generate report for gate level netlist
CO3->PSO1(2)  Moderately mapped as the students will be able to apply ethical principles and commit to
professional ethics.
CO3->PSO2(2)
 Moderatelymappedasthestudentswillbeabletoworkasateamandjointlyfinda solution for
the problem.
 Moderatelymappedasthestudentswillbeabletoeffectivelycommunicatethrough
Writing reports of design circuits and programs delivered in the lab.
 Moderately mapped as the students will be able to engage in lifelong learning
 Moderately mapped as Student will apply knowledge of ASIC design flow in embedded
system design.
 Moderately mapped as Student will apply knowledge of ASIC design flow in
communication system design.
CO4 -> PO1(2)  Moderately mapped as Design and simulate basic CMOS circuits like inverter, common
CO4 -> PO2(3) source amplifier and differential amplifier.
CO4 -> PO3(3)  Moderately mapped as Student will apply engineering knowledge to understand design
and simulation of basic CMOS Circuits like inverter, common source amplifier and
CO4 -> PO4(2)
differential amplifier
CO4 -> PO5(2)
 Moderately mapped as Student will use problem analysis skills to design and simulate
CO4 -> PO8(2) basic CMOS Circuits like inverter, common source amplifier and differential amplifier
CO4 -> PO9(2)  Moderately mapped as the students will be able to design experimental setup and
CO4>PO10(2) analyze information.
CO3->PO12(2)  Strongly mapped as Student will develop solutions for design and simulation of basic
CMOS Circuits like inverter, common source amplifier and differential amplifier
CO4->PO12(2)
 Moderately mapped as the students will be able to apply ethical principles and commit to
CO4->PSO1(2)
professional ethics.
CO4->PSO2(2)
 Moderately mapped as the students will be able to work as a team and jointly find a
solution for the problem.
 Moderatelymappedasthestudentswillbeabletoeffectivelycommunicatethrough
Writing reports of design circuits and programs delivered in the lab.
 Moderatelymappedasthestudentswillbeabletoengageinlifelonglearning
 Moderately mapped as Student will apply knowledge of CMOS circuits in embedded
system design
 Moderately mapped as Student will apply knowledge of CMOS circuits in
communication system design
CO5->PO1(2)  ModeratelymappedasStudentwillapplyengineeringknowledgetoperformRTL- GDSII
CO5 -> PO2(2) flow and understand the stages in ASIC design.

CO5 -> PO3(2)  Moderately mapped as Student will use problem analysis skills to perform RTL-GDSII
flow and understand the stages in ASIC design.
CO5 -> PO4(2)
 ModeratelymappedasStudentwilldevelopsolutionsforproblemsbasedonASIC design flow
CO5 -> PO5(2) and GDSII file generation
CO5 -> PO8(2)  Moderatelymappedasthestudentswillbeabletodesignexperimentalsetupand analyze
CO5 -> PO9(2) information.
CO5>PO10(2)  StronglymappedasStudentwilluseEDATooltogenerateGDSIIfileusingASIC design flow.
CO5->PO12(2)  Moderately mapped as the students will be able to apply ethical principles and commit to
professional ethics.
CO5->PSO1(2)
 Moderatelymappedasthestudentswillbeabletoworkasateamandjointlyfinda solution for
CO5->PSO2(2)
the problem.
 Moderatelymappedasthestudentswillbeabletoeffectivelycommunicatethrough
Writing reports of design circuits and programs delivered in the lab.
 Moderately mapped as the students will be able to engage in lifelong learning
 Moderately mapped as Student will apply knowledge of RTL-GDSII flow in embedded
system design.
 Moderately mapped as Student will apply knowledge of RTL-GDSII flow in
communication system design.