CHAPTER 11

Device Series and Parallel Operation,

Interference, and Grounding

This chapter considers various areas of power device application that are often overlooked, or at best,
underestimated. Such areas include parallel and series device utilisation, radio frequency interference
(rfi) noise, filtering, and interactive noise effects. The meaning of earth and neutral is explained.

The power-handling capabilities of power semiconductor devices are generally limited by device area
utilisation, encapsulation, and cooling efficiency. Many high-power applications exist where a single
device is inadequate and, in order to increase power capability, devices are paralleled to increase
current capability or series-connected to increase voltage ratings. Extensive series connection of
devices is utilised in HVDC transmission thyristor and IGBT modules while extensive paralleling of IGBTs
is common in inverter applications. Devices are also series connected in multilevel converters.
When devices are connected in series for high-voltage operation, both steady-state and transient
voltages must be shared equally by each individual series device. If power devices are connected in
parallel to obtain higher current capability, the current sharing during both switching and conduction is
achieved either by matching appropriate device electrical and thermal characteristics or by using
external forced sharing techniques.

11.1 Series connection and operation of power semiconductor devices

11.1.1 Series semiconductor device operation

Owing to variations in blocking currents, junction capacitances, delay times, on-state voltage drops, and
reverse recovery of individual power devices, external voltage equalisation networks and special gate
circuits are required if devices are to be reliably connected and operated in series (or parallel).

11.1.1i - Steady-state voltage sharing

Figure 11.1 shows the forward off-state voltage-current characteristics of two power switching devices,
such as SCRs or IGBTs. Both series devices conduct the same off-state leakage current but, as shown,
each supports a different voltage. The total voltage blocked is V1 + V2 which can be significantly less
than the sum of the individual voltage capabilities. Forced voltage sharing can be achieved by
connecting a resistor of suitable resistance in parallel with each series device as shown in figure 11.2.

These equal value sharing resistors will consume power and it is therefore desirable to use as large
resistance as possible. For worst case analysis consider n cells in series, where all the cells pass the
maximum leakage current except cell D1 which has the lowest leakage. Cell D1 will support a larger
blocking voltage than the remaining n - 1 which share voltage equally.
Let VD be the maximum blocking voltage for any cell which in the worst-case 
analysis

is supported by
D1. If the range of maximum rated leakage or blocking currents
is from I b to I b then the maximum

imbalance occurs when member D1 has a leakage current of I b whilst all the remainder conduct I b .

BWW
Chapter 11 Series and Parallel Device Operation, and Interferences 368

V1
Ileakage

V2

Figure 11.1. Collector (transistor) or anode (thyristor) forward blocking I-V characteristics
showing voltage sharing imbalance for two devices in series.


Ib
VD

a
 Po
I bint
3
Po
int
2


Ib

I2

Figure 11.2. Series IGBT string with resistive shunting for sustaining voltage equalisation in the off-state.

From figure 11.2, Kirchhoff‟s current law at node „a‟, gives

 
I  I b  I b (A) (11.1)
 I1  I 2 (A) (11.2)
where I1 > I2. The voltage across cell D1 is
VD  I 1R (V) (11.3)

By symmetry and Kirchhoff‟s voltage law, the total string voltage to be supported, Vs, is given by
Vs  (n - 1) I 2 R  VD (V) (11.4)
Eliminating ΔI, I1, and I2 from equations (11.1) to (11.4) yields
nVD V s
R   ohms  (11.5)
 

 n  1  I b  I b 
 
for n ≥ 2.
Generally only the maximum
leakage current at rated voltage and maximum junction temperature is
specified. By assuming I b = 0, a conservative value of the maximum allowable resistance is obtained,
namely
nVD Vs n 1  k s VD  1  k s VD ohms
R  
  n     (11.6)
 n  1 I b  n  1 I b Ib
369 Power Electronics

The extent to which nVD is greater than Vs, is termed the voltage sharing factor, namely
Vs
ks  1 (11.7)
nVD
As the number of devices is minimized the sharing factor approaches one, but equation (11.5) shows
that undesirably the resistance for sharing decreases, hence losses increase.
The power dissipation of the resistor experiencing the highest voltage is given by
Pd  VD2 / R (W) (11.8)
If resistors of ± l00a per cent resistance tolerance are used, the worst case occurs when cell D 1 has a
parallel resistance at the upper tolerance while all the other devices have parallel resistance at the lower
limit. After using VD = (1+a)I1R and Vs = (n-1)×(1-a) I2R + VD for equations (11.3) and (11.4), the
maximum resistance is given by
n (1 - a ) VD - (1  a ) V s
R  
(ohms) (11.9)
(n - 1) 1  a 2  I b
for n ≥ 2.

The maximum loss in a resistor is

PD  VD2 / R (1 - a ) (11.10)
If the dc supply toleration is incorporated, then Vs in equations (11.6) and (11.9) is replaced by (1+b)×Vs
where +100b is the supply percentage upper tolerance. This leads to a decreased resistance
requirement, hence increased resistor power losses.
n 1  a  VD - 1  a  1  b  V s
R  
(ohms) (11.11)
(n - 1) 1  a 2  I b
The effects and importance of just a few per cent resistance or supply voltage tolerance on the
maximum value for the sharing resistors and their power losses, are illustrated by example 11.1.

Example 11.1: Series device connection – static voltage balancing

Ten, 200 V reverse-blocking, ultra fast 35 ns reverse recovery diodes are to be employed in series in a
1500 V dc peak, string voltage application. If the maximum device reverse leakage current is 10 mA (at
maximum junction temperature) calculate the voltage sharing factor, and for worst-case conditions, the
maximum value of sharing resistance and power dissipation.

i. If 10 per cent tolerance resistors are employed, what is the maximum

sharing resistance and its associated power rating?
ii. If a further allowance for supply voltage tolerance of ±5% is incorporated,
what is the maximum sharing resistance and its associated power rating?

Solution

When n = 10, VD = 200 V dc, Vs = 1500 V dc, and I b = 10mA, the voltage sharing factor is
k s  1500V/10×200V = 0.75. Equation (11.6) yields the maximum allowable sharing
resistance
nVD Vs 10×200V - 1500V
R   = 5.55kΩ
n  1 I b 10 - 1 ×10mA


The nearest (lower) preferred value, 4.7kΩ, would be used.

Maximum resistor power losses occur when the diodes are continuously blocking. The maximum
individual supporting voltage appears across the diode which conducts the least leakage current.
Under worst-case conditions this diode therefore supports voltage VD, hence maximum power loss
PD is
P  V 2 / R
D D

= 200V 2 /4700 = 8.5 W

Since the worse device, (in terms of sharing has lowest leakage current), is randomly located in the
string, each 4.7kΩ resistor must be capable of dissipating 8.5W.

The maximum 1500V dc supply leakage current is 42.5mA (10mA+1500V/10×4.7kΩ) giving 63.8W
total losses (1500V×42.5mA), of which 15W (10mA×1500V) is lost in the diodes.
Chapter 11 Series and Parallel Device Operation, and Interferences 370

i. If 10% resistance tolerance is incorporated, equation (11.9) is employed with a = +0.1, that is
n (1 - a ) VD - (1  a ) V s
R  
(n - 1) 1  a 2  I b
10  (10 - 0.1)  200V - (1 + 0.1)  1500V
R 
(10 - 1)  1 - 0.12   10mA
= 2.13 kΩ
The nearest (lower) preferred value is 1.8kΩ, which is much lower resistance (higher losses) than if
closely matched resistors were to be used.
Worst-case resistor power dissipation is
P  V 2 / R (1 - a )
D D

= 200V 2 /1800  (1 - 0.1)

= 27.7 W
The maximum total module losses are 165W (1500V×103mA) arising from 103mA (10mA +
1500V/1.8kΩ×(1- 0.1)) of leakage current.

ii. If the device with the lowest leakage is associated with the worst case resistance (upper
tolerance band limit), and simultaneously the supply is at its upper tolerance limit, then worst case
resistance is given by equation (11.11), that is
n 1  a  VD - 1  a  1  b  V s
R  
(n - 1) 1  a 2  I b
10  1 - 0.1  200V - 1 + 0.1  1 + 0.05   1500V
= = 758
(10 - 1)  1 - 0.12   10mA
Each resistor (preferred value 680Ω) needs to be rated in excess of
200V 2 /680  (1 - 0.1) = 68.6 W
♣

When resistance tolerances are considered, sharing resistors of lower value must be used and the
wider the tolerance, the lower will be the resistance and the higher the power losses. A number of
solutions exist for reducing power losses and economic considerations dictate the acceptable trade-off
level. Matched semiconductor devices would allow a minimum number of string devices (voltage
sharing factor ks → 1) or, for a given string device number, a maximum value of sharing resistance
(lowest losses). But matching is complicated by the fact that semiconductor leakage current varies
significantly with temperature. Alternatively, by increasing the string device number (decreasing the
sharing factor ks) the sharing resistance is increased, thereby decreasing losses. By increasing the
string device number from 10 (ks = ¾) to 11 (ks = 0.68) in example 11.1, the sharing resistance
requirement increases from 4.7kΩ to 6.8kΩ and resistor losses are reduced from a total of 50.8 W to 31
W. Another method of minimising sharing resistance losses is to minimise resistance tolerances. A
tolerance reduction from 10 per cent to 5 per cent in example 11.1 increases the sharing resistance
requirements from 1.8kΩ to 3.9kΩ, while total power losses are reduced from 140 W to 64 W. These
worst-case losses assume a near 100% off-state duty cycle.

11.1.1ii - Transient voltage sharing

During steady-state or at very low frequencies, sharing resistors as shown in figure 11.2 are sufficient to
prevent individual device overvoltage. Mismatching of turn-on delay times of thyristors and transistors
can be minimised by supplying high enough turn-on drive with fast rise times. A higher initial di/dt is then
allowable.
Before a conducting string of diodes or thyristors can reverse-block, reverse recovery charge must flow.
Those elements with least recovery charge requirements recover first and support the reverse bias. The
un-recovered devices recover slowly, since recovery now occurs as a result of the low leakage current
though the recovered devices, and natural recombination.
The transient reverse-blocking voltage can be shared more equally by placing capacitors across each
string element as shown in figure 11.3. The capacitor action is to provide a transient current path
bypassing a recovered device to allow a slower device to recover and to support volts. In the case of
thyristors, low value resistance is connected in series with each capacitor to avoid high capacitor
discharge through the thyristors at turn-on. Figure 11.4 shows the I-V characteristics of two unmatched
thyristors or diodes during reverse recovery.
371 Power Electronics

ℓ
ΔQ ℓ

Figure 11.3. A series diode string with shunting capacitance for transient reverse blocking voltage sharing.

Figure 11.4. Reverse recovery current and voltage for two mismatched series connected diodes.

The worst

case assumptions for the analysis of figure 11.3 are that

element D1 has minimum stored
charge Q while all other devices have the maximum requirement, Q . The charge difference is
 
Q  Q  Q (C) (11.12)
The total string dc voltage Vs, comprises the voltage across the fast-recovery device VD plus the sum of
each of the voltages across the slow n - 1 devices, Vslow. That is
Vs  VD  (n - 1) Vslow (V) (11.13)
The voltage across each slow device is given by
Vslow  n1 Vs  V 

(V) (11.14)
   
where V   Q / C .
Eliminating Vslow from equations (11.13) and (11.14) yields

C 
n  1 Q = n  1 Q (F) (11.15)
nVD Vs n 1  k s  VD
This equation shows that as the number of devices is minimized, the sharing factor, ks, which is in the
denominator of equation (11.15), tends to one and the capacitance requirement undesirably increases.
Manufacturers do not specify the minimum reverse recovery charge but specify the maximum reverse
recovery charge for a given initial forward current, reverse recovery di/dt, and temperature. For worst
case design, assume Q = 0, thus
  

C


 n  1 Q =
 n  1 Q  Q
(F) (11.16)
nVD Vs n 1  k s VD n 
1  k s VD
Voltage sharing circuit design is complicated if the effects of reverse steady-state leakage current in ac
thyristor blocking are taken into account.

Supply and sharing capacitance tolerances significantly affect the minimum capacitance requirement.
Worst case assumptions for capacitance tolerances involve the case when the fastest recovering diode
is in parallel with capacitance at its lower tolerance limit while all the other sharing capacitances are at
their upper tolerance limit. Assuming the minimum reverse recovery charge is zero, then the minimum
sharing capacitance requirement is
Chapter 11 Series and Parallel Device Operation, and Interferences 372

 

C 
 n  1 Q =
n  1 Q (F) (11.17)
1  a nVD Vs  n 1  a  1  k s VD
where -100a is the capacitor negative percentage tolerance and n ≥ 2. Voltage sharing resistors help
minimise capacitor static voltage variation due to capacitance variations.

If the supply tolerance is incorporated, then Vs in equations (11.16) and (11.17) are replaced by
(1+b)×Vs where +100b is the supply percentage upper tolerance. This leads to an increased
capacitance requirement, hence increased energy losses, ½CVD2 .


C


 n  1 Q (F) (11.18)
1  a  nVD  1  b Vs 

Example 11.2: Series device connection – dynamic voltage balancing

The string of ten, 200 V diodes in worked example 11.1 is to incorporate capacitive reverse recovery
transient sharing. Using the data in chapter 5, figure 5.9, specify a suitable sharing capacitance based
on zero capacitance and supply tolerances (a = b = 0), then ± 10 per cent capacitance tolerances (a =
0.1, b = 0), ± 5 per cent supply tolerance (a = 0, b = 0.05), then both tolerances (a = 0.1, b = 0.05).
Estimate in each case the capacitor energy loss at capacitor discharge.
Solution
Figure 5.9 shows that worst-case reverse 
recovery conditions occur at maximum junction
temperature, di/dt, and IF, and a value of Q = 6μC is appropriate.
The minimum possible sharing capacitance occurs when the capacitance and dc rail voltage
are tightly specified. From equation (11.16)


C 
 n  1 Q =
10-1  6μC
= 108nF @ 200Vdc
nVD V s
10  200V - 1500V
The sharing capacitance requirement with 10% tolerance capacitors, is given by equation
(11.17)


C 
 n  1 Q =
10 - 1  6μC = 0.12μF @ 200Vdc
1  a nVD Vs  1 - 0.1  10  200V-1500V 
A further increase in capacitance requirement results if the upper tolerance dc rail voltage is
used. From equation (11.18)


C 
 n  1 Q
1  a  nVD  1  b V s 
=
10 - 1  6μC = 0.14μF @ 200Vdc
1 - 0.1  10  200V - (1+0.05)  1500V 
In each tolerance case the next larger preferred capacitance value should be used, namely,
120nF, 120nF, and 150nF respectively, all rated at 200V dc.
The total series capacitance, using the upper tolerance limit is


CT 
1  a  C
n
The stored energy with a 1500V dc rail in the 10 series connect 120nF capacitors, and
subsequently loss when the string voltages reduces to zero at diode forward bias, is therefore

2 1  a  C V
WT  ½C T Vs 1  b 
2
½ s
2

=½
1 + 0.1  120nF  1500V
2
 1  0.05   16.4mJ
2

10
The energy stored in the 10 series connect 150nF capacitors, and subsequently loss when the
string voltage reduces to zero at diode forward bias, is

WT =½ 
1 + 0.1 ×150nF ×1500V 2  (1 + 0.05)2 = 20.5mJ
10
♣
373 Power Electronics

When capacitive sharing is used with switching devices, at turn-on the transient sharing capacitor
discharges into the switching device. The discharge current magnitude is controlled by the turn-on
voltage fall characteristics. If a linear voltage fall at turn-on is assumed, then the transient sharing
capacitor maximum discharge current idis is a constant current pulse for the fall duration, of magnitude
VD V
i dis  C C D (A) (11.19)
t t tv
The discharge current can be of the order of hundreds of amperes, incurring initial di/dt values beyond
the capabilities of the switching device. In example 11.2 the discharge current for a switch rather than a
diode is approximately 150nF×200V/1μs =30A, assuming a 1μs voltage fall time. This 30A may not be
insignificant compared to the switches current rating. But, advantageously, the sharing capacitors do act
as turn-off snubbers, reducing switch turn-off stressing.
In the case of the thyristor, the addition of a low-valued, low inductance, resistor in series with each
transient capacitor can control the capacitor discharge current, yet not significantly affect the transient
sharing properties. The resultant R-C discharge current can provide thyristor latching current while still
offering transient recovery sharing, dv/dt, and voltage spike suppression. Thyristor snubber operation
and design are considered in chapter 9.1.2.

Figure 11.5 shows the complete steady-state and transient-sharing networks used for diodes, thyristors,
and transistors. Transient voltage sharing for transistors involves the use of the conventional R-D-C
snubber shown in figure 11.5c and considered in chapter 9. The series inductor used with thyristor and
transistor strings provides transient turn-on voltage protection. The inductor supports the main voltage
while each individual element switches on. Such an inductive turn-on snubber is mandatory for the GCT
and the GTO thyristor. No one device is voltage-stressed as a consequence of having a longer turn-on
delay time, although gate overdrive at turn-on minimises delay variations.

R R

R R

Figure 11.5. Transient and steady-state voltage sharing circuits for series connected:
(a) diodes; (b) thyristors; and (c) igbt transistors.

11.2 Parallel connection and operation of power semiconductor devices

11.2.1 Parallel semiconductor device operation

It is common practice to parallel power devices in order to achieve higher current ratings or lower
conducting voltages than are attainable with a single device. Although devices in parallel complicate
layout and interconnections, better cooling distribution is obtained. Also, built-in redundancy can give
improved equipment reliability. A cost saving may arise with extensive parallel connection of smaller,
cheaper, high production volume devices.
The main design consideration for parallel device operation is that all devices share both the steady-
state and transient currents. Any bipolar device carrying a disproportionately high current will heat up
and conduct more current, eventually leading to thermal runaway as considered in section 4.1.
The problem of current sharing is less severe with diodes because diode characteristics are more
uniform (because of their simpler structure and manufacturing) than those of thyristors and transistors.
Chapter 11 Series and Parallel Device Operation, and Interferences 374

Two basic sharing solutions exist

 matched devices
 external forced current sharing.

11.2.1i - Matched devices

Figure 11.6 shows the static I-V on-state characteristics of two SCR‟s. If these two devices are
connected in parallel, for the same on-state voltage, the resultant current flow is I1 + I2 where I1 and I2
can be very different in value. The total current rating of the pair is not the sum of the maximum current
rating for each but rather a value which can be just larger than the rating of one device alone. The
percentage parallel derating pd for n parallel connected devices is defined as
 I 
pd  1  T   100  1 - k p   100 per cent (11.20)
 n Im 
where IT = total current through the parallel arrangement
Im = maximum allowable single device current rating
n = number of parallel devices
kp = current parallel sharing factor = IT /nIm ≤ 1
Parallel connection of IGBT die within a module is made possible by using die from the same
wafer/batch. On-state voltage matching for single large area wafers is expensive and complicated by
the high temperature dependence of both static and dynamic electrical device characteristics.
Derating does not account for effects such as layout and electrical and thermal impedance imbalance.
The amount of derating is traded off against the extra cost involved in selecting devices with closer
(matched) static characteristics.

Im = 100A

Figure 11.6. Forward conduction characteristics of two unmatched devices.

11.2.1ii - External forced current sharing

Forced current sharing is applicable to both steady-state and transient conditions. For a current derating
of less than 5 per cent it is usually cheaper to use forced sharing techniques rather than matched
devices.
Figure 11.6 shows the maximum variation of I-V characteristics in devices of the same type. When
parallel connected the maximum current is restricted to Im+I2, (= 100A+70A = 170A at 1.6V). The
maximum current rating for each device is Im, (100A); hence with suitable forced sharing a combination
in excess of Im + I2 (170A) should be possible. The resistive network in figure 11.7 is used for forced
current sharing and in example 11.3 it is required that Im, 100A, flows through D1 and (1-2×pd)× Im > I2,
(90A) flows through D2, for a pd (5%) overall derating.

From Kirchhoff‟s voltage law in figure 11.7

V1  V 3  V 2  V 4
(11.21)
VD1  I m R  VD2   I T  I m  R
From equation (11.20), rearranged for two devices, n = 2
IT  2  (1  pd )I m  2k p I m
375 Power Electronics

Substituting for IT in equation (11.21) gives

VD VD1
R 2 (ohms) (11.22)
2 pd I m

Im

IT

Figure 11.7. Forced current sharing network for parallel connected devices.

For n devices connected in parallel, equation (11.21) becomes

I  I m  R
VD1  I m R  VD2  T (11.23)
n 1

which after substituting for IT from equation (11.20), for maximum device voltage variation, gives
 
V V D n  1
R D (ohms) (11.24)
I m n  pd

Although steady-state sharing is effective, sharing resistor losses can be high. The total resistor losses
in general terms for n parallel connected devices and a conduction duty cycle δ, are given by
  n  
2

Pt   1   1   pd   I m2 R (W) (11.25)
  n 1  
Since the devices are random in characteristics, each resistor must have a power rating of I m2 R .

Example 11.3: Resistive parallel current sharing – static current balancing

For the two diodes shown in figure 11.6, with I  100A , what derating results when they are parallel
connected, without any external sharing circuits?
The maximum current rating for each device is Im, 100A; hence with suitable forced sharing a 190A
combination should be possible. Using the network in figure 11.7 for current sharing, it is required that
100A flows through D1 and 90A through D2. Specify the per cent overall derating, the necessary sharing
resistors, their worst case losses and diode average, rms, and ac currents at a 50% duty cycle and
worst case.

Solution
The derating for the parallel situation depicted in figure 11.6, without external sharing, is
 170A  100A+70A
pd  1 -  ×100 = 15 per cent (k p = =0.85)
 2×100A  2  100A
With forced resistive sharing, the objective derating is reduced from 15% to
 190A  100A+90A
pd  1 -  ×100 = 5 per cent (k p = = 0.95)
 2×100A  2  100A
From figure 11.6
1.6V + 100A×R = 1.7V + 90A×R
that is
R = 10 milliohm
Equation (11.22), being based on the same procedure, gives the same result. The cell voltage drop is
increased to 1.6V+100A×0.01Ω = 1.7V+90A×0.01Ω = 2.6V .
 Chapter 11 Series and Parallel Device Operation, and Interferences 376

Thus, for an on-state duty cycle δ, the total losses are δ×2.6V×190A = δ×494W.
For δ = ½
I D 1    I D 1  ½  100A = 50A I D 2    I D 2  ½  90A = 45A
I D 1rms    I D1  ½  100A = 70.7A I D 2rms    ID2  ½  90A = 63.6A
2 2
I D 1ac  I D21rms  I D 1  70.72  502  50A I D 2ac  I D2 2rms  I D 2  63.6 2  452  45 A
PR 1  I D21rms R1  70.72  0.01mΩ = 50W PR 2  I D2 2 rms R2  63.6 2  0.01mΩ = 40.5W
PD 1  I D 1 VD 1  50A  1.6V = 80W PR 2  I D 2 VD 2  45A  1.7V = 76.5W
Ptotal = PR + PD =  50W + 40.5W  +  80W + 76.5W  = 90.5W + 156.5W = 247W

For worst case losses, δ →1

I D 1    I D 1  1  100A = 100A I D 2    I D 2  1  90A = 90A
I D 1rms    I D1  1  100A = 100A I D 2rms    ID2  1  90A = 90A
2 2
I D 1ac  I D21rms  I D 1  1002  1002  0A I D 2ac  I D2 2rms  I D2
 902  902  0A
PR 1  I D21rms R1  1002  0.01mΩ = 100W PR 2  I D2 2rms R2  90 2  0.01mΩ = 81W
PD 1  I D 1 VD 1  100A  1.6V = 160W PR 2  I D 2 VD 2  90A  1.7V = 153W
Ptotal = PR + PD = 100W + 81W  + 160W + 153W  = 181W + 313W = 494W

The general form in equation (11.25) gives the same total resistor losses for each conduction duty cycle
case, namely for δ = ½: 50W+40.5W = 90.5W and for δ → 1: 100W+81W = 181W.
♣

A more efficient method of current sharing is to use coupled reactors as shown in figure 11.8. In these
feedback arrangements, in figure 11.8a, if the current in D1 tends to increase above that through D 2, the
voltage across L1 increases to oppose current flow through D1. Simultaneously a negative voltage is
induced across L2 thereby increasing the voltage across D2 thus increasing its current. This technique is
most effective in ac circuits where the core is more readily designed to reset, avoiding saturation.

IF

X to X Np Ns Np Ns Np Ns

X to X

T1 T2 T3

D1 D2 D3

IF n 2
I F    V F
n n  1 2TLM
(c)

IF 2
I F   0.016n 2  VF
n 2TLM
for n  6

Figure 11.8. External forced current sharing networks using cross-coupled reactors:
(a) for two devices; and (b) and (c) for many devices.
 377 Power Electronics

Equalising reactor arrangements are possible for any number of devices in parallel, as shown in figures
11.8b and c, but size and cost become limiting constraints. The technique is applicable to steady-state
and transient sharing. At high current densities, the forward I-V characteristics of diodes and thyristors
(and some IGBTs) have a positive temperature dependence which provides feedback aiding sharing.
The mean current in the device with the highest current, therefore lowest voltage, of n parallel
connected devices in figure 11.8c (with one coupled circuit in series with each device), is given by
I I n 1 2 I n 1 2
I F  F  I F  F   VF  F   VF (11.26)
n n n 2TLM n n 2f s LM
where ΔVF is the maximum on-state voltage drop difference
LM is the self-inductance (magnetising inductance) of the coupled inductor
Τ is the cycle period, 1/fs, and
τ is the conduction period (τ < T)

(a) current sharing analysis for two devices:– ro = 0

Consider two thyristors (n = 2) connected in parallel as show in figure 11.9. The coupled circuit
magnetising current is modelled with the magnetising inductor LM. The transformer turns ratio is 1:1,
hence the winding voltages and currents are equal, taking into account the relative winding flux
orientation shown by the dots. Commutation inductance overlap is ignored.
From Kirchhoff‟s voltage law
vT 1  v 1  vT 2 v 1 (11.27)
That is
v 1  ½  v T 1 - v T 2   ½  v (11.28)
From Kirchhoff‟s current law
I M  i1  i 2 (11.29)
From Faraday‟s equation
dI M
v 1  LM (11.30)
dt
which after integrating both sides gives
1  1
IM   v 1dt  ½ VF 
LM 0 LM
(11.31)

As a condition it is assumed that the voltage difference Δv does not decrease as the operating point
moves along the I-V characteristics. That is, both devices are modelled by v = vo + i × ro, where the linear
resistance ro, is zero, each have different zero current voltages that is different vo, Δvo = ΔVF. Actually
D1 moves further up the I-V characteristic with time as it conducts more current while D 2 moves towards
the origin, as shown in figure 11.9b.

i
IT IT
IM =
i1 - i2
IT1 Im
i2 i2 -
+ t>0 ½IT
IT2
v1 LM v1
- + t=0
IM IM
+ + t
magnetising T1 VT1 VT2 T2
inductance
IF
- - t>0
i1 i2 iF
VF 1/ro
IT ΔVF

(a) (b) Δvo vF

Figure 11.9. External forced current sharing network using cross-coupled reactors:
(a) circuit (including magnetising inductance LM) for two devices and (b) I-V operating points.

(b) current sharing analysis for two devices:– ro ≠ 0

If static resistance is included in the device model for current sharing analysis, then equation (11.30),
assuming both devices have the equal resistance, becomes
dI
v o  LM M  2I M ro (11.32)
dt
Chapter 11 Series and Parallel Device Operation, and Interferences 378

The solution to this differential equation gives the magnetizing current as

v o  t o 
2r

IM  1  e M 
L
(11.33)
2ro  
The maximum magnetizing current increases from zero and reaches a maximum at the end of the
current conduction period τ. Re-arranging equation (11.33) gives the magnetizing inductance as
2ro
LM  (11.34)
 v o 
n 
 v o  I M 2ro 

(c) current sharing analysis for n devices:– ro = 0

When more than two devices are parallel connected, sharing can be enforced with the multiple
transformer technique shown in figure 11.8c, where the n transformer secondary windings are series
connected. Each transformer has a turns ratio of η = Np:Ns, and the magnetising inductance is assumed
to be on the primary side of each transformer.
The semiconductor devices are assumed to have a constant on-state voltage vo. The total current is IT,
and zero commutation inductance is assumed.

Using Kirchhoff’s voltage law on the primary side:

Since the secondary voltages sum to zero
v s 1  v s 2  v s 3  ...  v sn  0 (11.35)
then the transformer primary voltages also sum to zero
Ns
v p 1  v p 2  v p 3  ...  v pn  v  v s 2  v s 3  ...  v sn   0 (11.36)
N p s1
Since the legs are parallel connected
VT 1  v p1 VT 2  v p 2  ..... VTn  v pn (11.37)

For worst case analysis, let one device (n = 1) operate at minimum on-state voltage, V T , while the other
n - 1 devices have a maximum on-state voltage VT , therefore potentially conduct less current than the
device operating at minimum voltage.

V  v  V  v  .....  V  v
T p1 T p T p (11.38)
These equations yield the following primary voltages
n 1   
 1  

v p1  V T V T  and v p 2  v p 3 ...  v pn   V T V T  (11.39)
n   n 

Using Kirchhoff’s current law on the primary side:

I T  I T 1  I T 2  ...  I TN (11.40)
But a thyristor current, which is the transformer primary current, can be expressed in terms of the
transformer secondary current plus the parallel magnetising current on the primary side. That is
N 1
I T i  i p i  iM i  s is  iM i  is  iM i (11.41)
Np 
where, because the secondary windings are series connected, the secondary current is the same for
each transformer. The transformer magnetising current iMi is the same for transformers i = 2 to n, iM.
Thus the total current
n n
1 
IT   IT i    i s  i M i 
i 1 i 1    (11.42)
1
I T  n i s  i M 1   n  1 i M


Using Kirchhoff’s voltage law on the secondary side:

Since the transformers are identical, each has the same value of magnetising inductance (self-
inductance) LM. Because the secondary windings are series connected the sum of the secondary
voltages, hence sum of primary voltages, are zero.
379 Power Electronics

v p1  v p2  v p 3  ... v p n  0
d iM1 d iM 2 d iM n
 LM  LM  ......  LM 0
dt dt dt
d i di  (11.43)
 LM  M 1   n  1 M   0
 dt dt 
d
 LM i   n  1 i M   0
dt  M 1

The component inside the square bracket must be a constant.

i M 1   n  1 i M  c (11.44)
Substituting the constant c into equation (11.42) gives the secondary current as
1
i s   IT  c  (11.45)
n
In conjunction with Faraday‟s equation, the magnetising current is a linear function of time, starting from
zero. Applying these conditions to the worst case device, T 1, then as the magnetising current in
transformer Tr1 increases and the associated thyristor current IT1 increases, from equation (11.44), the
opposing magnetising current in the other transformers reduces the associated device principal current.
At the maximum on-time, the current in device T1 should not exceed its permitted rated limit, Im.
1
i M 1 t    v p 1t (11.46)
LM
From equation (11.39), when t = τ, the maximum magnetising current, in terms of the device voltage
extremes, is
1 n 1   

i M 1 t     iM 1   V T V T    (11.47)
LM n  
Re-arranging gives the necessary minimum transformer self-inductance with respect to the primary side.

n 1  
1 
 1 n 1
LM  V T V T      
  VF   (11.48)
M1 i
n   i M 1 n
The maximum magnetising current iM 1 can be expressed in terms of devices current rating Im and
device percentage derating, pd, or device utilisation, kp =1 - pd.
If the device current rating is Im, then n devices in parallel can theoretically conduct n×Im. When derated
by pd to kp, the total current is kp×nIm where each device initially conducts kp×Im. The current in the
worst-case device increases from kpIm to Im ( iM 1  1  k p  I m  pd  I m ) in the maximum period the
device conducts, τ.
I  k I  i M  k I  1  k  I  I
T p m p m p m m (11.49)

n×Im theoretical current

limit
pd×nIm
kpnIm Derated
current

Im Device rating Im
IT1 pd×Im
kp Im kp Im
 nk p 1
Im  
1  kp
Im  n 1 
n 1
t

o τ
Figure 11.10. External forced current sharing network using series connected secondary windings.
Chapter 11 Series and Parallel Device Operation, and Interferences 380

The current in each of the remaining n -1 devices decreases from kp Im by (1-kp) Im /n -1 to

 1  kp  nk  1 
I T  k pI m  I m  Im  p  (11.50)
n 1  n 1 
such that the necessary total current is maintained:
  nk  1 
IT  n  1 I T  I m  n  1 I m  p   nkp I m
 n 1 
These various current components are shown in figure 11.10.
By assuming a current quadratic dependence on time, equations similar to equations (11.26) can be
obtained.

Example 11.4: Transformer current sharing – static and dynamic current balancing

Two thyristors with the same forward conduction characteristics as the diodes in figure 11.6 are parallel
connected using the coupled circuit arrangement in figure 11.8a.
The maximum current rating for each device is Im, 100A; hence with suitable forced sharing a 190A
combination should be possible. Using the network in figure 11.9a for current sharing, it is required that
no more than rated current flow through the lower conducting voltage device, D 1. Specify the per cent
overall derating and the necessary sharing transformer properties assuming a half-wave, 180º
conduction, phase-controlled, 50Hz, highly inductive load application.
What are the transformer core reset requirements?
Estimate inductance requirements if the thyristors have a static on-state resistance of 1mΩ.

Solution

As in example 11.3, the derating for the parallel situation depicted in figure 11.6, without external
sharing, is
 170A 
pd  1 - ×100 = 15 per cent (k p =0.85)
 2×100A 
With forced transformer sharing, the objective derating is reduced from 15% to
 190A 
pd  1 -  ×100 = 5 per cent (k p =0.95)
 2×100A 
When the two thyristors are turned on, the magnetizing current is assumed zero and transformer
action will force each device to conduct 95A, giving 190A in total. From figure 11.6, the voltage
difference between the thyristors, ΔVF is about 0.1V, thus the transformer winding voltages will be
0.05V each, with polarities as shown in figure 11.9a. In time the magnetizing current increases and
the current in T1 increases above 95A due to the increasing magnetizing current, while the current
in T2 decreases below 95A, such that the total load current is maintained at 190A.

The worst case conduction period in this ac application, giving maximum magnetising current, is for
180º conduction, that is, 10ms. Thus it is required that T 1 current rises to 100A and T2 current falls
to 90A at τ =10ms, that is, the magnetising current is 100A - 90A = 10A.
Substitution into equation (11.31) gives
1 10ms 1
LM  ½
IM  0
v dt  ½ 
10A
 0.1V×10ms = 50μH

where it is assuming that the voltage differential ΔVF between the two devices is constant during
the conduction period. In fact figure 11.9b shows that the voltage difference decreases, so
assuming a constant value gives an under-estimate of requirements.

The core volt-μs during conduction is 0.05V×10ms = 500 V-μs. That is, during core reset the
reverse voltage time integral must be at least 500 V-μs to ensure the core flux is reset,
(magnetising current reduced to zero).
Using equation (11.34), with ro = 1mΩ, gives
2ro 2  1mΩ  10ms
LM    90μH
 v o   0.1V 
n   n  0.1V  10A  2  1mΩ 
 v o  I M 2ro   

The inductance, 50μH, given by equation (11.31) when neglecting model resistance, under-estimates
requirements.
♣
381 Power Electronics

11.3 Interference

Electromagnetic phenomenon, whether intentional or unintentional by-products, tend to result in

undesirable consequences in power electronic circuits and equipment, in terms of generated noise and
susceptibility.

 EMC - Electromagnetic Compatibility

The ability of a component or its associated system to operate and function correctly in its
intended electromagnetic environment.

 EMI - Electromagnetic Interference

Electromagnetic emissions from a component or its associated system that interfere with the
normal operation of another component or system, or the emitting component or system itself.

11.3.1 Noise

RFI noise (electromagnetic interference, EMI) and the resultant equipment interaction is an area of
power electronic design that is often fraught, under-estimated or overlooked.
EMI is due to the effects of undesired energy transfer caused by radiated electromagnetic fields or
conducted voltages and currents. The interference is produced by a source emitter and is detected by a
susceptible victim via a coupling path. The source itself may be a self-inflicted victim. The effects of this
interference can vary from simple intermittent reset conditions to a catastrophic failure.

differential mode common mode + +

+ - I1 I2
I I (symmetrical) (asymmetrical)

source victim source victim

parasitic C Vcm1 Vcm2

Vdm

(a) (b)

L L

Lcm

N N

(c)

L L
Ldm
Lcm

Ldm N
N

Ldm E
E
(d)

Figure 11.11. Common mode & differential mode mains supply noise filtering: (a) differential mode noise
paths; (b) common mode noise paths; (c) simple L-C mains filter; and (d) high specification mains filter.
Chapter 11 Series and Parallel Device Operation, and Interferences 382

The coupling path may involve one or more of the following four coupling mechanisms.

 Conduction - electric current, I

 Radiation - electromagnetic field, Zo
 Capacitive coupling - electric field, E
 Inductive coupling - magnetic field, H

11.3.1i - Conducted noise is coupled between components through interconnecting wiring such as
through power supply (both ac and dc supplies) and ground wiring and planes. This common
impedance coupling is caused when currents from two or more circuits flow through the same wiring
impedance. Coupling can also result because of common mode and differential (symmetrical) currents,
which are illustrated in figure 11.11. Two forms of common mode currents exist. When the conducting
currents are equal such that Vcm1 = Vcm2, then the common mode currents are termed asymmetrical,
while if Vcm1 ≠ Vcm2, then the currents are termed non-symmetrical.

11.3.1ii - Radiated electromagnetic field coupling can be considered as two cases, namely

 near field, r   / 2 , where radiation due to electric fields, E, and

magnetic fields, H, are considered separate
 far field, r   / 2 , where the coupling is treated as a plane wave.
The boundary between the near and far field is given by r   / 2 where λ is the noise wavelength and
r is distance from the source.
As a reference impedance, the characteristic impedance of free space in the far field Zo, is given by E /
H, which is constant, o / o  120 = 377 .
-3 -2 -1
In the near field region, the equation r (as opposed to r and r ) term dominates field strength.
-3 -2
 A wire currying current produces E α r and H α r , (common mode radiation)
o thus the electric field E dominates and the wave impedance Z > Zo.
-3 -2
 A wire loop carrying current produces H α r and E α r , (differential mode radiation)
o thus the magnetic field H dominates and the wave impedance Z < Zo.
In the near field, interference is dominated by the effective input impedance, Zin, of the
susceptible equipment and the source impedance Rs of its input drive.
 electric coupling increases with increased input impedance, while
 magnetic coupling decreases with increased input impedance.

That is, electric fields, E, are a problem with high input impedance, because the induced
current results in a high voltage similar to that given by equation (11.51)
dv
v  i c  Rs / /Z in  C c  Rs / /Z in (11.51)
dt
while magnetic fields, H, are a problem with low input impedance, because the induced
voltage results in a high current similar to that given by equation (11.52)
di
vc M
i   dt (11.52)
Rs / /Z in Rs / /Z in
-1
In the far field the r term dominates.
In the far field region both the E and H fields are in phase and at right angles. Importantly
their magnitudes both decrease, inversely proportionally with distance r, so their
magnitude ratio remains constant. That is, in the far field the characteristic impedance
Z o  E / H  o / o =120 = 377 is constant. The far field radiation wave with this
constant impedance is termed a plane wave. The electric field component of the plane
wave tends to dominate interference problems in the far field region.
11.3.1iii - Electric field coupling is caused by changing voltage differences, dv/dt, between
conductors. This coupling is usually modelled by capacitance.
The changing electric field produces a current according to i = Cc dv/dt, where coupling capacitance Cc
is dependant on distance of separation, area, and the permittivity of the media. The effect of the
produced current is dependant on the source impedance Rs and the effective input impedance, Zin, of
the victim equipment as given by equation (11.51).
11.3.1iv - Magnetic field coupling is due to changing currents, di/dt, flowing in conductors. This
coupling mechanism is usually modelled by a magnetically coupled circuit, or a transformer, according
to v = Mdi/dt, where the resultant current is given by equation (11.52). The mutual inductance M is
related to loop area, orientation, separation distance, and screening and its permeability. This induced
383 Power Electronics

voltage is independent of any ground connection or electrical connection between the coupled circuits.
Magnetic field problems tend to be at low frequencies. Below 100kHz effective screen materials (due to
the skin effect) are steel, mu-metal (μr = 20,000), and permalloy, while at higher frequencies the good
electrical conduction properties of copper and aluminium are more effective despite there much lower
permeabilities.

11.3.2 Mains filters

The conducted ac mains borne noise can be attenuated to safe levels by filtering. The simplest type of
filter is an inductor in series with the load in order to reduce any current di/dt changes. It is usual
practice to use L-C filtering, which gives second-order attenuation. The typical circuit diagram of an ac
mains voltage filter, with common mode noise filtering, is shown in figure 11.11c. The core inductance is
only presented to any ampere-turn imbalance (common mode current), not the much larger principle
throughput (go and return) ac current, hence the core dimensional requirements can be modest. Extra
non-coupled inductance is needed for differential mode filtering, as shown in figure 11.11d. Only the
higher frequency noise components can be effectively attenuated since the filter must not attenuate the
50/60 Hz ac mains component.

11.3.3 Noise filtering precautions

For power electronics, circuit noise suppression and interaction is ultimately based on a try-it and see
approach. Logic and experience do not necessarily prevail. The noise reduction precautions to follow
are orientated towards power electronics applications.
Good circuit layout and construction (incorporated at the initial design stage) can greatly reduce the
radiated noise, both transmitted and received. Obvious starting points are minimising wire loop lengths,
using ground planes, capacitor decoupling, twisted wire pairs, and judicious placement of magnetic
components. Use opto-couplers, not only to isolate signals but to allow flexible signal grounding that can
bypass ground power noise around sensitive circuitry. Sensitive electronic circuitry should be rfi
radiation protected by copper (electric and high frequency magnetic) or mild steel (low frequency
magnetic) sheeting, depending on the type of radiation and frequency. Shielding, including electrically
isolated heatsinks, should be electrically connected to a point that minimises interference. This may
involve connection to supply rails (one of positive, zero, negative) or ground.
An R-C snubber across a diode decreases dv/dt while a series inductive snubber will limit di/dt. Mains
ac supply series input inductors for bridge rectifiers (plus diode R-C snubbers) decrease the amount of
diode recovery noise injected back into the mains and into the equipment. Most effective are common
mode transformers in all input and output connection cabling. Although differential mode line inductors
may be effective in decoupling input power lines, stability issues can arise when used in output cables.
Figure 11.12 outlines the frequency bands where the various interference modes can be expected, and
the techniques commonly used to suppression that interference.

Interference
differential mode commonmode
common mode radiated field type

Propagation
conducted coupling
coupled emc field mode

101 102 103 104 105 106

frequency (kHz) f

X - type capacitance Y - type capacitance grounding shielding Remedial

Fe powder chokes current balanced chokes Cu actions

Figure 11.12. Expected interference types, mode of propagation,

and remedial techniques depending on the interference frequency.

In ac circuit applications, zero-voltage turn-on and zero-current turn-off minimise any rapid changes in
current, thus reducing radiation. To minimise freewheel diode recovery noise, slow down switch turn-on.
To minimise interactive noise effects, high noise immune circuit designs can be employed which utilise
mos technology. The high-voltage input thresholds of cmos logic (4000 series), 74AC (not ACT) logic
Chapter 11 Series and Parallel Device Operation, and Interferences 384

series, and power MOSFETs and IGBTs (high gate threshold and capacitance), offer circuit noise
immunity. Gates with Schmitt trigger (hysteresis) inputs are preferable, for example, 4093, 74AC132,
etc. Since noise possesses both magnitude and duration, the much slower response times (along with
high input thresholds) of 4000 HEF series cmos (or HEF series for a wider operating temperature range)
may result in better noise immunity in applications requiring clock frequencies below a few megahertz.
DSP core operating voltages below a few volts necessitate: the use of multilayer pcbs with ground
planes, carefully layout separating analogue and digital circuitry (& grounding), low inductance ceramic
chip decoupling, watchdog circuitry, etc. Do not avoid using analogue circuitry (±12V), if it is applicable.

11.4 Earthing

The planet earth is electrically neutral. This means that it has the same number of electrons and
protons, so their charges cancel out overall. Thus the earth has an electric potential of zero. The earth
wire of a mains plug is connected to the actual earth, terra firma (Terre/French, terra/Latin for earth).
Because of the size of the earth it is not possible to charge up anything wired to earth.

This inability to charge equipment connected to the earth is the reason that many systems have their
metal boxes wired electrically to the earth. This means that any fault inside the equipment cannot
produce a dangerous voltage on its enclosing metal box, so no electric shock is possible from touching
the outside of the box even if internally there is an electrical fault.
Copper is one of the better and commonly used materials for earth electrodes and underground
conductors, especially for a buried earth electrode.
The reasons for having an earthed system are:
 To provide a sufficiently low impedance to facilitate satisfactory protection operation
under fault conditions.
 To ensure that living beings in the vicinity of substations are not exposed to unsafe
potentials under steady state or fault conditions.
 To retain system voltages within reasonable limits under fault conditions (such as
lightning, switching surges or inadvertent contact with higher voltage systems), and
ensure that insulation breakdown voltages are not exceeded.
 Custom and practice.
 Graded insulation can be used in power transformers.
 To limit the voltage to earth on conductive materials which enclose electrical
conductors or equipment.
 To stabilise the phase to earth voltages on electricity lines under steady state
conditions, e.g. by dissipating electrostatic charges which have built up due to
clouds, dust, sleet, etc.
 A means of monitoring the insulation of the power delivery system.
 To eliminate persistent arcing ground faults.
 To ensure that a fault which develops between the high and low voltage windings of
a transformer can be dealt with by primary protection.
 To provide an alternative path for induced current and thereby minimise the electrical
“noise” in cables.
 Provide an equipotential platform on which electronic equipment can operate.

earth ground chassis

Figure 11.13. Three different grounding symbols.

As shown in figure 11.13, various symbols are used on circuit diagrams to represent earth or ground
potential. It is usually assumed that they all mean „zero volts‟, that is, the place from which all other
voltages in the circuit are referenced or measured. In practice, the meanings of the symbols are slightly
different, specifically:
 The earth symbol indicates a place actually wired to terra firma via the mains wires provided
or using a wire to a non-corroding metal plate buried in the earth.
 The ground symbol usually indicates a connection back to a place in the power supply,
which provides the energy required by the circuit in order to work. It is usually assumed that
this place in the power supply is connected to the earth.
385 Power Electronics

 The chassis symbol means a connection to a metal box enclosing the circuit. As far as the
circuit is concerned, this metal box is as good a place as the earth for referencing voltages.
From the point of view of most electronic circuits, this functions just like an earth connection,
however it need not actually be connected to the earth. Hence the chassis of some
equipment can potentially be charged up to a high voltage, with respect to the earth.

In most cases, the ground and chassis connections are just indirect paths to earth. However, in some
cases, for example, a portable radio using batteries, or the electrics in a vehicle, the ground or chassis
represent a sort of „local‟ or „floating‟ version of the earth used as the zero volts reference point. In most
vehicles, the electrical equipment is powered from a 12(/24)V battery. This provides 12V (positive or
negative) with respect to the metal bodywork (the chassis). So far as all the vehicle electronics is
concerned, it experiences only 12V. However this does not prevent an electric shock when stepping in
or out of the vehicle. This is because the chassis may sometimes become charged up to a high voltage
with respect to the earth due to movement of the insulating rubber tyres.

There are several factors which influence or determine the size required for a circuit protective
2
conductor. A minimum cross-sectional area of 2.5mm copper is required for any separate circuit
protective conductor, that is, one which is not part of a cable or formed by a wiring enclosure or
contained in such an enclosure.
An example would be a bare or insulated copper conductor clipped to a surface, run on a cable tray or
fixed to the outside of a wiring enclosure. Such a circuit protective conductor must also be suitably
protected if it is liable to suffer mechanical damage or chemical deterioration or be damaged by
electrodynamic effects produced by passing earth fault current through it. If mechanical protection is not
2
provided the minimum size is 4mm copper or equivalent.
There are two methods for sizing protective conductors including earthing conductors.
The easier method is to determine the protective conductor size from standard tables but this may
produce a larger size than is strictly necessary, since it employs a simple relationship to the cross-
sectional area of the phase conductor(s).
The second method involves a formula calculation.
The formula is commonly referred to as the adiabatic equation and is the same as that used for short-
circuit current calculations.
It assumes that no heat is dissipated from the protective conductor during an earth fault and therefore
errs on the safe side. Even so, application of the formula will in many instances result in a protective
conductor having a smaller cross sectional area than that of the live conductors of the associated circuit.
This is quite acceptable.
2
The nominal cross-sectional area of the conductor in mm , S, shall be not less than the value given by:
S  I 2t / k
I is the value in amperes (rms for ac) of the fault current for a fault of negligible impedance, which
can flow through the associated protective device, accounting for the current limiting effect of
2
the circuit impedances and the limiting capability (I t) of that protective device. Account is
taken of the effect, on the resistance of circuit conductors, of their temperature rise as a result
of over-current.
t is the operating time of the disconnecting device in seconds corresponding to the fault current I
amperes.
k is a factor taking account of the resistivity, temperature coefficient and heat capacity of the
conductor material, and the appropriate initial and final temperatures.

11.4.1 Earth and neutral

International standard IEC 60364 distinguishes three categories of earthing arrangements, using the
two-letter codes, viz., TN, TT, and IT.

The first letter indicates the connection between earth and the three-phase power-supply equipment
generator or transformer:
T: (Latin→French: terra): Direct connection of a point with earth;
I: No point is connected with earth (isolated), except perhaps via a high impedance.
The second letter indicates the connection between earth and the electrical device being supplied:
T: Direct connection of a point with earth
N: Direct connection to neutral at the origin of installation, which is connected to the earth
The remaining letter:
C: Combined neutral and protective earth functions (same conductor).
S: Separate neutral and protective earth functions (separate conductors).
Chapter 11 Series and Parallel Device Operation, and Interferences 386

1. TN networks
In a TN earthing system in Table 11.1, one of the points in the generator or transformer is connected
with earth, usually the star point in a three-phase system. The body of the electrical device is connected
with earth via this earth connection at the transformer.
The conductor that connects the exposed metallic parts of the consumer's electrical installation is called
protective earth (PE: Ground). The conductor that connects to the star point in a three-phase system, or
that carries the return current in a single-phase system, is called neutral, N.

Three variants of TN systems are:

i. TN−S:- Conductors PE and N are separate and are connected together only near the power
source. That is the supplier provides a separate earth conductor back to the substation. This is
most commonly done by having an earthing clamp connected to the sheath of the supply cable.
This arrangement is the current standard for most residential and industrial electric systems in
North America and Europe.
ii. TN−C:- No separate earth conductors exist anywhere. A combined PEN conductor fulfils the
functions of both a PE and an N conductor. Rarely used scheme.
iii. TN−C−S:- Part of the system uses a combined PEN conductor, which is at some point split
into separate PE and N lines. The combined PEN conductor typically occurs between the
substation and the entry point into the building, and separated in the service head. The earthing
conductor is connected to the supplier's neutral. In the UK, this system is also known as
protective multiple earthing (PME), because of the practice of connecting the combined neutral-
and-earth conductor to real earth at many locations, to reduce the risk of broken neutrals - with
a similar system in Australia being designated as multiple earthed neutral (MEN).

Table 11.1 Neutral/earth systems

generator or generator or generator or

transformer transformer transformer
L1 L1 L1

L2 L2 L2

L3 L3 L3

N N/E N

E E

T T T S
earth consumer earth consumer earth consumer

TN-S: TN-C: TN-C-S:

Separate protective earth (PE) and Combined PE and N conductor Combined PEN conductor from the
neutral (N) conductors from the all the way from the transformer transformer to the building
transformer to the consuming device, to the consuming device. distribution point, but separate PE
not connected together at any point and N conductors in fixed indoor
after the building distribution point. wiring and flexible power cords.

It is possible to have both TN-S and TN-C-S supplies from the same transformer. For example, the
sheaths on some underground cables corrode and stop providing good earth connections, so homes
with bad earths are converted to TN-C-S.

2. TT network
In a TT earthing system, in figure 11.14a, the protective earth connection of the consumer is provided by
a local connection to earth, independent of any earth connection at the generator. No earth is provided
by the supplier; the installation requires its own (one or more) earth rod (common used with overhead
supply lines).
The advantage of the TT earthing system is that it is clear of high and low frequency noises that come
through the neutral conductor from the connected equipment. TT is preferred for special applications like
telecommunication sites that benefit from interference-free earthing. Also, TT does not have the risk of a
broken neutral.
In locations where power is distributed overhead and TT is used, installation earth conductors are not at
risk should any overhead distribution conductor be fractured by, say, storm damage.
Before RCDs, the TT earthing system was unattractive for general use because of its poor capability of
accepting high currents in the case of a live-to-PE short circuit (compared to TN systems). The TT
earthing system is attractive for premises where all AC power circuits are RCD-protected.
387 Power Electronics

The TT earthing system is used throughout Japan, with RCD units in most industrial settings. This can
impose added requirements on variable frequency drives and switched-mode power supplies which
often have substantial filters passing high frequency noise into the ground conductor.

generator or generator or
transformer transformer
L1 L1

L2 L2

L3 L3

T T I T

earth consumer earth (a) (b) consumer earth

Figure 11.14. Earth/neutral systems: (a) TT network and (b) IT network.

3. IT network
In an IT network, in figure 11.14b, the electrical distribution system has no connection to earth, or it has
only a high impedance connection. In such systems, an insulation monitoring device is used to monitor
the impedance. The supply may be embedded generation or a portable generator with no earth
connection, so the installation has its own earth rod.

NB. House grounding is normally established by connecting (clamping) the household earth system wire
to a metal gas/water pipe (stake-less). Although this connection may appear satisfactory, much unseen
piping once underground may be made of plastic – an insulator.

11.5 Isolation (galvanic)

Incorporating isolation, both electrically and physically, into a system has many functions: preventing
ground loops (11.3.3) – including static and dynamic channel cross talk, rejecting common-mode voltage
– noise reduction (11.3.1), allowing two circuits to operate at different reference voltage levels (level
shifting), protecting equipment from surges, lightening strikes, etc., and providing electrical safety (11.4).
Wireless type techniques are mainly reserved for remote monitoring involving low band width
temperature, vibration, deflection, speed, etc. type measurements. Isolation where the ground wire is
passes through the system, as with transformers or a misconception with UPS, are not considered.

Difference between isolation and insulation

In terms of power electronics, isolation refers to systems that do not share a common electrical
reference or ground. The level of isolation is insulation which is a measure of the impedance (related to
voltage breakdown) separation between systems not sharing a common ground. For example, a switch
isolates a light bulb from the ac mains, but the switch air gap has a voltage insulation breakdown level.
The same reasoning can be applied to a transformer - the primary and secondary are physical isolated
(separated), but the two windings have an interwinding insulation voltage break down level due to the
enamel coating, physical construction, etc. IGBTs are available in modules with an insulated ceramic
base plate arrangement, but have an isolation test voltage rating.

11.5.1 Isolation problem and related measurements

i Ground Loops
Ground loops a common source of noise in power electronics applications. They occur when two
connected terminals in a circuit are at different ground potentials, causing current to flow between the
two terminals. The local system ground can be several volts above or below the ground of the other
system, and nearby lightning strikes can cause the difference to rise to several hundreds or thousands
of volts. This additional voltage can cause significant error in the measurement (notwithstanding a
catastrophic fault), but the current that causes it can also couple voltages in nearby connections. These
voltage errors can appear as transients or periodic signals. For example, if a ground loop is formed with
50/60Hz AC power lines, the unwanted AC signal appears as a periodic voltage error in a measurement.
Chapter 11 Series and Parallel Device Operation, and Interferences 388

When a ground loop exists, the measured voltage, Vm, in figure 11,15 is the sum of the signal voltage,
Vs, and the potential difference, ΔVg, which exists between the signal source ground and the
measurement system ground (as shown in Figure 11.15). This potential is generally not a DC level; thus,
the result is a noisy measurement system often showing power-line frequency (50/60 Hz) components in
the readings.

Fig. 11.15 Ground loop noise.

To avoid ground loops, ensure that there is only one ground reference in the measurement system, or
use isolated instrumentation. Using isolated hardware near eliminates the path between the ground of
the source and the secondary circuit, be it a measurement device or circuit, thus preventing any current
from flowing between multiple ground points.

ii Common-mode Voltage
An ideal differential measurement system responds only to the potential difference between the two op
amp terminals, the +ve and -ve inputs. The differential voltage across the circuit pair is the desired
signal, yet an unwanted signal may exist that is common to both sides of a differential circuit pair. This
voltage is known as common-mode voltage. An ideal differential measurement system will reject, rather
than measure, the common-mode voltage. Practical devices, however, have several limitations, such as
common-mode voltage range and common-mode rejection ratio (CMRR), which limit this ability to reject
the common-mode voltage.

The common-mode voltage range is defined as the maximum allowable voltage swing on each input
with respect to the measurement system ground. Violating this constraint results not only in
measurement error, but also in possible system damage.

Common mode rejection ratio is the ability of a measurement system to reject common-mode voltages.
Amplifiers (or an electronic circuit)) with a higher common-mode rejection ratio is more effective at
rejecting common-mode voltages. The common-mode rejection ratio (CMRR) is shown graphically in
Figure 11.16 and is defined as the logarithmic ratio of differential gain to common mode gain, viz.:

Differential Gain
CMRR  dB   20 log (11.53)
Common  Mode Gain

Fig. 11.16 Common mode voltage rejection.

389 Power Electronics

In a non-isolated differential measurement system, an electrical path still exists in the circuit between
input and output. Therefore, electrical characteristics of the amplifier limit the common mode signal level
that can be applied to the input. With the use of isolation amplifiers, the conductive electrical path is
eliminated and the common-mode rejection ratio is increased.

11.5.2 Isolation mechanisms

Physical isolation, a basic form of isolation, is where there is a physical barrier (air, vacuum, insulator, or
any non-conductive material) between two electrical systems. With pure physical isolation, no signal
transfer exists between electrical systems. With isolated electrical systems, transfer, or coupling, of
energy across the isolation barrier is required.

There are three basic types of electrical isolation that can be used, in power electronic, signal and data
acquisition systems:

i Optical Isolation (figure 11.17)

Optical isolation is common in digital isolation systems. The media for transmitting the signal is light and
the physical isolation barrier, typically an air gap. The light intensity is proportional to the measured
signal. The light signal from a photo diode is transmitted across the isolation barrier and detected by a
photoconductive element on the other side of the isolation barrier.

Isolation amplifier

light radiation

Figure 11.17. Optocoupling.

ii Electromagnetic Isolation (figure 11.18)

Electromagnetic isolation uses a transformer to couple a signal across an isolation barrier by generating
an electromagnetic field proportional to the electrical signal. The field is created and detected by a
coupled pair of conductive coils. The physical barrier can be air or another non-conductive barrier.

Isolation amplifier

magnetic - transformer

Figure 11.18. Magnetic (coreless) transformer coupling.

iii Capacitive Isolation (figure 11.19)

With capacitive isolation, an electromagnetic field changes the level of charge on the capacitor. This
charge is detected across the barrier and is proportional to the level of the measured signal.

Isolation amplifier

capacitive

Figure 11.19. Capacitive isolation.

Chapter 11 Series and Parallel Device Operation, and Interferences 390

Reading list

Grafham, D.R. et al., SCR Manual,

General Electric Company, 6th Edition, 1979.

Williams, T., EMC for Product Designers,

Newnes, 2nd Edition, 1998.

Problems

11.1. Derive an expression for the worst case maximum allowable voltage-sharing resistance for n
series devices each of voltage rating VD and maximum leakage Im across a supply Vs. The
resistance tolerance is ± 100a per cent and the supply tolerance is ± 100b per cent.
If Vs = 1500 V, VD = 200 V, Im = 10 mA, n = 10 and tolerances are ±10 per cent, calculate
resistance and maximum total power losses if
i. tolerances are neglected
ii. only one tolerance is considered
iii. both tolerances are included.
[i. R <5.5 kΩ, 63.8 W; ii. R <2.1 kΩ, 185 W; R <3.9 kΩ, 91 W; iii. R <280 Ω, 1234 W].

11.2. Derive a power loss expression for a voltage-sharing resistance network in which both supply
and resistance tolerances are included. Assume a dc reverse bias of duty cycle δ.

11.3. Derive the power loss expression for an SCR string with voltage-sharing resistance and an ac
supply.

11.4. Two diodes modelled as in figure 2.4a having characteristics approximated in the forward
direction by
Diode D1: VF = 1.0 + 0.01 IF (V)
Diode D2: VF = 0.95 + 0.011 IF (V)
are connected in parallel. Derive general expressions for the voltage across and the current in
each diode if the total current is 200 A.
At what total current and voltage will the diodes equally share?
[102.4 A, 97.6 A, 2.02 V; 100 A, 1.5 V]

11.5. In problem 11.4, what single value of resistance in series with each parallel connected diode
match the currents to within 1 per cent of equal sharing? Calculate the resistor maximum power
loss.
How will the current share at IT = 100 A and IT = 500A with the balancing resistors.
[14.5 mΩ, 148 W; 50 A, 50 A; 254 A, 246 A]

A Zener diode has an I-V characteristic described by I = kV . What percentage increase in

30
11.6.
voltage will increase the power dissipation by a factor of 1000?
[25 per cent]

11.7. What is the percentage decrease in the dynamic resistance of the Zener diode in question
11.6?
[99.845 per cent]

11.8. A string of three 2,600 V thyristors connected in series is designed to withstand an off-state
voltage of 7.2 kV. If the compensating circuit consists of a series 33 Ω, 0.01 μF snubber in
parallel with a 24 kΩ resistor, across each thyristor, and the leakage currents for the thyristors
are 20 mA, 25 mA, and 15 mA, at 125°C, calculate the voltage across each thyristor, then the
discharge current of each capacitor at turn-on.
[2400 V, 2280 V, 2520 V, 72.73 A, 69.09 A, 76.36 A]
391 Power Electronics

11.9. The reverse leakage current characteristics of two series connected diodes are
I1 = -10 V1 + 0.14 (A) for V1 < -1400 V
-4
Diode D1:
I2 = -10 V2 + 0.16 (A) for V2 < -1600V
-4
Diode D2:
If the resistance across diode D 1 is 100 kΩ and VD1 = VD2 = -2000 V, what is the leakage current
in each diode and what resistance is required across diode D 2?
[0.34 mA, 0.36 mA, ∞]

11.10. Two high voltage diodes are connected in series as shown in figure 11.5a. The dc input voltage
is 5 kV and 10 kΩ dc sharing resistors are used. If the reverse leakage current of each diode is
25mA and 75mA respectively, determine the voltage across each diode and the resistor power
loss.
[2750 V, 2250 V, 756.25 W, 506.25 W]

11.11. The forward characteristics of two parallel connected diodes are

Diode D1: I1 = 200 V1 - 100 (A) for V1 ≥ 0.5 V
Diode D2: I2 = 200 V2 - 200 (A) for V2 ≥ 1V
If the forward voltage of the parallel combination is 1.5V, determine the forward current through
each diode.
[200 A, 100 A]

11.12 Two diodes are connected in parallel and with current sharing resistances as shown in figure
11.7. The forward I-V characteristics are as given in problem 11.11. The voltage across the
parallel combination is 2V and the balancing resistors are equal in value.
Calculate each diode voltage and current. Calculate resistor maximum power loss. Let Itot = 400A.
Chapter 11 Series and Parallel Device Operation, and Interferences 392

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