CHAPTER 17

DC to AC Inverters
– Switched Mode
Inversion is the conversion of dc power to ac power at a desired output voltage or current and
frequency. A static semiconductor inverter circuit performs this electrical energy inverting transformation.
The terms voltage-fed and current-fed are used in connection with the output from inverter circuits.
A voltage-source inverter (VSI) is one in which the dc input voltage is essentially constant and
independent of the load current drawn. The inverter specifies the load voltage while the drawn current
shape is dictated by the load. Being a voltage source, an open circuit output is allowable.
A current-source inverter (CSI) is one in which the source, hence the load current is predetermined and
the load impedance determines the output voltage. The supply current cannot change quickly. This
current is controlled by series dc supply inductance which prevents sudden changes in current. The load
current magnitude is controlled by varying the input dc voltage to the large inductance, hence inverter
response to load changes is slow. Being a current source, the inverter can survive an output short circuit
thereby offering fault ride-through properties, but an open circuit output is problematic.
In the case of a VSI, voltage control may be required to maintain a fixed output voltage when the dc
input voltage regulation is poor, or to control load power. The inverter output can be single-phase, three-
phase or multi-phase. Variable output frequency may be required for ac motor speed control where, in
conjunction with voltage or current control, constant (controlled) motor flux can be maintained.
Inverter output waveforms (either voltage or current) are usually rectilinear in nature and as such contain
harmonics which may lead to reduced load efficiency and performance. Load harmonic reduction can be
achieved by either filtering, selected harmonic-reduction chopping or pulse-width modulation.

The quality of an inverter output is normally evaluated in terms of its harmonic factor, ρ, distortion factor,
μ, and total harmonic distortion, thd. In section 15.7.2 these first two factors were defined in terms of the
supply current. For VSI inverters the factors are redefined in terms of the output voltage harmonics as
follows
Vn
n   n n n 1 (17.1)
V1
The distortion factor for an individual harmonic is
Vn 
n   n (17.2)
nV1 n
  Vn 2   
 n 
2

thd      /V   n    
2
(17.3)
n  2  n  
1
n 2 n 2  n 

The factor Vn /n is used since the harmonic currents produced in an inductive load attenuate with
frequency. The harmonic currents produce unwanted heating and torque oscillations in ac motors,
although such harmonic currents are not a drawback to the power delivered to a resistive heating load or
an incandescent lighting load. Harmonics reflected back into the input may be problematic.

17.1 DC-to-ac voltage-source inverter bridge topologies

17.1.1 Single-phase voltage-source inverter bridge

Figure 17.1a shows an H-bridge inverter (VSI) for producing an ac voltage and employing switches
which may be transistors (MOSFET or IGBT), or at high powers, thyristors (GTO or GCT). Device

BWW
Chapter 17 DC to AC Inverters – Switched Mode 712

conduction patterns are also shown in figures 17.1b and c. With inductive loads (not purely resistive),
stored energy at turn-off is fed through the bridge reactive feedback or freewheel diodes D 1 to D4. These
four diodes clamp the load voltage to within the dc supply voltage rails (0 to Vs).

17.1.1i - Square-wave (bipolar) output

Figure 17.1b shows waveforms for a square-wave output (2t1 = t2) where each device is turned on as
appropriate for 180°, (that is π) of the output voltage cycle (state sequence 10, 01, 10, ..).
The load current iL grows exponentially through T 1 and T2 (state 10) according to
di L
Vs  L  i LR (V) (17.4)
dt
When T1 and T2 are turned off, T3 and T4 are turned on (state 01), thereby reversing the load voltage
polarity. Because of the inductive nature of the load, the load current cannot reverse instantaneously
and load reactive energy flows back into the supply via diodes D 3 and D4 (which are in parallel with T 3
and T4 respectively) according to
di L
V s  L  i LR (V) (17.5)
dt
The load current falls exponentially and at zero, T 3 and T4 become forward-biased and conduct load
current, thereby feeding power to the load.

The output voltage is a square wave of magnitude ± Vs, figure 17.1b, and has an rms value of Vs.
For a simple R-L load, with time constant τ = L /R, during the first cycle with no initial load current,
solving equation (17.4) yields a load current
t
V  
i L (t )  s  1  e   (A) (17.6)
R 

Vab

o
a b
-

VL
o
+Vs

½ δ

-Vs

α
Β=π-α α
α Β=π-α

δ
1-δ
 
I I
T I1 T
 ½T ½T
I
α α

Figure 17.1. GCT thyristor single-phase bridge inverter:

(a) circuit diagram; (b) square-wave output voltage; and (c) quasi-square-wave output voltage.
713 Power Electronics


Under steady-state load conditions, the initial current is I as shown in figure 17.1b, and equation (17.4)
yields

Vs Vs   t
i L (t )    I e (A)
R  R  (17.7)
0  t  t 1  ½T (s)
for v L  Vs (V)

I 0 (A)

During the second half-cycle (t1 ≤ t ≤ t2) when the supply is effectively reversed across the load, equation
(17.5) yields
V V 
 t V    t 
t

i L (t )   s   s  I  e    s  1   1  tanh  1   e   (A)
R R  R   2
   (17.8)
0  t  t 2  t 1  ½T (s)
for v L  V s (V)

I 0 (A)
A new time axis 
has been used in equation (17.8) starting
at t = t1 in figure 17.1b. Since in steady-state
by symmetry,

I  - I , the initial steady-state current I can be found from equation (17.7) when, at t =
t1, iL = I yielding
t 1
 V 1  e  Vs
 t 
I  -I  s  tanh  1  (A) (17.9)
R t 1
R  2 
1e 
The zero current cross-over point tx, shown on figure 17.1b, can be found by solving equation (17.7) for t
= tx when iL = 0, which yields

I R 


t x   n 1 
 Vs 
  (17.10)
 IR 
  n 1   (s)
 V s 

The average thyristor current, I T , average diode current, I D , and mean source current, I s can be
found by integration of the load current over the appropriated bounds shown in the following integrals.
1 t1
I T   i L t  dt
t2 tx

(17.11)
1 V s V s   1
t t o

  t
  t  
   I e  e 
 
t2 R 1 o  R  
where iL is given by equation (17.7) and
1 tx
I D   i L t  dt
t2 0

(17.12)
1  Vs V s   x
t

  t  
 R  I  e  1 
t2  R x   
where iL is given by equation (17.8).
Inspection of the source current waveform in figure 17.1b shows that the average dc voltage source
current is related to the average semiconductor device currents by
Is  2 IT I D  
1 V s V s   1
t
 (17.13)
  t 1
    I   e  1 
t2 R R  
The steady-state mean power delivered by the dc supply and absorbed by the resistive load component
R is given by
1 t1
PL   V s i L t  dt  V s I s   I Lrms
2
R (W) (17.14)
t1 0
where iL(t) is given by equation (17.7). Rather than integration involving equations (17.7) and (17.8), the
mean load power can be used to determine the rms load current:
Chapter 17 DC to AC Inverters – Switched Mode 714

Vs I s
i Lrms  PL  (A) (17.15)
R R
The rms output voltage is Vs and the output fundamental frequency fo is f o  1T  1
2t1  1
t2 .

The instantaneous output voltage expressed as a Fourier series is given by

4 
1
V L  V s  sin n ot (V) (17.16)
 n odd n
where o  2 f o  2 / t 2  2 /T and for n = 1 the magnitude of the fundament frequency fo is 4
 Vs
which is an output rms fundamental voltage vo1 of
2 2
v o 1   Vs  0.90Vs (V) (17.17)
The load current can be expressed in terms of the Fourier voltage waveform series, that is
4 
1
i L (t )  V s  sin  n ot  n 
 n  1, 3, 5 nZ n

(17.18)
  I n sin n ot  n 
n  1, 3, 5

4 Vs I
where I n = whence I n rms= n
 nZ n 2
n o L
Z n  R 2  (n o L )2 n  tan1 such that cos 1  R
R Z1
The fundamental output power is
2 2
v  V 2 2 2
P1  I R   o 1  R  s   cos 1
2 2
(17.19)
1
 Z1  R   
The load power is given by the sum of each harmonic i2R power component, that is
2
I
 
 
PL    n 2  R  n 
n 1, 3, 5  1, 3, 5
I n2
rms
R  Vs I s (17.20)

Alternately, after integrating equation (17.14), with the load current from equation (17.8)
  1 
t
V s2  2 1  e   V s2  2  t 
PL   1 t1 
 1  tanh  1   (17.21)
R  t1
1  e  
 R  t1  2  

From PL = ir2ms R the rms loads current is
Vs 2 t 
i L rms  1 tanh  1  (17.22)
R t1  2 

The load power factor is given by

P i R 2
2 t 
pf   L rms  1 tanh  1  (17.23)
S i L rmsv rms t1  2 

17.1.1ii - Quasi-square-wave (multilevel) output

The rms output voltage form an H-bridge can be varied by producing a quasi-square output voltage (2t1
= t2, t0 < t1) as shown in figure 17.1c. After T1 and T2 have been turned on (state 10), at the angle α one
device is turned off. (One leg is phase shifted α relative to the other leg.) If T1 is turned off (and T4 is
turned on after a short delay), the load current slowly freewheels through T 2 and D4 (state 00) in a zero
voltage loop according to
di L
0L  i LR (V) (17.24)
dt
When T2 is turned off and T3 turned on (state 01), the remaining load current rapidly reduces to zero
back into the dc supply Vs, through diodes D3 and D4. When the load current reaches zero, T3 and T4
become forward biased and the output current reverses, through T3 and T4.
The output voltage shown in figure 17.1c consists of a sequence of non-zero voltages ±Vs, alternated
with zero output voltage periods. During the zero output voltage period a diode and switch conduct,
firstly T1 and D3 in the first period, and T3 and D1 in the second zero output period. In each case, a zero
voltage loop is formed by a switch, diode, and the load. The next two zero output sequences would be
T2 and D4 then T4 and D2, forming alternating zero voltage loops (sequence 10, 00, 01, 11, 10, ..) rather
than repeating a continuous T 1 and D3 then T3 and D1 sequence of zero voltage loops (sequence 10, 11,
715 Power Electronics

01, 11, 10, .. or sequence 10, 00, 01, 00, 10, ..). By alternating the zero voltage loops (between states
00 and 11), losses are uniformly distributed between the semiconductors, device switching frequency is
half that experienced by the load, and a finer output voltage resolution is achievable.
With reference to figure 17.1c, the load current iL for an applied quasi square-wave voltage is defined as
follows.
(i) vL > 0
V V  t
i LI (t )  s   s  I o  e  0  t  to (17.25)
R R 
for I o  0 (A)
(ii) vL = 0
 t
i LI I (t )  I e  0  t  t1  to (17.26)

for I  0 (A)
(iii) vL < 0
V s V s  t
i L (t )      I 1  e   i LI (t ) 0  t  to (17.27)
R R 
for I1  0 (A)

The currents I o , I , and I1 are given by
t 1 t o t 1
V e 
e 
Io   s (A) (17.28)
R t 1

1e 

t
 o
 V 1e 
I  s (A) (17.29)
R t
 1
1e 
I1   Io(A) (17.30)
The zero current cross-over instant, tx, shown in figure 17.1c, is found by solving equation (17.25) for t
when iL equals zero current.
 I R  IR
t x   n 1  o    n 1  1  (17.31)
 Vs   Vs 
The average thyristor current, I T , average diode current, I D , and mean source current, I s can be
found by integration of the load current over the shown bounds (assuming alternating zero volt loops).
1 t1 1 t 1 t o
I T   i L I t  dt  i LI I t  dt
2t 2  0
(17.32)
t 2 tx
where iL is given by equations (17.25) and (17.26) for the respective integrals, and
1 tx 1 t 1 t o
I D   i LI t  dt  i L II t  dt
2t 2  0
(17.33)
t2 0

where iL is given by equations (17.25) and (17.26) for the respective integrals.

Inspection of the source current waveform in figure 17.1c shows that the average source current is
related to the average semiconductor device currents by
1 to
I s   i LI (t )dt  2 I T  I D
t1 0
 (17.34) 
The steady-state mean load and dc source powers are
1 to
PL   V s i L t  dt  V s I s
t1 0
  I Lrms
2
R (W) (17.35)

where iL(t) is given by equation (17.25). The mean load power can be used to determine the rms load
current:
Vs I s
I Lrms  PL  (A) (17.36)
R R

The output fundamental frequency fo is f o  1

2t1  1
t2 .

The variable rms output voltage, for 0 ≤ α ≤ π, is

1 to
v rms 
t1  0
V s2dt  1    Vs (17.37)
Chapter 17 DC to AC Inverters – Switched Mode 716

and the output fundamental frequency fo is f o  1t 2 . This equation for rms output voltage shows that only
the nth harmonic can be eliminated when cos½n  0 , that is for    / n . In so eliminating the nth
harmonic, from equation (17.38), the magnitude of the fundamental is reduced to 4 Vs cos  n .
The output voltage VL in its Fourier coefficient series form is given by
4 
cos ½n 
VL  Vs  sin n ot (V) (17.38)
 n odd n

and for n = 1, the rms fundamental of the output voltage vo1 is given by
2 2
v o1  V s cos½  0.90 V s  cos½ (V) (17.39)

The characteristics of these load voltage harmonics are shown in figure 17.2.

An alternative approach is to consider the control of one leg phase shifted by β radians with respect of
the other leg. The phase output voltage for each leg, with respect to the supply (artificial) mid point, o, is

2V s
V ao   sin n ot
n
n 1,3,5,...

2V s
V bo   sin  n ot    
n 1,3,5,... n 

The output Vab is then given by the difference, that is


2V s 
2V s
Vao V bo  Vab   sin n ot   sin n ot    
n 1,3,5,... n n 1,3,5,... n

4V s
 
n 1,3,5,... n
sin½n  cos n ot

Expressing the phase shift angle β in terms of the delay angle α, where β=π-α, yields equation (17.38).

The load current can be expressed in terms of the Fourier voltage waveform series, that is
V 4 
cos ½n  
i L (t )  L  V s  sin n ot  n    I n sin n ot  n  (17.40)
ZL  n  1,3,.. nZ n n  1, 3, 5 ,..

4 Vs I
where I n = cos ½n  whence I n rms= n
 nZ n 2
n  L
Z n  R 2  (n o L )2 n  tan1 o
R
1
Vrms
0.9
V1
per unit

0.8

1


0.6 squarewave
α=0 Vrms
Output Voltage

0.9
n V1
0.4
0.9 cos ½n 
V3 0.9  cos½n
n 
V3
V5
0.2
V5
V7
V7
0
0 20° 40° 60° 80° 100° 120° 140° 160° 180°
0 ½π π

delay angle α α=π-β

Figure 17.2. Full bridge inverter output voltage harmonics
normalised with respect to square wave rms output voltage, Vrms=Vs.
717 Power Electronics

The load power is given by the sum of each harmonic i2R power component, that is
2
In
V I 
 
R 
PL   
1, 3, 5 


2
 I n2
rms
R s s (17.41)
n n  1, 3, 5,...

The load power and rms current can be evaluated from equations (17.21) and (17.22) provided the rms
voltage given by equation (17.37) replaces Vs. That is
V2
R 

PL  s 1    1 

2
t1
  t 
 2  

tanh  1    i Lrms
2
R (17.42)

Vs 2 t 
i L rms  1 1 tanh  1  (17.43)
R  t1  2 
The load power factor is independent of α and is given by equation (17.23), that is
P i R 2
2 t 
pf   L rms  1 tanh  1  (17.44)
S i L rmsv rms t1  2 
A variation of the basic four-switch dc to ac single-phase H-bridge is the half-bridge version where two
series switches (one pole or leg) and diodes are replaced by a split two-capacitor voltage source, as
shown in figure 17.3. This reduces the number of semiconductors and gate circuit requirements, but at
the expense of halving the maximum output voltage. Example 17.3 illustrates the half-bridge and its
essential features. Behaviour characteristics are as for the full-bridge, square-wave, single-phase
inverter but Vs is replaced by ½Vs in the appropriate equations. Only a rectangular-wave bipolar output
voltage can be obtained. Since zero volt loops cannot be created, no rms voltage control is possible.
The rms output voltage is ½Vs, while the output power is a quarter that of the full H-bridge.

Example 17.1: Single-phase H-bridge with an L-R load

A single-phase H-bridge inverter, as shown in figure 17.1a, supplies a 10 Ω resistance with inductance
50 mH, from a 340 V dc source. If the bridge is operating at 50 Hz (output), determine the average
supply current and the load rms voltage and current and steady-state current waveforms with

i. a square-wave output
ii. a symmetrical quasi-square-wave output with a 50 per cent on-time.
Solution
The time constant of the load, τ = 0.05mH/10Ω = 5 ms, t1 = 10ms and t2 = 20ms.

i. The output voltage rms value is 340 V ac.

Equation (17.9) gives the load current at the time when the supply polarity is reversed across the
load, as shown in figure 17.1b, that is
t o

V 1e 

I  I  s (A)
R t 1

1e 
where t1 = 10 ms. Therefore
 
340V 1  e 2
I  I   (A)
10Ω 1  e 2
= 25.9A
When vL = +340 V, from equation (17.7) the load current is given by
i L  34 - (34  25.9)  e -200t  34 - 59.9e -200t 0  t  10 ms
From equation (17.10) the zero current cross-over time, tx, occurs 5ms  n 1 + 25.9A×10Ω/340V 
= 2.83ms after load voltage reversal.
When vL = -340 V, from equation (17.8) the load current is given by
i L  -34  (34  25.9)  e -200t  -34  59.9e -200t 0  t  10 ms
The mean power delivered to the load is given by equation (17.14), that is
1 10ms
PL 
10ms 0 340V  {34 - 59.9  e -200t } dt

= 2755 W
From P  i 2R , the load rms current is

i Lrms  PL  2755W
 16.60A and I s  L  2755W
P
= 8.1A
R 10 Vs 340V
These power and rms current results can be confirmed with equations (17.21) and (17.22).
Chapter 17 DC to AC Inverters – Switched Mode 718

ii. The quasi-square output voltage has a 5 ms on-time, to, and a 5 ms period of zero volts.
From equation (17.37) the rms output voltage is
Vs 1  5ms / 10ms  Vs 2  240V rms .

The current during the different intervals is specified by equations (17.25) to (17.30). Alternately, the
steady-state load current equations can be specified by determining the load current equations for
the first few cycles at start-up until steady-state conditions are attained.
First 5 ms on-period when vL = 340 V and initially iL = 0 A
i L = 34 - 34 e -200t
and at 5ms, iL = 21.5A
First 5 ms zero-period when vL = 0 V
i L = 21.5 e -200t
and at 5ms, iL =7.9A
Second 5 ms on-period when vL = -340 V
i L = -34 + (34+7.9)  e -200t
with iL = 0 at 1 ms and ending with iL = -18.6 A
Second 5 ms zero-period when vL = 0 V
i L = -18.6 e -200t
ending with iL = -6.8A
Third 5 ms on-period when vL = 340 V
i L = 34 - (34+6.8)  e -200t
with iL = 0 at 0.9 ms and ending with iL = 19.0 A
Third 5 ms zero-period when vL = 0 V
i L = 19.0 e -200t
ending with iL = 7.0A
Fourth 5 ms on-period when vL = -340 V
i L = -34 + (34+7.0)  e -200t
with iL = 0 at 0.93 ms and ending with iL = -18.9 A
Fourth 5 ms zero-period when vL = 0 V
i L = -18.9 e -200t
ending with iL = -7.0A
Steady-state load current conditions have been reached and the load current waveform is as shown
in figure 17.1c. Convergence of an iterative solution is more rapid if the periods considered are
much longer than the load time constant (and vice versa).
The mean load power for the quasi-square wave is given by
1 5ms
PL =
10ms  0
340V  {34 - 41  e -200t } dt

= 1378 W
The load rms and supply currents are

i Lrms  PL  1378W  11.74A I s  PL  1378W = 4.05A

R 10 Vs 340V
♣

Example 17.2: H-bridge inverter ac output factors

In each waveform case (square and quasi-square) of example 17.1a calculate

i. the average and peak current in the switches

ii. the average and peak current in the diodes
iii. the peak blocking voltage of each semiconductor type
iv. the average source current
v. the harmonic factor and distortion factor of the lowest order harmonic
vi. the total harmonic distortion
719 Power Electronics

Solution

Square-wave

i. The peak current in the switch is I = 25.9 A and the current zero cross-over occurs at tx =2.83ms.
The average switch current, from equation (17.11) is
1 10ms
IT 
20ms  (34 - 59.9 e 200t ) dt
2.83ms

= 5.71 A

ii. The peak diode current is 25.9 A. The average diode current from equation (17.12) is
1 2.83ms
ID 
20ms 0 (34 - 59.9 e 200t ) dt

= 1.66 A
iii. The maximum blocking voltage of each device is 340 V dc.

iv. The average supply current is

 
I s  2 I T  I D  2  5.71A - 1.66A   8.10A
This results in the supply delivery power of 340Vdc × 8.10A = 2754W

v. From equation (17.16), with the third as the lowest harmonic, the distortion factors are
V3
hf  3   ⅓, that is, 33⅓ per cent
V1
V3
df  3   1 , that is, 11.11 per cent
3V1 9

vi. From equation (17.16)

2
Vn 
thd    n  /V1

 13    15    17   ......
2 2 2
=
= 46.2 per cent

Quasi-square-wave, α = ½π (5 ms) and from equation (17.31) tx = 0.93ms

i. The peak switch current is 18.9 A.

From equation (17.32) the average switch current, using alternating zero volt loops, is
1 5ms 1 5ms
IT 
20ms  (34 - 41e -200t ) dt 
0.93ms 40ms  0
19e -200t dt

= 2.18 + 1.50 = 3.68 A

ii. The peak diode current (and peak switch current) is 18.9 A. The average diode current, from
equation (17.33), when using alternating zero volt loops, is given by
1 1
 34  41e 200t  dt 
0.93ms 5ms
ID 
20ms  0 40ms  0
19e -200t dt

= 0.16 + 1.50 = 1.66 A

iii. The maximum blocking voltage of each device type is 340 V.

iv. The average supply current is

 
I s  2 I T  I D  2  3.68A - 1.66A   4.04A
This results in the supply delivery power of 340Vdc × 4.04A = 1374W

v. The harmonics are given by equations (17.1) to (17.3)

V3
hf   3   1 / 1 = ⅓, that is, 33⅓ per cent
V1 3 2 2

V3 3
df  3 =  = 1 , that is, 11.11 per cent
nV1 n 9
Chapter 17 DC to AC Inverters – Switched Mode 720

vi.
  Vn 2 
thd      /V1
 n 2  n  
2 2 2 2
 1   1   1   1 
  3    5    7    9   ... = 46.2 per cent
       
♣

Example 17.3: Harmonic analysis of H-bridge inverter with an L-R load

For each delay case (α = 0° and α = 90°) in example 17.1, using Fourier voltage analysis, determine
(ignore harmonics above the 10th):
i. the magnitude of the fundamental and first four harmonics
ii. the load rms voltage and current
iii. load power
iv. load power factor

Solution

The appropriate harmonic analysis is outline in the following table, for α = 0° and α = 90°.

n Zn Vn (α=0) In (α=0) Vn (α=90°) In (α=90°)

0.9Vs Vn 0.9V s Vn
R 2   2 50nL  cos ½n  
2
harmonic
n Zn n Zn
Ω V A V A
1 18.62 306 16.43 216.37 11.62
3 48.17 102 2.12 -72.12 -1.50
5 79.17 61.2 0.77 -43.28 -0.55
7 110.41 43.71 0.40 30.91 0.28
9 141.72 34 0.24 24.04 0.17
332.95V 16.59A 235.43V 11.73A

i. The magnitude of the fundamental voltage is 306V for the square wave and is reduced to 216V when
a phase delay angle of 90° is introduced. The table shows that the harmonics magnitudes reduce  1 n  as
the harmonic order increases.

ii. The rms load current and voltage can be derived by the square root of the sum of the squares of the
fundamental and harmonic components, that is, for the current
i rms  I 12  I 32  I 52  .....
The load rms currents, from the table, are 16.59A and 11.73A, which agree with the values obtained in
example 17.1a. Notice that the predicted rms voltages of 333V and 235V differ significantly from the
values in example 17.1a, given by V s 1    , namely 340V and 240.4V respectively. This is because
the magnitude of the harmonics higher in order than 10 are not insignificant. The error introduced into
the rms current value by ignoring these higher order voltages is insignificant because the impedance
increases approximately proportionally with harmonic number, hence the resultant current becomes
much smaller (insignificant) as the order increases.

iii. The load power is the load i2R loss, that is

PL  i rms
2
R  16.592  10  2752W for   0
PL  i rms
2
R  11.732  10  1376W for   90

iv. The load power factor is the ratio of real power dissipated to apparent power, that is
P i2 R 2752W
pf   rms   0.488 for   0
S i rmsv rms 16.59A  340V
P i2 R 1376W
pf   rms   0.486 for   90
S i rmsv rms 11.79A  240.4V
Equations (17.23) and (17.44) confirm the load power factor is 0.488, independent of α.
♣
721 Power Electronics

Example 17.4: Single-phase half-bridge inverter with an L-R load

A single-phase half-bridge inverter as shown in the figure 17.3, supplies a 10 Ω resistance with
inductance 50 mH from a 340 V dc source. If the bridge is operating at 50 Hz, determine for the square-
wave output
i. steady-state current waveforms
ii. the load rms voltage (the capacitors block any dc voltage output component)
iii. the peak load current and its time domain solution, iL(t)
iv. the average and peak current in the switches
v. the average and peak current in the diodes
vi. the peak blocking voltage of each semiconductor type
vii. the power delivered to the load, rms load current, and average supply current

Cl Cl Cl

Cu Cu
+ Cupper
VL
½Vs
+½Vs
170V ½Vs

½ δ
½Vs -170V
+ t1 t2 1

½Vs
tx I 12.95A
Clower 2.83ms
-½Vs

I -12.95A
(a) (b) (c)
Figure 17.3. GCT thyristor single-phase half-bridge inverter:
(a) circuit diagram; (b) square-wave output voltage; and (c) output voltage transfer function.

Solution

From examples 17.1 and 17.2, τ = 5ms.

i. Figure 17.3 shows the output voltage and current waveforms, with various circuit component current
waveforms superimposed. Note that no zero voltage loops can be created with the half-bridge. Only
load voltages ±½Vs , that is ±170V dc, are possible.

ii. The output voltage swing is ±½Vs, ±170V, thus the rms output voltage is ½Vs, 170V. This is, half that
of the full-bridge inverter using the same magnitude source voltage Vs, 340V dc.

iii. The peak load current is half that given by equation (17.9), that is
t 1
 ½Vs 1  e 
½Vs t 
I   tanh  1 
R t 1
R  2 
1e 
½×340V  10ms 
=
10Ω
× tanh    12.95A
 2×5ms 
The load current waveform is defined by equations (17.7) and (17.8), specifically
½Vs  ½Vs   t
i L I (t )    I  e 
R  R 
t
½  340V  ½  340V 
   12.95A   e 5ms
10  10 
t
 17  29.95 e 5ms for 0  t  10ms
and
½Vs
 ½V 
 t
i L II (t )     s  I  e 
R  R 
t
½×340V  ½×340V 
   12.95   e 5ms
10Ω  10Ω 
t
 17  29.95 e 5ms for 0  t  10ms
By halving the effective supply voltage, the current swing is also halved.
Chapter 17 DC to AC Inverters – Switched Mode 722

iv. The peak switch current is I  12.95A .

The average switch current is given by
t
1 10ms
IT  
20ms 2.83ms
(17  29.95e 5ms ) dt

= 2.86 A

v. The peak diode current is I = 12.95A .

The average diode current is given by
2.83ms  
t
1
ID 
20ms  0


17  29.95e 5ms
 dt

= 0.83 A

vi. When a switch or diode of a parallel pair conduct, the complementary pair of devices experience a
voltage Vs, 340V dc. Thus although the load experiences half the supply voltage, the semiconductors
experience twice that voltage, the same voltage experienced by the switches in the full bridge inverter.
vii. The load power (whence various currents) is found by averaging the instantaneous load power

1
170V  17 - 29.95  e -200t  dt ir ms  PL I s  PL
10 ms
PL 
10ms  0 R Vs
= 638.5 W  638.5W  8A  638.5W  1.88A
10Ω 340V
♣

17.1.1iii - PWM-wave output

The output voltage and frequency of a single-phase voltage-source inverter bridge can be control using
one of two forms of pulse-width modulation, termed:
 bipolar
 multi-level, usually (meaninglessly) called unipolar
Both pwm techniques have been analysed extensively for dc voltage outputs when applied to the two
quadrant and four quadrant dc choppers considered in Chapter 16, sections 16.5 and 16.6. It will be
seen that the same triangular modulation principles can be applied and extended, when producing low-
harmonic single-phase ac output voltages and currents. The main voltage output difference between the
two methods is the harmonic content near the carrier frequency and its harmonics. Three-phase pwm is
a naturally extension to the single-phase case, except single-phase pwm offers more degrees of
flexibility than its application to three phase inverters, although three-phase pwm does have the attribute
of triplen harmonic cancellation, due to the use of one (co-phasal) triangular carrier.

Bipolar pulse width modulation

Bipolar modulation is the simplest pwm method and involves comparing a fixed frequency and
magnitude triangular carrier with the ac waveform desired, called the modulation waveform. The
modulation waveform is usually a sinusoid of magnitude (modulation index) M such that 0 ≤ M ≤ 1.
The waveforms in figure 17.4 shown that the load voltage VL swings between the two voltage levels, +Vs
and -Vs, (hence the term bipolar output voltage), according to
 T1 and T2 are on when vref > vΔ (T3 and T4 are off ) such that VL = +Vs
 T3 and T4 are on when vref < vΔ (T1 and T2 are off ) such that VL = -Vs

Multi-level pulse width modulation

Two multilevel output voltage techniques can be use with single-phase voltage fed ac bridges. In both
case, two triangular carries displaced by 180° give the same output for the same switching frequency.

i. The waveforms in figure 17.5 show that the load voltage VL swings between the two voltage levels,
+Vs and -Vs, with interspaced zero periods (hence the term multilevel, specifically three-level in this
case, 0V and ±Vs ), according to
 T1 is on when vref > vΔ such that Vao = +Vs
 T4 is on when vref < vΔ such that Vao = 0V

 T3 is on when vref < -vΔ such that Vbo = Vs

 T2 is on when vref > -vΔ such that Vbo = 0V

The multilevel load output voltage is the difference between the two leg voltage waveforms and can be
defines as follows:
723 Power Electronics

 T1 and T2 are on such that Vao = +Vs, Vbo = 0V, Vab = +Vs
 T2 and T3 are on such that Vao = 0V, Vbo = +Vs, Vab = -Vs

 T1 and T3 are on such that Vao = +Vs, Vbo = +Vs, Vab = 0V

 T2 and T4 are on such that Vao = 0V, Vbo = 0V, Vab = 0V

+1 M

-1

VΔ Vref
(a)

Vs
T1 T1 T1 T1 T1
T2 T2 T2 T2 T2
ON ON ON ON ON
VL

T3 T3 T3 T3 T3
T4 T4 T4 T4 T4
ON ON ON ON ON
(b)
-Vs

Figure 17.4. Bipolar pulse width modulation:

(a) carrier and modulation waveforms and (b) resultant load pwm waveform.

+1
M

-1

(a)
VΔ -VΔ Vref

Vs T1 on (T4 off)
Vao

T4 on (T1 off)

Vs T3 on (T2 off)

Vbo
T2 on (T3 off)
(b)
Vs

Vab Vab=Vao-Vbo
VL

-Vs

Figure 17.5. Multilevel (3 level) pulse width modulation:

(a) carriers and modulation waveforms and (b) resultant load pwm waveforms.
Chapter 17 DC to AC Inverters – Switched Mode 724

The two zero output states are interleaved to balance switching losses between all four bridge switches.
Device switching is at the carrier frequency, but the bridge load voltage (hence load current)
experiences twice the leg switching frequency since the two carriers are displaced by 180°.

ii. A second multilevel output voltage approach is shown in figure 17.17, where the triangular carriers
are not only displaced by 180° in time, but are vertically displaced, as for multilevel inverter pwm
generation, which is considered in section 17.4 (half the magnitude and twice the frequency as in
figure 17.6). The upper triangle modulates reference values greater than zero, while the lower
triangle modulates when the reference is less than zero.

Spectral comparison between bipolar and multilevel pwm waveforms

The key features of the H-bridge inverter output voltage with bipolar pwm are (fig 17.6a):
 a triangular carrier has only odd Fourier components, so the output spectrum only has carrier
components at odd harmonics of the carrier frequency
 the first carrier components occur at the carrier frequency, fc
 side-band components occur spaced by 2fo from other components, around all multiples of the
carrier frequency fc

From figure 17.6b, the key features of the H-bridge inverter output voltage with multilevel pwm are:
 the output switching frequency is double 2fc each leg switching frequency fc, since the switching
of each leg is time shifted (by 180°), hence the first carrier related components in the output
occur at 2fc and then at multiples of 2fc (effectively the carrier is 2fo)
 no triangular carrier Fourier components exist in the output voltage since the two carriers are in
anti-phase (180° apart), effectively cancelling one another in spectrum terms
 side-band components occur spaced by 2fo from other components, around each multiple of the
carrier frequency 2fc

fc
M- fc- 2fo fc+ 2fo
fc- 4fo fc+ 4fo with single-phase bipolar pwm
nfc = 0 for n even

2fc- fo 2fc+ fo
2 fo
2fc-3fo 2fc+3fo

fo 1×fc 2×fc 3×fc 4×fc

(a)
M-
with single-phase multilevel pwm
nfc = 0 for all n
(suppressed carrier)
2fc- fo 2fc+ fo
2fc-3fo 2fc+3fo 2 fo

fo 1×fc 2×fc 3×fc 4×fc

(b)

Figure 17.6. Typical phase output frequency spectrum, at a give switch commutation frequency, for:
(a) bipolar pwm and (b) multilevel pwm.

17.1.2 Three-phase voltage-source inverter bridge

The basic dc to three-phase voltage-source inverter (VSI) bridge is shown in figure 17.7. It comprises
six power switches together with six associated reactive energy feedback diodes. Each of the three
inverter legs operates at a relative time displacement (phase) of ⅔π, 120°.
725 Power Electronics

Table 17.1: Quasi-square-wave six conduction states - 180° conduction

Interval Three conducting switches leg state voltage vector

1 T1 T2 T3 101 v5
2 T2 T3 T4 001 v1
3 T3 T4 T5 011 v3
4 T4 T5 T6 010 v2
5 T5 T6 T1 110 v6
6 T6 T1 T2 100 v4

17.1.2i - 180° (π) conduction

Figure 17.8 shows inverter bridge quasi-square output voltage waveforms for a 180° switch conduction
pattern. Each switch conducts for 180°, such that no two series connected (leg or arm) semiconductor
switches across the voltage rail conduct simultaneously. Six patterns exist for one output cycle and the
rate of sequencing these patterns, 6fo, specifies the bridge output frequency, fo. The conducting switches
during the six distinct intervals are shown and can be summarised as in Table 17.1.

Figure 17.7. Three-phase VSI inverter circuit:

(a) GCT thyristor bridge inverter; (b) star-type load; and (c) delta-type load.

The three output voltage waveforms can be derived by analysing a balanced resistive star load and
considering each of the six connection patterns, as shown in figure 17.9, using the matrix in figure 17.8c.
Effectively the resistors representing the three-phase load are sequentially cycled anticlockwise one at a
time, being alternately connected to each supply rail. The output voltage is independent of the load, as it
is for all voltage source inverters.
Alternatively, the generation of the three-phase voltages can be analysed analytically by using the
rotating voltage space vector technique. With this approach, the output voltage state from each of the
three inverter legs (or poles) is encoded as summarised in table 17.1, where a ‘1’ signifies the upper
switch in the leg is on, while a ‘0’ means the lower switch is on in that leg. The resultant binary number
(one bit for each of the three inverter legs), represents the output voltage vector number (when
converted to decimal). The six voltage vectors are shown in figure 17.10 forming sextant boundaries,
where the quasi-square output waveform in figure 17.8b is generated by stepping instantaneously from
one vector position to another in an anticlockwise direction. Note that the rotational stepping sequence
is arranged such that when rotating in either direction, only one leg changes state, that is, one device
turns off and then the complementary switch of that leg turns on, at each step. This minimises the
inverter switching losses. The dwell time of the created rotating vector at each of the six vector
positions, is ⅓π (T) of the cycle period (T). Note that the line-to-line zero voltage states 000 and 111
are not used. These represent the condition when either all the upper switches (T1, T3, T5) are on or all
the lower switches (T2, T4, T5) are switched on (represented as the origin in figure 17.10). Phase
reversal can be obtained by interchanging two phase outputs, or as is the preferred method, the
direction of the rotating vector sequence is reversed. Reversing is therefore effectively achieved by
back-tracking along each output waveform.
Chapter 17 DC to AC Inverters – Switched Mode 726

With reference to figure 17.8b, the line-to-load neutral voltage Fourier coefficients are given by
n  2n 
2  cos cos
2 3 3
V nL N  V s (17.45)
3 n

The line-to-load neutral voltage is therefore

2 
sin n t
VnL N  V s  r  1, 2, 3, .. (17.46)
 n  1, 6r 1
n
that is
2
v RN  Vs sint  15 sin5t  17 sin7t  11
1
sin11t  . . . (V) (17.47)

similarly for vYN and vBN, where ωt is substituted by ωt+⅔π and ωt-⅔π respectively.

T1 T5 T3

T4 T2 T6
0V

VRo

VBo

VYo

110 100 101 001 011 010

VRB

VBY

VYR
v RB  v RN  v BN 
   
v BY   v BN  v YN 
   
v YR  v YN  v RN 
VRN
1 -1 0  v RN 
(iR)   
0 1 -1 v BN 

 -1 1  
VBN  0  v YN 

(iB)
(c)

VYN
v RN   1 0  1 v RB 
v   1  1 1 0  v 
(iY)
 BN  3    BY 
v YN   0  1 1  v YR 
v6 v4 v5 v1 v3 v2
(b)

Figure 17.8. A three-phase bridge inverter employing 180° switch conduction with a resistive load:
(a) the bridge circuit showing T1, T5, and T6 conducting (leg state v6 :– 110); (b) circuit voltage and
current waveforms with each of six sequential output voltage vectors identified; and
(c) phase voltage to line voltage conversion matrices and vice versa.

The line-to-line voltage, from equation (17.38) with α = ⅓π, gives Fourier coefficients defined by
 n 
cos
4  6 
V  V (17.48)
nL  L
 s
n
727 Power Electronics

The line-to-line voltage is thus

2 3 n  sin n t

VnL L  Vs  cos r  1, 2, 3, .
.

(17.49)
 n 1,6r 1 6 n
(the symbol provides the sign), that is
2 3
v RB  V s sin t - 15 sin5t - 17 sin7t  1
sin11t + . . . (V) (17.50)
 11

and similarly for vBY and vYR. Figure 17.8b shows that vRB is shifted π with respect to vRN, hence to
obtain the three line voltages while maintaining a vRN reference, ωt should be substituted with ωt + π,
ωt- ½π and ωt+π, respectively. The three line-to-line fundamental voltages are:
2 3
V AB ,1  V s sin t  1 6  

2 3
V BC ,1  V s sin t  ½ 

2 3
VCA ,1  V s sin t  5 6  

Since the interphase voltages consist of two square waves displaced by ⅔π, no triplen harmonics (3, 6,
9, . . .) exist. The outputs comprise harmonics given by the series n = 6r ± 1 where r ≥ 0 and is an
integer. The nth harmonic has a magnitude of 1/n relative to the fundamental.
T1 / T4

T5 / T2 T3 / T6

Y R
T1
T5 T1
VRN = Vs /3 VRN = 2Vs /3
VBN = -2Vs /3 VBN = -Vs /3
VYN = Vs /3 VYN = -Vs /3

T2 T6
T6
B Y B

B
R B
T3
T1 T3
VRN = Vs /3 VRN = -Vs /3
VBN = Vs /3 VBN = 2Vs /3
VYN = -2Vs /3 VYN = -Vs /3

T4 T2
T2
Y R Y

B Y
Y
T5
T3 T5
VRN = -2Vs/3 VRN = -Vs /3
VBN = Vs/3 VBN = -Vs /3
VYN = Vs/3 VYN = 2Vs /3

T6 T4
T4 B R

3 3 2π

Figure 17.9. Determination of the line-to-neutral voltage waveforms for a balanced resistive load
and 180° conduction as illustrated in figure 17.8.
Chapter 17 DC to AC Inverters – Switched Mode 728

By examination of the interphase output voltages in figure 17.8 it can be established that the mean half-
cycle voltage is ⅔Vs and the rms value is √⅔ Vs, namely 0.816 Vs. From equation (17.50) the rms value
of the fundamental is √6 Vs /π, namely 0.78 Vs, that is 3/π times the total rms voltage value.
The three-phase inverter output voltage properties are summarised in Table 17.2.

17.1.2ii - 120° (⅔π) conduction

The basic three-phase inverter bridge in figure 17.7 can be controlled with each switch conducting for
120°. As a result, at any instant only two switches (one upper and one non-complementary lower)
conduct and the resultant quasi-square output voltage waveforms are shown in figure 17.12. A 60°
(⅓π), dead time exists between two series switches conducting, thereby providing a safety margin
against simultaneous conduction of the two series devices (for example T 1 and T4) across the dc supply
rail. This safety margin is obtained at the expense of a lower semi-conductor device utilisation and rms
output voltage than with 180° device conduction. The device conduction pattern is summarised in Table
17.3. A feature with ⅔π conduction is that the phase currents can be measured from the dc link current.
Interval # 4 Interval # 3
T4 T5 T6 on T3 T4 T5 on
leg state 010 leg state 011
v2 = Vs e π j v3 = Vs e π j

000
Interval # 5 111 Interval # 2
T1 T5 T6 on T2 T3 T4 on
leg state 110 leg state 001
v6 = Vs e π j v1 = Vs e 0 j

Interval # 6 Interval # 1
T1 T2 T6 on T1 T2 T3 on
leg state 100 leg state 101
v4 = Vs e π j v5 = Vs e -π j

001 011 010

v1 v3 v2

110 100 101

v6 v4 v5
Figure 17.10. Generation and arrangement of the six quasi-square inverter output voltage states.

Figure 17.8b for 180° conduction and 17.12b for 120° conduction show that the line to neutral voltage of
one conduction pattern is proportional to the line-to-line voltage of the other. That is, from equation
(17.38) with α = ⅓π

2 n
v RN  2 3    ½v RY     V s cos sin n t
n 1,3,5  n 6
(17.51)
3
 V s sin t - 15 sin5t - 17 sin 7t  11 1
sin11t + . . . (V)

and

2 3 n
v RY  2
3    3 2v RN     V s cos sin n t
n 1,3,5 n 6
(17.52)
3
 V s sin t  sin5t  sin 7t 
1 1 1
sin11t + . . . (V)
 5 7 11

Also vRY = √3 vRN and the phase relationship between these line and phase voltages, of π, has not
been retained. That is, with respect to figure 17.12b, substitute ωt with ωt + π in equation (17.51) and
ωt + ⅓π in equation (17.52). 180° conduction gives a 15% increase in ac voltage magnitude compared
to 120° conduction, but both techniques give the same harmonic spectrum components.
729 Power Electronics

The output voltage properties for both 120° and 180° conduction are summarised in the Table 17.2.
Independent of the conduction angle (120°, 180° or even 150°), quasi-square 180° conduction occurs
with inductive loads, producing the six hexagon states shown in the upper part of figure 17.10. The
resistive load assumptions made in this section for explanation purposes can be misleading.

Table 17.2: Quasi-squarewave voltage properties for a resistive load

Conduction Fundamental voltage Characteristic

period peak rms Total rms Distortion Factor THD
V1 V1 Vrms μ thd
180° (V) (V) (V)

2 2 2 3 2
Phase Vs
Voltage   Vs 3 s
V
 9
1
V L- N  0.637V s  0.450 V s  0.471V s  0.955  0.311
Line 2 3 6 2 3 2
Vs V
Voltage   Vs 3 s  9
1
V L- L  1.10 V s  0.78 V s  0.816V s  0.955  0.311
120° (V) (V) (V)

3 6 1 3 2
Phase
Vs Vs
Voltage  2 Vs 6  9
1
V L- N  0.551V s  0.390 V s  0.408V s  0.955  0.311
3 3 1 3 2
Line Vs V Vs 1
Voltage  2 s 2  9
V L- L  0.955V s  0.673 V s  0.707V s  0.955  0.311

Table 17.3: Quasi-squarewave conduction states - 120° conduction

Interval Two conducting devices

1 T1 T2
2 T2 T3
3 T3 T4
4 T4 T5
5 T5 T6
6 T6 T1

An ideal switch model of the three-phase voltage source inverter, with 180° conduction, connected to
passive load, where (T1, T4), (T5, T2) and (T3 and T6) represent complementary switch pairs, can be
describe by: T1+T4 =1; T5+T2 =1 and T3+T6 =1. The upper and lower switches in the same arm operate
in a complementary manner, that is, turning on T 1 corresponds to T1=1 and T4=0, and similarly phases Y
and B. Then the inverter terminal voltages at R, Y and B relative to supply mid-point ‘o’ can be
synthesized from dc link voltage as:
v Ro  ½ (T1 -T4 )V s
v Yo  ½ (T5 -T2 )V s
v Bo  ½ (T3 -T6 )V s
With T1 on and T4 off, the converter output phase R is connected to ½Vs, while T1 off and T4 on
connects output phase R to -½Vs.
The equations describing the ac side transients for a three-phase load RR, RY, RB, and LR, LY, LB are:
v Rn   RR 
   0 0
L L
i R   R   R  i 
d   v Yn    RY  R
i   
  0 0  iY 
dt  Y   LY   LY  i 
i B 
v   R  B
 Bn   0 0 B

 LB   LB 
where vRn, vYn and vBn are phase voltages relative to the load floating neutral-point ‘n’, where iR+iY+iB=0.
Chapter 17 DC to AC Inverters – Switched Mode 730

Modulation
Techniques

Six Pulse Mode PWM Stepping

180° conduction 120° conduction

Harmonic
Elimination

Const/Variable Const/Variable
Constant Sigma Delta
DC link DC link
Pulse Width

Carrier SHE
Signal

1. Hysteresis control
Modulating
Modulating Feedback 2. Linear current control
Signal Control 3. Digital deadbeat
4. Advanced techniques

Pure Sinusoidal TH Injection Dead band Space Vector

(SPWM) (THI) (DBPWM) (SVM)

Figure 17.11. Derivation tree for three-phase bridge inverter output frequency and magnitude
control techniques.

17.1.3 Inverter ac output voltage and frequency control techniques

It is a common requirement that the output voltage and/or frequency of an inverter be varied in order to
control the load power or, in the case of an induction motor, to control the shaft speed and torque by
maintaining a constant V / f ratio. The six VSI modulation control techniques to be considered are:
 Variable voltage dc link
 Single-pulse width modulation
 Multi-pulse width modulation
 Multi-pulse, selected notching modulation
 Sinusoidal pulse width modulation
 Triplen injection
 Triplens injected into the modulation waveform
 Voltage space vector modulation
 Selected harmonic elimination, SHE

Inverter voltage and frequency control techniques are summarised in figure 17.11.

17.1.3i - Variable voltage dc link

The rms voltage of a square-wave can be changed and controlled by varying the dc link source voltage.
A variable dc link voltage can be achieved with a dc chopper as considered in chapter 16 or an ac
phase-controlled thyristor bridge as considered in sections 14.2 and 14.4. A dc link L-C smoothing filter
may be necessary.

17.1.3ii - Single-pulse width modulation

Simple pulse-width control can be employed as considered in section 17.1.1b, where a single-phase
bridge is used to produce a quasi-square-wave output voltage as shown in figure 17.1c.
An alternative method of producing a quasi-square wave of controllable pulse width is to transformer-
add the square-wave outputs from two push-pull bridge inverters as shown in figure 17.13a. By phase-
shifting the output by α, a quasi-square sum results as shown in figure 17.13b.
731 Power Electronics

The output voltage can be described by


Vo  v
n odd
an sin n t (V) (17.53)

where
v an  2  Vs cos n  d   4 V s cos(½n  )
½
(V) (17.54)
½  n

v RB  v RN  v BN 
   
v BY   v BN  v YN 
   
v YR  v YN  v RN 
1 -1 0  v RN 
  
0 1 -1 v BN 

 -1 1  
 0  v YN 

(c)

Figure 17.12. A three-phase bridge inverter employing 120° switch conduction with a resistive star
load: (a) the bridge circuit showing T1 and T2 conducting; (b) circuit voltage and current waveforms;
and (c) phase voltage to line voltage conversion matrix.

The rms output voltage is

Vr  Vs 1 -  (V) (17.55)

Chapter 17 DC to AC Inverters – Switched Mode 732

and the rms value of the fundamental is

2 2
V1  V s cos ½ (V) (17.56)

As α increases, the magnitude of the harmonics, particularly the third, becomes significant compared
with the fundamental magnitude. This type of control may be used in high power applications.

Figure 17.13. Voltage control by combining phase-shifted push-pull inverters:

(a) two inverters with two transformers for summing and (b) circuit voltage waveforms for a phase
displacement of α.

Example 17.5: Single-pulse width modulation

Two single-phase H-bridge inverter outputs are transformer added, as shown in figure 17.13. Each
inverter operates at 50Hz but phase shifted so as to produce 240V rms fundamental output when the rail
voltage of each inverter is 340V dc and the transformers turns ratios are 2:2:1.

Determine
i. the phase shift between the two single phase inverters
ii. the rms output voltage
iii. the frequency and magnitude of the first 4 harmonics of 50Hz and their rms ac
contribution to the rms output
iv. rms voltage of higher order harmonics (higher frequencies than those in part iii.)
v. the total harmonic distortion of the output voltage.

Solution

i. The output is a quasi-square waveform of magnitude ±340V dc. The magnitude of the
50Hz fundamental is given by equation (17.54), for n =1:
v a 1  4 V s cos(½ )

4
2 240V   340V  cos(½ )

from which the phase shift is 76.7°, 1.34 radians.
733 Power Electronics

ii. The rms output voltage is given by equation (17.55), that is

Vrms  Vs 1 -   340V 1 - 1.34  257.5V
 

iii. The peak values of the first four harmonics are given in the table below.

v an  4 Vs cos(½n  )
harmonic
v an2
n n
3 -61.4 3765.0
5 -84.7 7175.3
7 -1.4 1.9
9 46.6 2168.5
.
v 2
an  114.50

The rms value of the ac of the first four harmonics is 114.5/√2 = 81.0V.

iv. The ac component of the harmonics above the 9th is given by

Vr ms n 9  Vr ms
2
Vr ms
2
n 9

 257.5V 2   240V 2  81.0V 2   46.3V

v. The total harmonic voltage distortion is given by

2
Vr ms2 V a21 Vrms 
THDv   100     1  100
Va 1  Va 1 
2
 257.5V 
  240V   1  100  38.9%
 
♣

+Vs
c fo

δ1
Magnitude (pu)

-Vs

δ1 < δ 2
Carrier frequency fc

+Vs
fo

Harmonic order (n)

δ2
(c)
-Vs

Figure 17.14. Inverter control giving variable duty cycle of five notches per half cycle:
(a) low duty cycle, δ1, hence low fundamental magnitude,
(b) higher duty cycle, δ2, for a high fundamental voltage output, and (c) voltage output spectrum.

17.1.3iii - Multi-pulse width modulation

An extension of the single-pulse modulation technique is multiple-notching as shown in figure 17.14. The
bridge switches are controlled so as to vary the on to off time of each notch, δ, thereby varying the
output rms voltage which is given by Vr ms   V s . Alternatively, the number of notches can be varied.
Chapter 17 DC to AC Inverters – Switched Mode 734

The harmonic content at lower output voltages is significantly lower than that obtained with single-pulse
modulation. The increased switching frequency does increase the magnitude of higher order harmonics
and the switching losses. The Fourier coefficients of the output voltage in figure 17.14 are given by
fc
4  fo
fo fo 
Vn  cos 2 n  2 j  1     cos 2 n  2 j  1   
 (17.57)
n  j 1,2,3,..  fc fc 
where fo is the fundamental frequency, fc the triangular carrier frequency and 0 ≤ δ ≤ 1 is the duty cycle.

17.1.3iv - Multi-pulse, selected notching modulation – selected harmonic elimination

If a multi-level waveform (±Vs, 0) is used with quarter wave symmetry, as shown in figure 17.15a, then
both the harmonics and total rms output voltage can be controlled. With one pulse per quarter wave, the
kth harmonic is eliminated from the output voltage if the centre of the pulse is located such that
sin k   0
(17.58)
that is   
k
Independent of the pulse width δ, the kth harmonic is eliminated and the other Fourier components are
given by
8 
Vn  V s sin n sin n  (17.59)
n k

The output voltage total rms is solely dependent on the pulse width δ and is given by
2
Vo rms  V s  (17.60)

On the other hand, the bipolar waveform (±Vs) in figure 17.15b has an rms value of Vs, independent of
the harmonics eliminated.

vL
δ
Vs

½π π 2π

ωt
λ λ
(a)
-Vs

δ
(b)

λ
Figure 17.15. Output voltage harmonic reduction for a single-phase bridge using selected notching:
(a) multilevel output voltage and (b) bipolar output voltage.

Selected elimination of lower-order harmonics can be achieved by producing an output voltage

waveform as shown in figure 17.15b. The exact switching points are calculated off-line so as to eliminate
the required harmonics. For n switchings per half cycle, n selected harmonics can be eliminated.
735 Power Electronics

In figure 17.15b two notches per half cycle are introduced; hence any two selected harmonics can be
eliminated. The more notches, the lower is the output fundamental. For example, with two notches, the
third and fifth harmonics are eliminated. From
½
bn  4  f   sin n d  for n  1, 2, 3, .... (17.61)
0

b3  4 V s 1  2 cos 3  2 cos 3   0
3
and

b5  4 V s 1  2 cos 5  2 cos 5    0
5
Solving yields α1 = 23.6° and β1 = 33.3°. The total rms output voltage is Vs, independent of the
harmonics eliminated. The magnitude (whence rms) of each harmonic component is
4
Vn  V 1  4  sin n   sin n   (17.62)
n s
The maximum fundamental rms component of the output voltage waveform is 0.84 of a square wave,
which is (2√2/π)Vs when δ = ½π which produces a square wave.
Ten switching intervals exist compared with two per cycle for a square-wave, hence switching losses
and control circuit complexity are increased.
In the case of a three-phase inverter bridge, the third harmonic does not exist, hence the fifth and
seventh (b5 and b7) can be eliminated with α1 = 16.3° and β1 = 22.1. The 5th, 7th, 11th, and 13th can be
eliminated with the angles 10.55°, 16.09°, 30.91°, and 32.87° respectively. Because the waveforms
have quarter wave symmetry, only angles for 90° need be stored.
The output rms voltage magnitude can be varied by controlling the dc link voltage or by transformer-
adding two phase-displaced bridge outputs as demonstrated in figure 17.13. The output voltage Fourier
components in equation (17.62) are modified by equation(17.54) given
4
Vn  V 1  4  sin n   sin n   cos ½n  (17.63)
n s
And the total rms output voltage is reduced from Vs , as given by equation (17.55), that is
Vo rms  Vs 1 -  (V) (17.64)

Thus the fundamental rms magnitude can be changed by introducing an extra constraint to be satisfied,
along with the harmonic eliminating constraints (as a result of the extra constraint, one fewer harmonic
can now be eliminated for a given number of switchings per quarter cycle).
The multi-pulse selected notching modulation technique can be extended to the optimal pulse-width
modulation method, where harmonics may not be eliminated, but minimised according to a specific
criterion. In this method, the quarter wave output is considered to have a number of switching angles.
These angles are selected so as, for example, to eliminate certain harmonics, minimise the rms of the
ripple current, or any other desired performance index. The resultant non-linear equations are solved
using numerical methods off-line. The computed angles are then stored in a ROM look-up table for use.
A set of angles must be computed and stored for each desired level of the voltage fundamental and
output frequency.
The optimal pwm approach is particularly useful for high-power, high-voltage GCT thyristor inverters,
which tend to be limited in switching frequency by device switching losses.

Generally sinωt+ksin3ωt is generated (since the third harmonic of the square wave is not eliminated)
½ ½
4 4
bn   f   sin n  d    1  sin n  d 
 0
 0

For a fundamental magnitude of √3m of the pu link voltage and to eliminate N-1 (N-1>2) harmonics:

 
N
-  1  cos k  ¼ 2   1 
k N 1
m
k 1
N
(17.65)
-  1  cos n k  ½ for n = 5, 7, ..., 3N - 3 2  ½  1 
k N 1

k 1

where  
1  2  ...  N  ½ 1  1 6 1   1
N 1

For N-1 even, all k angles are less than ½π other wise ⅓π (when N-1 is odd).
 Chapter 17 DC to AC Inverters – Switched Mode 736

90 90

80 80

70 70

60 60

Angle (◦)
Angle (◦)

50 50

40 40

30 30

20 20

10 10

0 0
0 0.2 0.4 0.6 0.8 1 1.2 4/π 0 0.2 0.4 0.6 0.8 1 1.2 4/π
Modulation Index Modulation Index

1.4 1.4

1.2 1.2 3rd Fundamental

0.5

½ dc link voltage
1 Fundamental 1

0.8 0.8
3rd 11th
th
9th 9
0.6 0.6
11th
0
0.4 0.4
13th
pu

13th
0.2 0.2
7th 5th 5th 7th
0
0 0.2 0.4 0.6 0.8 1 1.2 4/π
-0.5 0
0 0.2 0.4 0.6 0.8 1 1.2 4/π
0 2 4 6 8 10 12 14 16 18 20
Modulation Index Modulation Index

0.5 0.2
pu of dc link Voltage

0.1

0 0

-0.1

-0.5 -0.2
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
M=1
Time (ms) Time (ms)

THD
0.2
20 0.5

18
0.45
pu of dc link Voltage

16
0.1 Total Harmonic distortion 0.4
14

12
0-60° and 0-90° including triplens 0.35

100
0-60° excluding triplens 0-90°
0.3
8 0-60°
0-90° excluding triplens
-0.16 0.25

4 Common mode voltage, rms

0.2
2
-0.20
00 2 0.2 4 60.4 8 10
0.6 120.8 14 16
1 18 1.24/π
20 0 0.2 0.4 0.6 0.8 1 1.2
4/π
Modulation Index Modulation Index
(a) (b)

Figure 17.16. SHE commutation angles, normalised as a function of the fundamental eliminating:
the 5th and 7th harmonics with commutation angles (a) 0 to 90° and (b) 0 to 60°.
737 Power Electronics

To eliminate the 5th and 7th harmonics (an even number of harmonics), with a fundamental magnitude
with modulation index m, three angles are required, N=3 and the three equations to be solved are
cos 1  cos  2  cos  3  ¼  2  m  
cos 51  cos 5 2  cos 5 3  ½
cos 71  cos 7 2  cos 7 3  ½

The resultant angles are shown in figure 17.16. The maximum modulation index, with respect to a
square wave is 1.166 and 1.188 for angles less that 60 degrees and greater, respectively. Any solution
with all angles less than 60° represents dead banding of the three phases, where each phase is
alternately clamped to the dc link zero and positive rails (see section 17.1.3vi). The total harmonic
distortion is virtually the same in both cases, as is the maximum common mode voltage dv/dt, while the
rms common mode voltage is greater for the case when the angles can exceed 60 degrees.

To eliminate the 5th, 7th, and 11th harmonics (an odd number of harmonics), with a fundamental
magnitude with modulation index m, four angles are required, N=4 and the four equations to be solved
are
cos 1  cos 2  cos 3  cos  4  ¼ 2  m  
cos 51  cos 52  cos 53  cos 5 4  ½
cos 71  cos 72  cos 73  cos 7 4  ½
cos111  cos112  cos113  cos11 4  ½

As further harmonics are eliminated, multiple solutions arise, with at least one solution giving a
maximum magnitude tending to 1.155 (π/3) in magnitude, compared to 1.27 (4/ π) for a square wave.

17.1.3v - Sinusoidal pulse-width modulation (pwm), SPWM

1 - Natural sampling

(a) Synchronous carrier

The output voltage waveform and method of generation for synchronous carrier, natural sampling
sinusoidal pwm, suitable for the single-phase bridge of figure 17.1, are illustrated in figure 17.17. The
switching points are determined by the intersection of the triangular carrier wave fc and the reference
modulation sine wave, fo. The output frequency is at the sine-wave frequency fo and the output voltage is
proportional to the magnitude of the sine wave. The amplitude M (0 ≤ M ≤ 1) is called the modulation
index. For example, figure 17.17a shows maximum voltage output (M = 1), while in figure 17.17b where
the sine-wave magnitude is halved (M = 0.5), the output voltage is halved.
If the frequency of the modulation sinewave, fo, is an integer multiple of the triangular wave carrier-
frequency, fc that is, fc = nfo where n is integer, then the modulation is synchronous, as shown in figure
17.17. If n is odd then the positive and negative output half cycles are symmetrical and the output
voltage contains no even harmonics. In a three-phase system if n is a multiple of 3 (and odd), the carrier
is a triplen of the modulating frequency and the spectrum does not contain the carrier or its harmonics.
fc  (6q  3) fo  nf o (17.66)
for q = 1, 2, 3.
The Fourier harmonic magnitudes of the line to line voltages are given by
 n   n 
a n  V cos   cos  
 2   3 
(17.67)
 n   n 
bn  V sin   sin  
 2   3 
where Vℓ is proportional to the dc supply voltage Vs and the modulation index M.
Sinusoidal pwm requires a carrier of much higher frequency than the modulation frequency. The
generated rectilinear output voltage pulses are modulated such that their duration is proportional to the
instantaneous value of the sinusoidal waveform at the centre of the pulse; that is, the pulse area is
proportional to the corresponding value of the modulating sine wave.

If the carrier frequency is very high, an averaging effect occurs, resulting in a sinusoidal fundamental
output with high-frequency harmonics, but minimal low-frequency harmonics.
Rather than using two offset triangular carriers, as shown in figure 17.17, a triangular carrier without an
offset can be used. Now the output only approximates the ideal. Figure 17.18 shows this pwm
generation technique and voltage bipolar output waveform, when applied to the three-phase VSI
inverter in figure 17.7. Two offset carriers are not applicable to six-switch, three-phase pwm generation
since complementary switch action is required. That is, one switch in the inverter leg must always be on.
Chapter 17 DC to AC Inverters – Switched Mode 738

upper triangular carrier wave

fc

lower triangular carrier wave

fc

reference modulation sinewave fo

Figure 17.17. Derivation of trigger signals for multi-level naturally sampled pulse-width modulation
waveforms: (a) for a high fundamental output voltage (M = 1) and
(b) for a lower output voltage (M = 0.5), with conducting devices shown.

It will be noticed that, unlike the output in figure 17.17, no zero voltage output periods exist. This has the
effect that, in the case of GCT thyristor bridges, a large number of commutation cycles is required. When
zero output periods exist, as in figure 17.12, one GCT thyristor is commutated and the complementary
device in that leg is not turned on. The previously commutated device can be turned back on without the
need to commutate the complementary device, as would be required with the pwm technique illustrated
in figure 17.18. Commutation losses are reduced, control circuitry simplified and the likelihood of
simultaneous conduction of two series leg devices is reduced.

The alternating zero voltage loop concept can be used, where in figure 17.18b, rather than T1 being on
continuously during the first half of the output cycle, T 2 is turned off leaving T1 on, then when either T1 or
T2 must be turned off, T1 is turned off leaving T2 on.
739 Power Electronics

Figure 17.18. Naturally sampled pulse-width modulation waveforms suitable for a three-phase
bridge inverter: (a) reference signals; (b) conducting devices and fundamental sine waves; and (c)
one output line-to-line voltage waveform.

(b) Asynchronous carrier

When the carrier is not an integer multiple of the modulation waveform, asynchronous modulation
results. Because the output frequency, fo, is usually variable over a wide range, it is difficult to ensure fc
= nfo. To achieve synchronism, the carrier frequency must vary with frequency fo. Simpler generating
systems result if a fixed carrier frequency is used, resulting in asynchronism between fo and fc at most
output frequencies. Left over, incomplete carrier cycles create slowly varying output voltages, called
subharmonics, which may be troublesome with low carrier frequencies, as found in high-power drives.
Natural sampling, asynchronous sinusoidal pwm is usually restricted to analogue or ASIC
implementation. The harmonic consequences of asynchronous-carrier natural-sampling are similar to
asynchronous-carrier regular-sampling in 2 to follow.

2 - Regular sampling

(a) Asynchronous carrier

When a fixed carrier frequency is used, usually no attempt is made to synchronise the modulation
frequency. The output waveforms do not have quarter-wave symmetry which produces subharmonics.
These subharmonics are insignificant if fc >> fo, usually, fc > 20 fo.
The implementation of sinusoidal pwm with microprocessors or digital signal processors is common
because of flexibility and the elimination of analogue circuitry associated problems. The digital pwm
generation process involves scaling, by multiplication, of the per unit sine-wave samples stored in ROM.
Chapter 17 DC to AC Inverters – Switched Mode 740

Figure 17.19. Regular sampling, asynchronous, sinusoidal pulse-width-modulation:

(a) symmetrical modulation and (b) asymmetrical modulation.

The multiplication process is time-consuming, hence natural sampling is not possible. In order to
minimise the multiplication rate, the sinusoidal sine-wave reference is replaced by a quantised stepped
representation of the sine-wave. Figure 17.19 shows two methods used. Sampling is synchronised to
the carrier frequency and the multiplication process is performed at twice the sampling rate for three-
phase pwm generation (the third phase can be expressed in terms of two phases, since v1 + v2 + v3 = 0).

 Symmetrical modulation

Figure 17.19a illustrates the process of symmetrical modulation, where sampling is at the carrier
frequency. The quantised sine-wave is stepped and held at each sample point. The triangular carrier is
then compared with the step sine-wave sample. The modulation process is termed symmetrical
modulation because the intersection of adjacent sides of the triangular carrier with the stepped sine-
wave, about the non-sampled carrier peak, are equidistant about the carrier peak. The pulse width,
independent of the modulation index M, is symmetrical about the triangular carrier peak not associated
with sampling, as illustrated by the upper pulse in figure 17.20. The pulse width is given by
1
t ps  1 - M sin 2 f ot 1  (17.68)
2f c
where t1 is the time of sampling.
741 Power Electronics

 Asymmetrical modulation

Asymmetrical modulation is produced when the carrier is compared with a stepped sine wave produced
by sampling and holding at twice the carrier frequency, as shown in figure 17.19b. Each side of the
triangular carrier about a sampling point intersects the stepped waveform at different step levels. The
resultant pulse width is asymmetrical about the sampling point, as illustrated by the lower pulse in figure
17.20 for two modulation waveform magnitudes. The pulse width is given by
1
t pa 
2f c
1 - ½M  sin 2 f ot 1  sin 2 f ot 2   (17.69)

where t1 and t2 are the times at sampling such that t2 = t1 + 1/2fc.

Figure 17.20 shows that a change in the modulation index M varies the pulse width on each edge,
termed double edge modulation. A triangular carrier produces double edge modulation, while a sawtooth
carrier produces single edge modulation, independent of the sampling technique.
tp2s
tp1s

M2 M1

t1

Triangular carrier
fc

Reference fo2

Reference fo1
t2

M2 M1 Line of
symmetry

tp1a
tp2a

Figure 17.20. Regular sampling, asynchronous, sinusoidal pulse-width-modulation,

showing double edge: (upper) asymmetrical modulation and (lower) symmetrical modulation.

3 - Frequency spectra of pwm waveforms

The most common form of sinusoidal modulation for three-phase inverters is regular sampling,
asynchronous, fixed frequency carrier, pwm. If fc > 20fo, low frequency subharmonics can be ignored.
The output spectra consists of the modulation frequency fo with magnitude M. Also present are the
spectra components associated with the triangular carrier, fc. For any sampling, these are fc and the odd
harmonics of fc. (The triangular carrier fc contains only odd harmonics). These decrease in magnitude
with increasing frequency. About the frequency nfc are components of fo spaced at ± 2fo, which generally
decrease in magnitude when further away from nfc. That is, at fc the harmonics present are fc, fc ± 2fo, fc
± 4fo, … while about 2fc, the harmonics present are 2fc ± f0, 2fc ± 3fo,..., but 2fc is not present. The typical
output spectrum is shown in figure 17.21. The relative magnitudes of the sidebands vary with modulation
depth and the carrier related frequencies present, fh, are given by

f h  ½ 1   1
n 1
 n f  2k  ½ 1   1  f
c
n
o (17.70)
where k  1, 2, 3,.... (sidebands) and n  1, 2, 3,.... (carrier )
Chapter 17 DC to AC Inverters – Switched Mode 742

M-
with single-phase unipolar pwm
fh = 0 for n odd
(suppressed carrier and n - odd side bands)
2fo
2fo

fo 1 fc 2 fc 3 fc 4 fc

Figure 17.21. Location of carrier harmonics and modulation frequency sidebands,

showing all sideband separated by 2fm.

Fundamental and phase voltage line to line

wrt 0 voltage

phase voltage line voltage

spectrum spectrum

output
upper switch
currents
current

dc link
current

Waveforms for ideal switch model of the voltage source inverter

(modulation index m=0.9, 2kHz switching frequency, 200V dc link voltage)
743 Power Electronics

Although the various pwm techniques produce other less predominate spectra components, the main
difference is seen in the magnitude of the carrier harmonics and sidebands. The magnitudes increase as
the pwm type changes from naturally sampling to regular sampling, then from asymmetrical to sym-
metrical modulation, and finally from double edge to single edge. With a three-phase inverter, the
carrier fc and its harmonics do not appear in the line-to-line voltages since the carrier fc and in particular
its harmonics, are co-phase to the three modulation waveforms.

m=0

m=¼

m=½

m=¾

m=1

ωt

1 2 π 4 5 π
o π π π 2π
3 3 3 3

Figure 17.22. Modulation reference waveform for phase dead banding.

17.1.3vi - Phase dead-banding, DBPWM

Dead banding is when one phase (leg) is in a fixed on state, and the remaining phases are appropriately
modulated so that the phase currents remain sinusoidal. The dead banding occurs for 60° periods of
each cycle with the phase with the largest magnitude voltage being permanently turned on. Sequentially
each switch is clamped to the appropriate link rail. The leg output is in a high state if it is associated with
the largest positive phase voltage magnitude, while the phase output is zero if it is associated with the
largest negative phase magnitude. Thus the phase outputs are cycled, being alternately clamped high
and low for 60° every 180° as shown in figure 17.22. A consequence of dead banding is reduced
switching losses since each leg is not switched at the carrier frequency for 120° (two 60° periods 180°
apart). A consequence of dead banding is increased ripple current. Dead banding is achieved with
discontinuous modulating reference signals. Dead banding for a continuous 120° per phase leg is also
possible but the switching loss savings are not uniformly distributed amongst the six inverter switches.

The magnitude of the fundamental (with respect to the ac mains) when using standard PWM can be
increased by 2/√3 from 3x√3/2π, 0.827pu to 3/π, 0.955pu without introducing output voltage distortion,
by the injection of triplen components, which are co-phasal in a three-phase system, and therefore do
not appear in the line currents. Two approaches can be used to affect this undistorted output voltage
magnitude increase.

 Triplen injection into the modulation waveform or

 Voltage space vector modulation
Chapter 17 DC to AC Inverters – Switched Mode 744

17.1.3vii - Triplen Injection modulation

1 - Triplens injected into the modulation waveform, THI

An inverter reconstitutes three-phase voltages with a maximum magnitude of 0.827 (3√3/2π) of the fixed
three-phase input ac supply, converted to dc before inversion. A motor designed for the fixed mains
supply is therefore under-fluxed at rated frequency and not fully utilised on an inverter. As will be shown,
by using third harmonic voltage injection, the flux level can be increased to 0.955 (3/π) of that produced
on the three-phase ac mains supply.
If over-modulation (M > 1) is not allowed, then the modulation wave M sin ωt is restricted in magnitude
to M = 1, as shown in figure 17.23a.
If VRN = M sinωt ≤ 1pu
and VYN = M sin(ωt + ⅔π) ≤ 1 pu
then VRY = √3 M sin(ωt - π)
where 0 ≤ M ≤ 1

×1.155

Figure 17.23. Modulation reference waveforms: (a) sinusoidal reference, sin ωt; (b) third harmonic
injection reference, sin ωt +  sin 3ωt; and (c) triplen injection reference, sin ωt + (1/√3π){9/8
sin3ωt - 80/81 sin9ωt + . ..} where the near triangular waveform b is half the magnitude of the
shaded area.

In a three-phase pwm generator, the fact that harmonics at 3fo (and odd multiplies of 3fo) vectorally
cancel can be utilised effectively to increase M beyond 1, yet still ensure modulation occurs for every
carrier frequency cycle.
Let VRN = M′ sinωt+ sin3ωt) ≤ 1 pu
and VYN = M′ ( sin(ωt +⅔π) +  sin 3(ωt + ⅔π)) ≤ 1 pu
then VRY = √3 M′ sin(ωt - π)

VRN has a maximum instantaneous value of 1 pu at ωt = ±⅓π, as shown in figure 17.23b. Therefore
3
VRN t  13    M ' 1
2
745 Power Electronics

that is
2
M' M  1.155M (17.71)
3

Thus the fundamental of the phase voltage is M′ sin ωt = 1.155 M sin ωt. That is, if the modulation
reference sin ωt +  sin 3ωt is used, the fundamental output voltage is 15.5 per cent larger than when
sin ωt is used as a reference. The increased fundamental is shown in figure 17.23b.

The spatial voltage vector technique injects the triplens according to


 1  1r 

VRN  M ' sint   sin  2r  1 3t   (17.72)

 3 r 0  2r  1  3   2r  1  3 
1 1


The Fourier triplen series represents half the magnitude of the shaded area in figure 17.23c (the
waveform marked ‘b’), which is formed by the three-phase sinusoidal waveforms. The spatial voltage
vector waveform is defined by
3
sint 0  t  16 
2
(17.73)
3
sin(t  6  )
1 1
6
  t  ½
2

The use of this reference increases the duration of the zero volt loops, thereby decreasing inverter
output current ripple. The maximum modulation index is 2/√3, 1.155. Third harmonic injection, yielding M
= 1.155, is a satisfactory approximation to spatial voltage vector injection.

2 - Voltage space vector pwm, SVM

When generating three-phase quasi-square output voltages, the inverter switches step progressively to
each of the six switch output possibilities (states). In figure 17.10, when producing the quasi-square
output, each of these six states is represented by an output voltage space vector. Each vector has a ⅓π
displacement from its two adjacent states, and each has a length Vs which is the pole output voltage
relative to the inverter 0V rail. Effectively, the quasi-square three-phase output is generated by a
rotating vector of length Vs, jumping successively from one output state to the next in the sequence, and
in so doing creating six voltage output sectors. The speed of rotation, in particular the time for one
rotation, determines the inverter output frequency. The sequence of voltage vectors {v1, v3, v2, v6, v4, v5}
is arranged such that stepping from one state to the next involves only one of the three poles changing
state. Thus the number of inverter devices needing to change states (switch) at each transition, is
minimised. But multiple steps occur if the carrier frequency is not a six times multiple of the fundamental
frequency.
[If the inverter switches are relabelled, upper switches T 1, T2, T3 - right to left; and lower switches T 4, T5,
T6 - right to left: then the rotating voltage sequence becomes {v1, v2, v3, v4, v5, v6}]

Interval # 4 Interval # 3
T4 T5 T6 on T3 T4 T5 on
leg state 010 leg state 011
v2 = Vs e π j v3 = Vs e π j
SECTOR
II
SECTOR
SECTOR
III
I
#
Interval 5 000 Interval # 2
T1 T5 T6 on 111 T2 T3 T4 on
leg state 110 leg state 001
v6 = Vs e π j SECTOR SECTOR v1 = Vs e 0 j
IV VI
SECTOR
V

Interval # 6 Interval # 1
T1 T2 T6 on T1 T2 T3 on
leg state 100 leg state 101
v4 = Vs e π j v5 = Vs e -π j
Chapter 17 DC to AC Inverters – Switched Mode 746

001 011 010

v1 v3 v2

110 100 101

v6 v4 v5

111 000
v7 v0

Figure 17.24. Instantaneous output voltage states for the three legs of an inverter.

Rather than stepping ⅓π radians per step, from one voltage space vector position to the next, thereby
producing a six-step quasi-square fixed magnitude voltage output, the rotating vector is rotated in
smaller steps based on the position being updated at a constant rate (carrier frequency). Furthermore,
the vector length can be varied, modulated, to a magnitude less than Vs.
2 V sin 1   
t a Va o /p 3 
  3
Tc v1 Vs
(17.74)
2
Vo / p sin 
t b Vb 3
  where v 1  v 3
Tc v 3 Vs

To incorporate a variable length rotating vector length (modulation depth), it is necessary to vary the
average voltage in each carrier period. Hence pulse width modulation is used in the period between
each finite step of the rotating vector. Pulse width modulation requires the introduction of zero voltage
output states, namely all the top switches on (state 111, v7) or all the lower switches on (state 000, v0).
These two extra states are shown in figure 17.24, at the centre of the hexagon. Now the pole-to-pole
output voltage can be zero, which allows duty cycle variation to achieve variable average output voltage
for each phase, within each carrier period, proportional to the magnitude of the position vector.
To facilitate vector positions (angles) that do not lie on one of the six quasi-square output vectors, an
intermediate vector Vo/p e jθ is resolved into the vector sum of the two quasi-square vectors adjacent to
the rotating vector. This process is shown in figure 17.25 for a voltage vector Vo/p that lies in sector I,
between output states v1 (001) and v3 (011). The voltage vector has been resolved (using Park’s
transformation) into the two components Va and Vb as shown.

The time represented by quasi-square vectors v1 and v3 is the carrier period Tc, in each case. Therefore
the portion of Tc associated with va and vb is scaled proportionally to v1 and v3, giving ta and tb.

The two sine terms in equation (17.74) generate two sine waves displaced by 120°, identical to that
generated with standard carrier based sinusoidal pwm.
The sum of ta and tb cannot be greater than the carrier period Tc, thus
t a  t b  Tc
(17.75)
t a  t b  t o  Tc
where the slack variable to has been included to form an equality. The equality dictates that vector v1 is
used for a period ta, v3 is used for a period tb, and during period to, the null vector, v0 or v7, at the centre
of the hexagon is used, which do not affect the average voltage during the carrier interval Tc.
747 Power Electronics

A further constraint is imposed in the time domain. The rotating voltage vector is a fixed length for all
rotating angles, for a given inverter output voltage. Its length is restricted in both time and space.
Obviously the resolved component lengths cannot exceed the pole vector length, Vs. Additionally, the
two vector magnitudes are each a portion of the carrier period, where ta and tb could be both equal to Tc,
that is, they both have a maximum length Vs. The anomaly is that voltages va and vb are added
vectorially but their scalar durations (times ta and tb) are added linearly. The longest time ta + tb possible
is when to is zero, as shown in figures 17.25a and 17.24a, by the hexagon boundary. The shortest
vector to the boundary is where both resolving vectors have a length ½Vs, as shown in figure 17.25b.
For such a condition, ta = tb = ½Tc, that is ta + tb = Tc. Thus for a constant inverter output voltage, when
the rotating voltage vector has a constant length, Vo /p the locus of allowable rotating reference voltage
vectors must be within the circle scribed by the maximum length vector shown in figure 17.25b. As
shown, this vector has a length v1 cos30°, specifically 0.866Vs. Thus the full quasi-square vectors v1, v2,
etc., which have a magnitude of 1×Vs, cannot be used for generating a sinusoidal output voltage. The
excess length of each quasi-square voltage (which represents time) is accounted for by using zero state
voltage vectors for a period corresponding to that extra length (1- cos30° at maximum output voltage).
The dwell time calculations for all six sectors are
t a  23 mT c sin( 13 n    )
t b  23 mT c sin(  13 (n  1) ) (17.76)
t o  Tc  t a  t b
where n represents sector number, 1 to 6, and m is modulation index m = Vo/p / Vs.
Having calculated the necessary periods for the inverter poles (ta, tb, and to), the carrier period switching
pattern can be assigned in two ways.
 Minimised current ripple
 Minimised switching losses, using dead banding
j?π j ?π
V3 =Vs e V3 =Vs e Tc
011 011

SECTOR I SECTOR I
Tc
ωt

Vo / p
tb
Vs cos30°
Vb  2 VO / P sin 
3 e j
VoV/pO/P ½v3 = ½Vs
θ ta 30° Tc
000 000
111 111
½v1 = ½Vs
Va  2 VO / P sin  13    
j0 j0
v1 =Vs e v1 =Vs e
3
001 001
(a) (b)
tb + ta < Tc
V3 =Vs e
j?π reduced to
Tc
011

60°-α tb + ta > Tc
no to
Vo /p  Vo /p
T
Tcc

Vo /p

tb + ta < Tc
reduced to
α Tc
000
111
j0
v1 =Vs e

001
(c)

Figure 17.25. First sector of inverter operational area involving pole outputs 001 and 011:
(a) general rotating voltage vector; (b) maximum allowable voltage vector length for undistorted
output voltages; and (c) over modulation.

Each approach is shown in figure 17.26, using single edged modulation. The waveforms are based on
the equivalent of symmetrical modulation where the pulses are symmetrical about the carrier trough. By
minimising the current ripple, seven switch states are used per carrier cycle, while for loss minimisation
(dead banding) only five switch states occur, but at the expense of increased ripple current in the output
Chapter 17 DC to AC Inverters – Switched Mode 748

current. When dead banding, the zero voltage state v0 is used in even numbered sextants and v7 is
used in odd numbered sextants.
Sideband and harmonic component magnitudes can be decreased if double-edged modulation
placement of the states is used, which requires recalculation of ta, tb, and to at the carrier crest, as well
as at the trough.

Over-modulation is when the magnitude of the demanded rotating vector is greater than Vo /p such that
the zero voltage time reduces to zero, to = 0, during a portion of the time of one rotation of the output
vector. Initially this occurs at 30°  16  2N sector  1  when the output vector length reachesVo /p , as shown
in figure 17.25b. As the demand voltage magnitude increases further, the region around the 30° vector
position where to ceases to occur, increases as shown in figure 17.25c. When the output rotational
vector magnitude increases to Vs, the maximum possible, angle α reduces to zero, and to ceases to
occur at any rotational angle. The values of ta, tb, and to (if greater than zero), are calculated as usual,
but pulse times are assigned pro rata to fit within the carrier period Tc.

The switching frequency can be decreased by using dc-link clamping like in 17.1.3vi. Each leg is
successively clamped, alternately to each dc rail (that is states 000 and 111 are alternated every 60°
when a zero state is required). For example, in sector 1, an odd sector number, the sequence would be
states [111] [011] [001] [011] [111]. In sector 2, an even sector number, the sequence would be states
[000] [010] [001] [010] [000]. In odd sector number zero vector [111] is used, while [000] is used in even
numbered sector.

v0 v1 v3 v7 v7 v3 v1 v0
000 001 011 111 111 011 001 000
¼ t o ½ ta ½ tb ¼ to ¼ t o ½ tb ¼ ta ¼ to

ΦR

ΦY

ΦB

Tc

(a)
v1 v3 v7 v7 v3 v1
001 011 111 111 011 001
½ ta ½ tb ¼ to ¼ t o ½ tb ¼ ta

ΦR

ΦY

ΦB

Tc
(b)

Figure 17.26. Assignment of pole periods ta and tb based on:

(a) minimum current ripple and (b) minimum switching transitions per carrier cycle, Tc.

17.1.4 Assessment of PWM modulation techniques

The following are some considerations when comparing different modulation techniques:
 Good utilization of DC power supply, that is, to deliver high output voltage for a given DC supply
 Good linearity in voltage and or current control
 Low harmonic content in the output voltage and currents, especially in the low-frequency region
 Low switching losses
749 Power Electronics

Figure 17.27 compares different PWM modulating signals, namely SPWM, THI, DBPWM and SVM, for
a three-phase inverter with a 500Hz switching frequency via a triangular carrier signal. Figure 17.27a
shows the fundamental inverter output phase voltage at different modulation indices where THI,
DBPWM and SVM give a higher fundamental component than SPWM. Figure 17.27b shows inverter
output phase voltage THD at different modulation indices where SPWM gives the highest THD.
Distortion factor, DF for inverter output phase voltage at different modulation indexes in Figure 17.27c
shows that THI gives the lowest DF at higher modulation indices.

0.7
SPWM

Fundamental phase voltage (pu)

0.6 SVM, THI, DB

0.5

0.4

0.3

0.2

0.1

0
0.2 0.4 0.6 0.8 1
Modulation index
(a)

400 9
SPWM SPWM
350 SVM, THI, DB SVM
THD for phase voltage %

8 THI
300
DF for phase voltage %

DB
250
7
200

150 6

100
5
50

0 4
0.2 0.4 0.6 0.8 1 0.2 0.4 0.6 0.8 1
Modulation index Modulation index
(c) (d)

Figure 17.27. Performance parameters for different modulation techniques:

(a) fundamental phase voltage; (b) THD for the phase voltage; and (c) DF for the phase voltage.

17.1.5 Common mode voltage

The common mode CM voltage is a remanent voltage with respect to a reference zero ‘o’ as shown in
figure 17.28(a). The line voltages and a common mode voltage Vcm can be derived based on leg phase
voltages (Vao, Vbo, Vco) of a two-level three-phase inverter, as follows:
V ao  V an Vcm
V bo  V bn Vcm
Vco  Vcn Vcm
The sum of the leg voltages is given by :
Vao Vbo Vco  (Van Vbn Vcn )  3Vcm
In a three-phase system:
Van Vbn Vcn  0
thus the common mode voltage source in a three-phase system is:
Vcm t   ⅓ Vao t  Vbo t  Vco t    ⅓ Va t  Vb t  Vc t  
where Va, Vb, Vc are the phase voltages, n is the load neutral, and o is the split dc link centre voltage
node.
Chapter 17 DC to AC Inverters – Switched Mode 750

The CM voltage is a staircase function with steps of ⅓Vdc (Vdc - dc link voltage) within a frequency of
three time the inverter modulation frequency, plus carrier related modulation steps superimposed, as
shown in figure 17.28. Because the Kirchhoff voltage loop is usually completed by capacitance, a train of
damped sinewave pulses of CM current flows as a result of each CM voltage step. In electrical
machines such currents cause bearing deterioration. Generally, in electrical circuits, the CM currents
through substrates, isolation capacitance, etc., produce and inject electrical noise and cause EMC
interference.

Van

a
o Vao n (a)

Vno

Two-level inverter Three-level inverter

(b) (c)

Figure 17.28. Inverter common mode voltage: (a) source voltages,

(b) two level inverter common mode voltage, and (c) three level inverter common mode voltage.

17.1.6 DC link voltage boosting

Both triplen injection and SVM under flux a 50/60Hz machine designed to operate from a given three-
phase ac mains supply. Increased dc rail voltage (over that produced from rectification) can be achieved
with the three-phase boost converter shown in figure 17.29. Additionally, being a boost converter, the ac
input current can be continuous, and forced to track any reference whilst maintaining the transferred
power balance between the input and the output. By using the ac mains as references, the input current
can be sinusoidal, of high quality and at any desired angle, usually in phase with the supply voltage -
unity power factor. The bridge acts as an uncontrolled rectifier when the output voltage is below the
mains rectified level, as during start-up when the dc link capacitor is uncharged. Near instantaneous
power reversal (by current direction reversal) is possible when the converter acts as a dc to ac inverter.
The power factor angle and three-phase voltage magnitude can be varied to control the active and
reactive power flows back into the ac grid. PWM or SVM control can insure sinusoidal current in both
conversion directions. Unbeknown to the power electronics community, this so called ‘boost’ converter
can control the dc output down to 0.86 the uncontrolled rectifier level if third harmonics (or SVM) are
used. As a bidirectional SVM converter (triplen injection), it offers better dc link utilisation as a dc to ac
inverter, and better ac source utilisation as an ac to dc converter.

Io

V1 Lin i1 S1 S5 S3

Lin i2
+ L
O Vdc
V2
A
D

Lin i3 S4 S2 S6
V3

Figure 17.29. PWM boost three-phase rectifier.

751 Power Electronics

17.2 DC-to-ac controlled current-source inverters

In the current source inverter, CSI, the dc supply is of high reactance, being inductive so as to maintain
the required inverter output bidirectional current independent of the inverter load. At medium and low
power levels CSIs use self commutating devices, as shown in figure 17.30. If IGBTs are used, figure
17.30a, series diodes are need for the necessary reverse blocking requirements, while the GGT devices
in 17.30b require symmetrical voltage blocking characteristics.

At high power levels (hvdc), it is still not uncommon to utilise the robustness of thyristor technology that
requires external commutation circuitry.

IDC

ac
grid

(a)

IDC
Load

Cfilter
(b)

Figure 17.30. Current source converters: (a) singe phase and (b) three phase.

17.2.1 Single-phase current source inverter

A single-phase, controlled current-sourced bridge is shown in figure 17.31a and its near square-wave
output current is shown in figure 17.31b. No freewheel diodes are required and the thyristors require
forced commutation and have to withstand reverse voltages. An inverter current path must be
maintained at all times for the source controlled current.
Consider thyristors T1 and T2 on and conducting the constant load current. The capacitors are charged
with plates X and Y positive as a result of the previous commutation cycle.

 Phase I
Thyristors T1 and T2 are commutated by triggering thyristors T 3 and T4. The capacitors impress negative
voltages across the respective thyristors to be commutated off, as shown in figure 17.32a. The load
current is displaced from T1 and T2 via the path T3-C1-D1, the load and D2-C2-T4. The two capacitors
discharge in series with the load, each capacitor reverse biasing the thyristor to be commutated, T 1 and
T2 as well as diodes D3 to D4. The capacitors discharge linearly (due to the constant current source).

 Phase II
When both capacitors are discharged, the load current transfers from D 1 to D2 and from D3 to D4, which
connects the capacitors in parallel with the load via diodes D 1 to D2. The plates X and Y now charge
negative, ready for the next commutation cycle, as shown in figure 17.32b. Thyristors T1 and T2 are
now forward biased and must have attained forward blocking ability before the start of phase 2.
Chapter 17 DC to AC Inverters – Switched Mode 752

Figure 17.31. Single-phase controlled-current sourced bridge inverter:

(a) bridge circuit with a current source input and (b) load current waveform.

- +
- +
+ -

-
- +
+

- +

+ -

(a) (b)
Figure 17.32. Controlled-current sourced bridge inverter showing commutation of T1 and T2 by T3 and
T4: (a) capacitors C1 and C2 discharging and T1, T2, D3, and D4 reversed biased and
(b) C1, C2, and the load in parallel with C1 and C2 charging.

The on-going thyristor automatically commutates the outgoing thyristor. This repeated commutation
sequencing is a processed termed auto-sequential thyristor commutation. The load voltage is load
dependent and usually has controlled voltage spikes during commutation.
Since the GTO and GCT both can be commutated from the gate, the two commutation capacitors C 1 and
C2 are not necessary. Commutation overlap is still essential. Also, if the thyristors have reverse
blocking capability, the four diodes D1 to D4 are not necessary. IGBTs require series blocking diodes,
which increases on-state losses. In practice, the current source inverter is only used in very high-power
applications (>1MVA), and the ratings of the self-commutating thyristor devices can be greatly extended
if the simple external capacitive commutation circuits shown in figure 17.31 are used to reduce thyristor
turn-off stresses.

17.2.2 Three-phase current source inverter

A three-phase controlled current-source inverter is shown in figure 17.33a. Only two thyristors can be on
at any instant, that is, the 120° thyristor conduction principle shown in figure 17.12 is used. A quasi-
square line current results, as illustrated in figure 17.33b. There is a 60° phase displacement between
commutation of an upper device followed by commutation of a lower device. An upper device (T1, T3, T5)
is turned on to commutate another upper device, and a lower device (T2, T4, T6) commutates another
lower device. The three upper capacitors are all involved with each upper device commutation, whilst
the same constraint applies to the lower capacitors. Thyristor commutation occurs in two distinct phases.
753 Power Electronics

 Phase I
In figure 17.34a the capacitors C13, C35, C51 are charged with the shown polarities as a result of the
earlier commutation of T5. T1 is commutated by turning on T 3. During commutation, the capacitor
between the two commutating switches is in parallel with the two remaining capacitors which are
effectively connected in series. Capacitor C13 provides displacement current whilst in parallel, C35
and C151 in series also provide thyristor T 1 displacement current, thereby reverse biasing T 1.

 Phase II
When the capacitors have discharged, T 1 becomes forward biased, as shown in figure 17.34b, and
must have regained forward blocking capability before the applied positive dv/dt. The capacitor
voltages reverse as shown in figure 17.34b and when fully charged, diode D 1 ceases to conduct.
Independent of this commutation, lower thyristor T 2 is commutated by turning on T4, 60° later.

Figure 17.33. Three-phase controlled-current sourced bridge inverter:

(a) bridge circuit with a current source input and (b) load current waveform for one phase
showing 120° conduction.

As with the single-phase current sourced inverter, assisted capacitor commutation can greatly improve
the capabilities of self-commutating thyristors, such as the GTO thyristor and GCT. Transient voltage
sharing of series connected devices is also aided. The output capacitors stiffen the output ac voltage.

A typical application for a three-phase current-sourced inverter would be to feed and control a three-
phase induction motor. Varying load requirements are met by changing the source current level over a
number of cycles by varying the link inductor input voltage.
An important advantage of the controlled current source concept, as opposed to the constant voltage
link, is good fault tolerance and protection. An output short circuit or simultaneous conduction in an
inverter leg is controlled by the current source. Its time constant is usually longer than that of the input
converter, hence converter shut-down can be initiated before the link current can rise to a catastrophic
level. Stray inductance in the capacitor commutation paths is a major problem at high power levels.
Chapter 17 DC to AC Inverters – Switched Mode 754

- Io + Io
- + + -
+ + - - - +

C35 C35
C13 C13

- + - - +
D1 C51 D1 D3 C51
+
Io

Io

Io Io

Io Io

(a) (b)

Figure 17.34. Controlled-current sourced bridge three-phase inverter showing commutation of T1

and T3: (a) capacitors C13 discharging in parallel with C35 and C51 discharging in series, with T1 and D3
reversed biased (b) C13, C35, and C51 charging in series with the load , with T1 forward biased.

PWM techniques are applicable to current source inverters in order to reduce current harmonics,
thereby reducing load losses and pulsating motor shaft torques. Since current source inverters are most
attractive in very high-power applications, inverter switching is minimised by using optimal pwm
(selected harmonic elimination). The central 60° portion about the maximums of each phase cannot be
modulated, since link current must flow and during such periods both the other phases require the
opposite current direction. Attempts to over come such pwm restrictions include using a current sourced
inverter with additional parallel current displacement paths as shown in figure 17.35. The auxiliary
thyristors, Tupper and Tlower, and capacitors, CR, CY, and CB, provide alternative current paths (extra
control states) and temporary energy storage. The auxiliary thyristor can be commutated by the extra
capacitors. The problem can be alleviated by triplen injection or SVM, which minimises the duration of
any such periods in the central 60° blocks, so that the link can be shorted for the short periods.
Characteristics and features of current source inverters
 The inverter is simple and can utilise rectifier grade thyristors. The switching devices must have
reverse blocking capability and experience high voltages (both forward and reverse) during
commutation. Extra losses are associated with two series devices, a diode and a thyristor.
 Commutation capability is load current dependent and a minimum load is required. This limits
the operating frequency and precludes use in UPS systems. The limited operating frequency
can result in torque pulsations.
 The inverter can recover from an output short circuit hence the system is rugged and reliable –
fault tolerant.
 The converter-inverter configuration has inherent four quadrant capability without extra power
components. Power inversion is achieved by reversing the converter average voltage output
with a delay angle of α > ½π, as in the three-phase fully controlled converter shown in figure
14.11 (or 17.4.3). In the event of a power supply failure, mechanical braking is necessary.
Dynamic braking is possible with voltage source systems.
 Current source inverter systems have sluggish performance and stability problems on light loads
and at high frequency. On the other hand, voltage source systems have minimal stability
problems and can operate open loop.
 Each machine must have its own controlled rectifier and inverter. The dc link of the voltage
source scheme can be used by many inverters or many machines can utilise one inverter. A
dc link offers limited ride-through.
 Current feed inverters tend to be larger in size and weight, because of the link inductor and
filtering requirements.
755 Power Electronics

T1 T5 T3
Tupper

CR

CY

CB

Tlower T4 T2 T6

(a)

IR
+Io

ωt

-Io

(b)
Figure 17.35. Three-phase controlled-current sourced bridge inverter with alternative commutation
current paths: (a) bridge circuit with a current source input and two extra thyristors and
(b) load current waveform for one phase showing 180° conduction involving pwm switching.

17.3 Multi-level voltage-source inverters

The conventional three-phase, six-switch dc to ac voltage-source inverter is shown in figure 17.7. Each
of the three inverter legs has an output which can provide one of two voltage levels, Vs, when the upper
switch (or diode) is on, and 0 when the lower switch (or diode) conducts. The quality of the output
waveform is determined by the resolution and switching frequency of the pwm technique used.

½Vs ½Vs
½Vs
Vs /N-1
½Vs Vs /N-1
a a a
0 0
Vs 0
½Vs
Va0 Va0 Va0
Vs /N-1

-½Vs -½Vs
-½Vs
+½Vs

+½Vs +¼Vs
+½Vs
0V 0V t
t t
-½Vs
-½Vs -¼Vs

(a) (b) (c) -½Vs

Figure 17.36. One phase leg of a voltage-source bridge inverter with:

(a) two levels; (b) three levels; and (c) N-levels, with N-1 capacitors and waveform for five levels.
Chapter 17 DC to AC Inverters – Switched Mode 756

A multilevel inverter (directly or indirectly) divides the dc rail, so that the output of the leg can be more
than two discrete levels, as shown in figure 17.36 for a diode clamped multilevel inverter model. In this
way, the output quality is improved because both pulse width modulation and amplitude modulation can
be used. The output pole is made from more than two series connected, clamped switches, so the total
dc voltage rail can be the sum of the voltage rating of the individual switches. Very high output voltages
can be achieved, where each device does not experience a voltage in excess of its individual rating.

A multilevel inverter allows higher output voltages with low distortion (due to the use of both pulse width
and amplitude modulation) and reduced output dv/dt.
There are four main types of multilevel converters
 Diode clamped
 Flying capacitor
 Cascaded H-bridge, and
 Modular multilevel

17.3.1 Diode clamped multilevel inverter

Figure 17.36 shows the basic principle of the diode clamped (or neutral point clamped, NPC) multilevel
inverter, where only one dc supply, Vs, is used and N is the number levels present in the output voltage
between the leg output and the inverter negative terminal, Va-neg. The capacitors split the dc rail voltage
into a number of lower voltage levels, each of which can be tapped and connected to the leg output
through switches (and diodes). Only one string of series connected capacitors is necessary for any
number of output phase legs.
The number of levels in the line-to-line voltage waveform will be
k  2N  1 (17.77)
while the number of levels in the line to load neutral of a star (wye) load will be
p  2k  1 (17.78)
The number of capacitors required, independent of the number of phase, is
N cap  N  1 (17.79)
while the number of clamping diodes per phase is
Dclamp  2 N  2 but N  1N  2 if rated at switch voltage (17.80)
The number of possible switch states is
nstates  N phases (17.81)
and the number of switches (and inverse parallel diodes) in each leg is
S n  2 N  1 (17.82)
The basic three-level inverter (±½Vs, 0) is shown in figure 17.37, along with the basic three-level voltage
from the leg output to centre tap of the capacitor string, R (neutral point). When switch T1 is on, its
complement T1′ is off, and visa versa. Similarly for the pair of switches T 2 and T2′. Specifically T1 and T2
on give the output +½Vs, T1′ and T2′ on give the output -½Vs, and T2 and T1′ on give the output 0.
Essential to attaining these output levels, are the clamping diodes Du and Dℓ. These two diodes clamp
the outer switches to the capacitor string mid-point, which is half the dc rail voltage. In this way, no
switch experiences a voltage in excess of half the dc rail voltage. Inner switches must be turned on (or
off) before outer switches are turned on (or off).
The five-level inverter uses four capacitors, and eight switches in each inverter leg. A set of clamping
diodes (three in total for each leg) clamp the complementary switches in each leg. The output is
characterised by having five levels, ±½Vs, ±¼ Vs, and zero. Some of the clamping diodes experience
voltages in excess of that experienced by the main switches. Series connection of some of the clamping
diodes avoids this limitation, but at the expense of increasing the number of clamping diodes from 2×
(N-2) to (N-1)×(N-2) per phase. Thus, depending on the diode position in the structure, two diodes have
blocking requirements of
N 1  k
VRB  V (17.83)
N 1 s
where 1 ≤ k ≤ N-2. These diodes require series connection of diodes, if all devices in the structure are to
support Vs /(N-1). For N > 2, capacitor imbalance occurs at high modulation indices.
The general output voltage, to the centre of the capacitor string is given by
Vs
Van  (T  T 2  .. ..  T N 1  ½ N  1) (17.84)
N 1 1
Common to all diode clamped inverter, each phase leg is identical in structure, and all legs share a
common dc link capacitor string.
Table 17.5 in combination with the six parts of figure 17.38, show the conducting devices for the six
different output voltage and current combinations of the NPC inverter leg. The commercial inverter,
757 Power Electronics

HVDC Light, uses the NPC structure in figure 17.37, but uses extensive series connection of devices to
achieve a high dc link voltage. The main problem in increasing the number of output voltage levels,
other than increased circuit complexity, is voltage balancing the dc link series connected capacitors at
higher modulation levels, M>½(N-1). This capacitor voltage balancing problem can be avoided when two
multilevel inverters are used in an ac-dc-ac back to back converter arrangement, where the link
capacitors are common to both converters.

T1 D1
Cu ½Vs Dcu

T2 D2
Vs
R

D1’
C
Cℓ? ½Vs T1’

Dcℓ
Dc? D2’
T2’
neg

ia ib b ic
VaR

+½Vs
t c
0 Vba o

-½Vs
a Vao

Figure 17.37. Three-phase, voltage-source, three-level, diode-clamped (NPC) bridge inverter.

Table 17.5: Conduction paths in the diode clamped three-level inverter

On Output current and path Active clamping

Vout
switches + iL I - iL diodes
½ Vs T1 T2 T1 T2 Fig 17.38a D1 D2 Fig 17.38d none

0 T1′ T2 Dcu T2 Fig 17.38b T1′ Dcℓ Fig 17.38e Dcu Dcℓ

-½ Vs T1′ T2′ D1′ D2′ Fig 17.38c T1′ T2′ Fig 17.38f none
Chapter 17 DC to AC Inverters – Switched Mode 758

+½Vs +½Vs +½Vs

T1 D1′ T1 D1′ T1 D1′

T2 D2 T2 D2 T2 D2

0 vo 0 vo 0 vo
iL > 0 iL > 0 iL > 0
T1′ D1′ T1′ D1′ T1′ D1′

T2′ D2′ T2′ D2′ T2′ D2′

-½Vs -½Vs -½Vs

iL > 0 vo = ½Vs iL > 0 vo = 0 iL > 0 vo = -½Vs

(a) (b) (c)

+½Vs +½Vs +½Vs

T1 D1′ T1 D1′ T1 D1′

T2 D2 T2 D2 T2 D2

0 vo 0 vo 0 vo
iL < 0 iL < 0 iL < 0
T1′ D1′ T1′ D1′ T1′ D1′

T2′ D2′ T2′ D2′ T2′ D2′

-½Vs -½Vs -½Vs

iL < 0 vo = ½Vs iL < 0 vo = 0 iL < 0 vo = -½Vs

(d) (e) (f)

Figure 17.38. The six output voltage and current combinations for the NPC bridge inverter:
(a), (b), (c) output current iL > 0; and (d), (e), (f) output current iL < 0.

17.3.2 Flying capacitor multilevel inverter

One leg of a fly-capacitor clamped five-level voltage source inverter is shown in figure 17.39b, where
capacitors are used to clamp the switch voltages to ¼Vs. The available output voltages are ±½Vs, ±¼Vs,
and 0, where the output is connected to the dc link (Vs and 0) indirectly via capacitors. Figure 17.39
shows that in general, switches T n and Tn+1 connect to capacitor Cn. The configuration offers more
usable switch states than the clamped diode inverter, and this redundancy allows better, flexible control
of capacitor voltages. For example, Table 17.5 shows that there are six states for obtaining 0V output,
and four states for each of ±¼Vs. The output states ±½Vs do not involve the capacitors, hence they offer
no redundant states. The basic switch restriction is that only one complementary switch (for example, T4
or T4′ ) is on at any time, so as to prevent shorting of a flying capacitor (e.g., T4 and T4′ would short C3).
The number of levels in the line-to-line voltage waveform will be
k  2N  1 (17.85)
while the number of levels in the line to load neutral of a star (wye) load will be
p  2k  1 (17.86)
The number of capacitors required, which is dependent of the number of phase, is for each phase
N cap  ½ N  1N  2 (17.87)
The number of possible switch states is
nstates  N phases (17.88)
and the number of switches in each leg is
S n  2 N  1 (17.89)
759 Power Electronics

VC1 T1 D1
VCu
VC1 Vs
T1 D1 Cu
C1 T2 D2 phase
VCu a
T2 D2 R
VC2
CC?ℓ T2? D2?
Cu VCℓ
VC?
T1? D1?
VC3 T3 D3

Vs
C1 C2 C3 T4 D4
phase
VCℓ R a (a)
V C?

¾Vs ½Vs ¼Vs ′ D′4?

T4?

C
Cℓ?
′
′ D3?
T3?

′ D′2? (b)
T2?

′ D′1?
T1?

Figure 17.39. One leg of a voltage-source:

(a) three-level and (b) five-level, flying capacitor clamped bridge inverter.

Table 17.6: Five-level flying-capacitor inverter output states (phase A to R)

switch states capacitors

mode VAR paths
T1 T2 T3 T4 C1 C2 C3
1 ½Vs 1 1 1 1 = = = ½Vs
1 1 1 0 = = + ½Vs -VC3
2
1 1 0 1 = + - ½Vs -VC2+VC3
¼Vs
N-1 1 0 1 1 + - = ½Vs-VC1+VC2
states
0 1 1 1 - = = -½Vs+VC1
1 1 0 0 = + = ½Vs -VC2
1 0 1 0 + - + ½Vs-VC1+VC2 -VC3
3
0 1 1 0 - = + -½Vs+VC1-VC3
0
N2-4N+1 1 0 0 1 + = - ½Vs-VC1+-VC3
states
0 1 0 1 - + - -½Vs+VC1-VC2+VC3
0 0 1 1 = - = -½Vs +VC2
1 0 0 0 + = = ½Vs-VC1
4
0 1 0 0 - + = -½Vs+VC1-VC2
-¼Vs
N-1 0 0 1 0 = - + -½Vs -VC2 -VC3
states
0 0 0 1 = = - -½Vs +VC3
5 -½Vs 0 0 0 0 = = = -½Vs
Chapter 17 DC to AC Inverters – Switched Mode 760

The current output paths in Table 17.6 are made up by the series (and parallel) connection of the flying
capacitors through the turn-on of the appropriate switches. Capacitors shown as negative are
discharging in the formed path, while those shown as positive are charging. Use of the shown
redundant states allows control to maintain the necessary voltage level on all the flying capacitors, while
providing the desired output voltages.
A feature of the flying capacitor multilevel inverter is its ride through capability due to the large
capacitance used. On the other hand, the capacitors have a high voltage rating and suffer from high
current ripple, since they conduct the full load current when connected into an active output voltage
state. Capacitor initial charging is also problematic, especially given the capacitors for each leg, and
between the different legs, are independent.

If all the flying capacitors are voltage rated at the switch voltage level, then C 2 comprises two series
connect capacitors and C3 comprises three series capacitors, and all the same voltage rating as C 1.

17.3.3 Cascaded H-bridge multilevel inverter

The N-level cascaded H-bridge, multilevel inverter comprises ½(N-1) series connected single-phase H-
bridges per phase, for which each H-bridge has its own isolated dc voltage source. For each bridge, as
shown in table 17.7, three output voltages are possible, ±Vs, and zero, giving a total number of states of
3½( N 1) , where N is odd. Figure 17.40 shows one phase of a seven-level cascaded H-bridge inverter.
The cascaded H-bridge multilevel inverter is based on multiple two level inverter outputs (each H-
bridge), with the output of each phase shifted. Despite four diodes and switches, it achieves the
greatest number of output voltage levels for the fewest switches.

Vs
T1 D1 D2 T2

V1

T3 D3 D4 T4

Vs
T1 D1 D2 T2

V1

T3 D3 D4 T4

Vs
T1 D1 D2 T2

V1

T3 D3 D4 T4

Figure 17.40. One leg of a voltage-source, seven-level, cascaded H-bridge inverter.

761 Power Electronics

Table 17.7: Three output states of H-bridges and their current paths.

On Bidirectional current paths

Vℓ
switches + iL - iL
Vs T2 T3 T2 T3 D2 D3
0 none D4 D1 D2 D3
-Vs T1 T4 T1 T4 D2 D3

Its main limitation lies in the need for isolated power sources for each H-bridge and for each phase,
although for VA compensation, capacitors replace the dc voltage supplies, and the necessary capacitor
energy is only to replace losses due to inverter losses. Its modular structure of identical H-bridges is a
positive design feature.

The number of levels in the line-to-line voltage waveform will be

k  2N  1 (17.90)
while the number of levels in the line to load neutral of a star (wye) load will be
p  2k  1 (17.91)
The number of capacitors or isolated supplies required per phase is
N cap  ½ N  1 (17.92)
The number of possible switch states is
nstates  N phases (17.93)
and the number of switches in each leg is
S n  2 N  1 (17.94)

17.3.4 Capacitor clamped modular multilevel M2C inverter

The capacitor-clamped modular multilevel inverter has several advantages compared to conventional
multilevel inverters, such as: modular construction; can be extended to any number levels; capacitor
voltage balance is attainable for any number of voltage levels; for a large number of voltage levels
extremely low total harmonic distortion can be achieved without the need for filters. In addition, to
reduced voltage stress on switching device dv/dt; and it has failure management capability in the case of
device failures.
Figure 17.41 shows one cell of a capacitor-clamped multilevel converter, when the switching device Sm
is turned on and Sc is turned off, the voltage Vo = 0; when the switching device Sm is turned off and Sc is
turned on, the voltage Vo = Vdc. Table 17.8 and figure 17.41b summarizes the switch states of a cell
shown in Fig. 17.41 and their influence in capacitor voltage. Switches Sm and Sc are complementary,
when any one of them is on.
Figure 17.42 shows one-phase of the three-level capacitor-clamped inverter in which each voltage level
can be synthesized by turning four switching devices simultaneously; in each instant two switches must
belong to (Sy1, Sy2, Sy3 and Sy4) and the remaining two from auxiliary switches (Sx1, Sx2, Sx3 and Sx4).
There are four complementary switch pairs in each phase, turning on one of the pair switches will
excluded the other from being turned on. The four complementary switches are (S y1, Sx1), (Sy2, Sx2), (Sy3,
Sx3) and (Sy4, Sx4). For a dc bus of Vdc, the voltage across each cell capacitor is ½Vdc and each switching
device voltage stress is limited to one capacitor voltage. For an n-level converter, the voltage across
each capacitor and switching device is limited to Vdc /(n-1) while the number of switching devices (IGBT
plus free wheeling diode) required per phase is doubled that for multipoint clamped converters. The
number of capacitors required for three-phases is 6n-6 (2n-2 per phase), while no clamping diodes are
required. To explain how the multilevel waveform voltage is synthesized, the supply mid point is
assumed the output voltage reference. Using the three-level converter circuit shown in Figure 17.42 as
an example, there are six switching combinations to synthesize three-level voltages between x and o.
1. For voltage level Vxo = ½Vdc, turn on all the upper main switches (Sy1 and Sy2) and all the lower
auxiliary switches (Sx3 and Sx4).
2. For voltage level Vxo = 0, there are four different switch combinations:
a) turn on Sy1, Sy3, Sx2 and Sx4
b) turn on Sy2, Sy3, Sx1 and Sx4
c) turn on Sy2, Sy4, Sx1 and Sx3
d) turn on Sy1, Sy4, Sx2 and Sx3
3. For voltage level Vxo = -½Vdc, turn on all the upper auxiliary switches (Sx1 and Sx2) and all the
lower main switches (Sy3 and Sx4).
Chapter 17 DC to AC Inverters – Switched Mode 762

Dc Io
Sc

+
Vdc Sm
C Vo
Dm

State (0,0) State (1,0) State (0,1)

Icell > 0 Sa1 Sa1 Sa1

Da1 Da1 Da1
+ + +
Sa2 Sa2 Sa2
Da2 Da2 Da2

Sa1 off Sa1 on Sa1 off

Sa2 off Sa2 off Sa2 on

Icell < 0 Sa1 Sa1 Sa1

Da1 Da1 Da1
+ + +
Sa2 Sa2 Sa2
Da2 Da2 Da2

Figure 17.41. Structure of one cell in capacitor-clamped multilevel converter

and its current direction dependant conduction states.

Table 17.8: Switch states of one cell

Sm Sc Vo Current direction Power path Capacitor state

ON OFF 0 io > 0 Sm unchanged
ON OFF 0 io < 0 Dm unchanged
OFF ON Vdc io > 0 Dc charging
OFF ON Vdc io < 0 Sc discharging
763 Power Electronics

Dx1

+ Sy1
Sx1 Dy1
½Vdc C1
+
½Vdc
Dx2

+ Sy2
Sx2 Dy2
½Vdc C2

L Iy
0 y
L
Dx3

+ Sy3
Sx3 Dy3
½Vdc C3
+ Vyo
½Vdc
Dx4

+ Sy4
Sx4 Dy4
½Vdc C4

Figure 17.42. Schematic for one-leg of a three-level capacitor-clamped multilevel (M2C) inverter.

Table 17.9 lists the voltage levels and their corresponding switch states. State condition 1
means the switch is on, and 0 means the switch is off. In order to maintain equal voltage stressing on
the switching devices, the voltage across each cell capacitor must be maintained at ½Vdc.

Table 17.9: Switching combinations for three-level capacitor-clamped M2C converter

output voltage switch states

Vxo Sy1 Sy2 Sy3 Sy4 Sx1 Sx2 Sx3 Sx4
½Vdc 1 1 0 0 0 0 1 1
1 0 1 0 0 1 0 1 (a)
0 1 1 0 1 0 0 1 (b)
0
0 1 0 1 1 0 1 0 (c)
1 0 0 1 0 1 1 0 (d)
½Vdc 0 0 1 1 1 1 0 0

A consequence of capacitor voltage balancing and PWM operation is a significant dc current component
in each leg that contributes to an increase in switch losses.

Multilevel topology comparison

A comparison between the three basic multilevel inverters is possible from the numerical summary of
component numbers for each inverter, as in Table 17.10.
The diode clamped inverter requires many clamping diodes; the flying capacitor inverter requires many
independent capacitors; while the cascaded inverter requires many isolated dc voltage power supplies.
 Chapter 17 DC to AC Inverters – Switched Mode 764

Table 17.10: Multilevel inverter component count, per phase

levels switches Outer hex
Inverter type diodes flying level isolated
& // redundant
* either /or VA-0V VA-B VA-N clamping capacitors capacitors supplies
diodes states
diode clamped N 2N-1 4N-3 2(N-1) (N-1)(N-2) 0 (N-1) 1 0
flying capacitor N 2N-1 4N-3 2(N-1) 0 ½(N-1)(N-2) (N-1) 1 yes
cascade N (odd) 2N-1 4N-3 2(N-1) 0 0 ½ (N-1)* ½(N-1)* n/a
capacitor clamped N 2N-1 4N-3 4(N-1) 0 0 2(N-1) 1 yes

17.3.5 PWM for multilevel inverters

Two basic approaches can be used to generate the necessary pwm signals for multilevel inverters. Each
approach is based on the extension of a two level equivalent.
 Modulating waveform comparison with offset triangular carriers
 Space vector modulation based on a rotating vector in multilevel space

17.3.4i - Multiple offset triangular carriers

Various sinusoidal pwm techniques were considered in sections 17.1.3v and 17.1.3vi of this chapter.
Figure 17.43 shows how a triangular carrier is associate with each complementary switch pair, four
carriers (N-1) for the five-level inverter as illustrated. The parts of figure 17.43 show how the four
individual carriers can be displaced with respect to one another. The figure also shows how triplen
injection is incorporated. The appropriate five-level switch states, as in tables 17.4 to 17.6, can be used
to decode the necessary switching sequences. To minimise losses, switching is restricted to only occur
between adjacent levels.
1.5

½Vs 1


¼Vs 0.5

0
V oltage(pu)

0 0


-¼Vs -0.5

0
-½Vs -1

-1.5
0 0.002 0.004 0.006 0.008 0.01
t(s )
0.012 0.014 0.016 0.018 0.02 1
1.5

1
½
0
0.5

0
V oltage(pu)

0
0
0
-0.5

0
-1
-½
-1.5
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
t(s)

1.5
-1
1

0
0.5

0
V oltage(pu)

0
-0.5

0
-1

-1.5
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
t(s)

Figure 17.43. Multi-carrier based pwm generation for a voltage-source, 5-level, inverter.
765 Power Electronics

17.3.4ii - Multilevel rotating voltage space vector

Space vector modulation for the two-level inverter was considered in section 17.1.3vi of this chapter.
The basic hexagon shape for two levels is extended to higher levels as shown in figure 17.44, for three
levels. The number of triangles, vectors, and states increases rapidly as the level number increases.

Table 17.11: Properties of N-level vector spaces

levels states triangles vectors vectors

N N3 6(N-1)2 3N(N-1)+1 in each hexagon
2 8 6 7 (1+6)
3 27 24 19 (1+6)+12
5 125 96 61 (1+6)+12+18+24

From Table 17.11, the states for the two and three level inverters can be specified as follows.

The 2-level inverter

The zero state matrix is
000 111
The first and only hexagon is shown in figure 17.24a.
100 110 010 011 001 101
The three level inverter
The zero state matrix is
000 111 222
The first hexagon matrix is
100 110 010 011 001 101 
211 221 121 122 112 212
 
The second hexagon matrix is
200 210 220 120 020 021 022 012 002 102 202 201

These pole states are shown figure 17.44. β

020 120 220

021 010 110

210
121 221
000
011 100
022 111 200
122 211
222 α
001 101
012 201
112 212

002 102 202

β parallelogram β parallelogram p2
V4

V p1
V2
V
V2
p2

V3 p1

V1 V1

α α

Figure 17.44. Rotating voltage space vector approached applied to three phases of a voltage-source
three-level, inverter and decomposition of the vector in a given parallelogram.
Chapter 17 DC to AC Inverters – Switched Mode 766

A ′0′ represents the minimum voltage obtainable from the multilevel converter and N-1 represents the
maximum value. For example, in a two-level converter, ′0′ is equivalent to 0V and ′1′ is equivalent to Vs,
where Vs is the converter DC link voltage. In a three-level converter ′0′ is equivalent to -½Vs, ′1′ is
equivalent to 0 V, and ′2′ is equivalent to ½Vs where Vs is the dc link voltage of the multilevel converter.
When the rotating vector is drawn in the vector space, it is decomposed into vectors bordering the
triangle it lies in. When operating in the outer hexagon, the vectors states used in the inner most
hexagon mean that that level of the converter is operating with a six-step quasi-square output voltage
waveform, to which is added a modulated square waveform for the next higher level.

Generally, the rotating vector can lay in one of two triangles of any parallelogram. Once the
parallelogram has been uniquely decoded, for the triangle nearer the origin:
   
V  p1 V 1 V 3  p 2 V 2 V 3 V 3  p1V 1  p 2V 2  1  p1  p 2 V 3
(17.95)
 p 1  p 2 V 3
while for the triangle further from the origin:
   
V  p1 V 1 V 4  p 2 V 2 V 4 V 4  p1V 1  p 2V 2  1  p1  p 2 V 4
(17.96)
 p 1  p 2 V 4
where p1 and p2 are the relative duration lengths of the active vectors V1 and V2.
The zero vectors, V3 and V4, constitute the remaining time in the carrier period not assigned to the V1
and V2 associated duration components. The periods associated with p1V1 and p2V2 are distributed
within the carrier period as for to level SVM in section 17.1.3vii-2.
Since SVM decomposes a single rotating vector into three identical components displaced by 120°, such
a modulation strategy may not be applicable to any inverter used for FACTS type applications since
phases may be unbalanced, distorted or phase shifted.

Multilevel converter advantages:

 Low THD and lower dv/dt than conventional two-level converters at the same switching frequency.
 Blocking voltage of each switch is clamped to a divided capacitor link voltage level.
 Lower common mode (CM) voltage, thus reduce insulation stresses. With sophisticated
modulation methods, the CM voltage can be eliminated.
 Scalable to different power and voltage levels.
 Inherent reliability. If a multilevel converter component fails, the desired output voltage can still be
produced because of module redundancy.

Multilevel converter disadvantages:

 Control becomes complex with increased number of levels.
 Multiple DC voltages are required, which are usually provided by capacitors.
 Balancing capacitor voltages is a challenge.
 Switching losses increase with an increase in the number of levels.
 Numerous clamping diodes and capacitors are required, therefore system costs increase.
 Switching device current ratings vary due to different conduction duty cycles.

17.4 Reversible dc link converters

Power inversion by phase angle control is attained with a fully controlled single-phase converter as
discussed in section 14.2.3. Power regeneration is also possible with the fully controlled three-phase
converter shown in figure 14.11. If a fully controlled converter supplies a dc machine, two-quadrant
control is possible (QI and QII), motoring in one direction of rotation and generating in the other
direction. Power regeneration into the supply is achieved by reversing the dc output voltage by
controlling the converter phase delay angle. The converter current is uni-directional, that is, the
converter output current cannot reverse.
The dual or double converter circuit in figure 17.45a and b will accommodate four-quadrant dc machine
operation, where the circuit performs as two fully controlled converters in anti-parallel. Each converter is
able to rectify and invert, but because of their inverse parallel connection, one converter (the positive
converter P) operates in quadrants QI and QII, while the other (the negative converter N) operates in
quadrants QIII and QIV, as shown in figure 17.46.
The two converters can be operated synchronously, called simultaneous control (circulating current
mode) or independently where one is always blocking, called independent control (non-circulating
current mode).
767 Power Electronics

17.4.1 Independent control

Simultaneous converter control can be used if continuous load current can be guaranteed. Otherwise
only one converter, depending on the quadrant, need operate at anyone time (the other is in a blocking
state), as shown in figure 17.45a. No circulating currents arise due to possible mismatched N and P
converter output voltages. The continuous current condition may be difficult to ensure at light load levels.
Additional series armature inductance, L in figure 17.45a and b, helps with current smoothing and
ensuring continuous machine current.

+I

α1 L
+
α2
+V (a)

-
V
P N
IV I I
III II dc link +I

α1 L
+
α2
+V
(b)
-

P N

+I
α1 +
α2
+V

-
(c)

P N

(d)
dc link
input L-C
filter output
filter
rectifier/
converter

3Φ 3Φ
input inverter output

½L

Figure 17.45. Reversible converter allowing four-quadrant control of: (a) a dc machine with
independent converters; (b) a dc machine with simultaneously controlled converters; and
(c) voltage and (d) current fed induction machine.
Chapter 17 DC to AC Inverters – Switched Mode 768

A machine rotational direction change is affected by the following converter operating procedure.
 Initially the motor is operating in quadrant I (rectification), with 0° ≤ α1 ≤ 90° for the positive
converter P. The negative converter, N, is in the fully blocking state, with all thyristors turned off.
Both Vo and Io are positive, hence the average load power Po is positive with power flowing from
ac source to the load.
 The positive converter is put into the inverting mode with 90° ≤ α1 ≤ 180°, (quadrant II) changing
the average output voltage from positive to negative. Vo is negative and Io is positive, hence the
average load power Po is negative with power flowing from the load circuit to the ac [Link]
machine current rapidly falls to zero. The machine rotational speed slows, the rate depending on
the load inertia.
 After a dead time, the positive converter blocks and the negative converter N starts in a motor
braking mode in quadrant II, with 0° ≤ α2 ≤ 90°. The motor speed falls rapidly to zero.
 The second converter operates in quadrant III and rapidly accelerates the motor in the opposite
direction, with 0° ≤ α2 ≤ 90°. Both Vo and Io are negative, hence the average load power Po is
positive with power flowing from ac source to the load.
Reversal back to the original direction commences with
 With converter P remaining off, converter N operates with α2 > 90° in the inversion mode,
quadrant IV. Vo is positive, Io is negative hence the average load power Po is negative. Power
(hence energy) flows from the load circuit to the ac supply source.

The dead time before turning on the negative converter N is to ensure the positive converter P is fully off
(and vice versa), otherwise the three-phase input voltage lines may short through the two converters.
Such a current condition cannot be controlled with line-commutated thyristors. Operation is
characterised by transitions from QI to QII to QIII for reversal, and transitions from QIII to QIV to QI
for returning to the original direction of rotation. Transition between the two converters occur with dead
times so that only one converter is ever activated.
speed
vo

Ia Ia
+ +
N energy P
α1
E E
< 90°
vo vo

α2 > 90° energy

regenerative braking
/inversion
III I motor/rectification torque
V
motor/rectification I regenerative braking Ia
III IV /inversion
I
N
Ia P Ia

energy vo α1 vo
E E
> 90°
+ +
α2 < 90°
energy

Figure 17.46. Four quadrants of reversible converter operation.

17.4.2 Simultaneous control

Simultaneous converter control, also called circulating current control, functions with both converters
always in operation which gives a faster dynamic response than when the converters are used mutually
exclusively. To avoid supply short circuits requires that the output voltage of both converters (rectifier Vr
and inverter Vi) be the same in order to minimise circulating currents.
769 Power Electronics

V r V i 0
V cos 1 V cos 2 0
(17.97)
cos 1  cos 2 0
that is 1  2
 180
Equation (17.97) implies that both converters operate with firing angles that sum to 180°. Each
converter produces the opposite polarity average output voltage, which is cancelled by reversing the
relative output connections. Under such conditions the load current can be maintained continuous. To
minimize any circulating current due to ripple voltage produced by instantaneous voltage differences
between the two converters, inductance Lr is usually inserted between each converter and the dc
machine load, as shown in figure 17.45b. Adversely the cost and weight are increased, and the supply
power factor and drive efficiency are decreased, compared to that obtained with independently
controlled converters.

During interval  + 1 to ½ + 1, the line to line voltage vab appears across the output of converter 1
and vbc appears across the output of converter 2
If vo1 and v o2 are the output voltages of converters 1 and 2 respectively, the instantaneous voltage
across the circulating current limiting inductor Lr during the interval  + 1  t  ½ + 1 such that 1
+2 =, is given by
v r  v o 1  v o 2  v ab  v bc
v r  3 2 V sin t  1 6    sin t  ½  
v r t   3 2 V cos t  1 6   (17.98)
The circulating current is
t
1
i r t    v r t  d t
 Lr 
1
6
t
1
i r t    3 2 V cos  t  1 6   d t
 Lr 
1
6


3 2V
ir  (17.99)
 Lr

Converter P output α1 = 60°

Converter N output α1 = 120°

Inter-converter inductor
voltage

Figure 17.47. Reversible converter output voltages and output ripple voltage

A machine rotational direction change is affected by the following converter operating procedure.
 Initially the motor is operating in quadrant I for the rectifying, positive converter, with 0° ≤ α1 ≤
90°. The other converter is operating in the inverting mode with 90° ≤ α2 ≤ 180°, such that α1 + α2
Chapter 17 DC to AC Inverters – Switched Mode 770

= 180°. The output voltage for both converters is the same, and the negative converter N carries
only the circulating current.
 For rotational direction reversal, α1 ≥ 90° and α2 ≤ 90°, such that α1 + α2 = 180°. The armature
back emf voltage now exceeds the converter output voltages, and current diverts to the negative
converter N and the machine regeneratively brakes, operating in quadrant II. The current
rapidly falls to zero and the positive converter P carries only the ac circulating current.
 The speed rapidly falls to zero, with α1 = α2 = 90° giving zero output voltage, so as to control the
armature current since the back emf is zero. Then with α2 < 90° the machine rapidly accelerates
in quadrant III, in the reverse direction to the original rotation.
For reversing the direction of rotation from Q III the operation sequence is QIII to QIV to QI. Since no
converter dead time is introduced, a fast dynamic response can be attained. A small dc circulating
current is deliberately maintained, that is greater in magnitude than the peak of the ac ripple current. The
ac current can then flow continuously in both converters, both of which can operate in the continuous
conduction mode without the need for continuous converter current reversal operation.

17.4.3 Inverter regeneration

The bridge freewheel diodes of a three-phase inverter restrict the dc rail or dc link voltage from
reversing. The dual or double converter circuit in figure 17.45c will allow inversion with a three-phase
voltage source inverter. One converter rectifies, the other converter inverts, functioning as a self-
commutated inverter, transferring power from the dc link to the ac supply. Complete four-quadrant
control of the three-phase ac machine on the inverter is achieved in conjunction with control of the dc to
ac inverter. That is, motor reversal is achieved by effectively interchanging the pwm control signals
associated with two phases. The real power flow back into the ac supply is controlled by the converter
phase delay angle, while the reactive power flow is controlled by the voltage magnitude. The angle and
voltage are not independent. In the case of a pwm controlled inverter fed ac machine, the ac to dc
converter can be uncontrolled, using all diodes, since dc output voltage reversal is not utilised.

Figure 17.45d shows a fully reversible current controlled converter/inverter configuration, using self-
commutating devices. The use of self-commutated switches (rather than mains commutated converter
thyristors) offers the possibility to minimise the input current distortion and to reduce the inductor size
hence improve the dynamic current response. The switch series diodes are essential since the shown
IGBTs have no useable reverse blocking capability. The use of reverse blocking GCTs avoids the need
for the series blocking diodes, which reduces the on-state voltage losses but increases gate drive
complexity and power rating. Series connection of devices is necessary above a few kV, and above 1
MVA the GCT dominates.

17.5 Standby inverters and uninterruptible power supplies

Standby inverters and uninterruptible power supplies ( UPS’s) provide a 50/60 Hz supply in the event of
an ac mains failure. A UPS must provide ac output such that mains failure is undetected by the load. To
achieve this, a UPS continually feeds the load from an inverter. A load that can tolerate a short
interruption of the ac supply is fed from a standby inverter which becomes operational within 1-5 ms
after the ac supply failure. In communications, computing, and automated production lines, UPS’s are
essential for even brownouts (V and f outwith bounds for reliable equipment operation), while in lighting
and heating applications, standby inverters are used since a few missing ac cycles (due to a blackout -
total interruption of the mains power) may be tolerated. In each power supply case, the alternative
energy source is a standby dc battery. The UPS keeps the battery charged when the ac input is
supplying the output power.

17.5.1 Single-phase UPS

A basic single-phase UPS is shown in figure 17.48. A key safety objective is to retain the supply neutral
at both the supply input and the ac output, without resorting to any from of isolating transformer.
Consequently, the input ac mains is half-wave rectified by diodes DR and DR . Boost converters on the
positive and negative groups ensure supply sinusoidal input current and unity power factor. The output
H-bridge (T1-T4) uses pwm and feedback control to produce a fixed frequency and magnitude output
(and ac mains phase synchronisation if required), which is filtered by an L-C filter. In the event of a loss
of the ac supply, the backup batteries, V+ and V -, provide energy to the boost converters, hence to the
output inverter. The battery backup voltage magnitude is much less than the ac supply magnitude and
diodes, DB and DB , isolate the batteries from the rectified ac supply voltage. The shown UPS has two
basic limitations that manufactures strive to overt.
771 Power Electronics

½ wave rectifier boost converter H-bridge inverter L-C filter

+
DR + + T3
L D
ac +
DB +
+ +
T C - T1 D1 D3 Lo
+
V
Co

N N o/p
- - - T2
V T C T4 D4 D2
+
- -
DB
- - -
DR L D

Figure 17.48. Single-phase uninterruptible power supply.

 If the battery is to be connected to neutral, then two batteries are necessary. Proprietary
attempts using only one battery involve circuit complications and limitations. At best, with one
battery, it is one forward biased diode voltage drop from neutral.
 Because the batteries supplies are not isolated during normal operation, during part of the
mains cycle near zero voltage, the batteries alternately provide energy. This decreases their
lifetime and necessitates more complicated trickle charge circuits. The input current is also
distorted at the 0V crossover. Replacement of the blocking diodes D B by switches involves
complexity and battery backup operation requires detection and is not fail safe.

DB

Figure 17.49. Three-phase uninterruptible power supply.

17.5.2 Three-phase UPS

Figure 17.49 shows a basic three-phase UPS, used up to a few tens of kilowatts. The ac supply is
rectified and filtered. A forward converter controls the dc link voltage to just above the battery voltage
level. This dc voltage is boosted to a dc level such that after inversion it provides the required output
Chapter 17 DC to AC Inverters – Switched Mode 772

voltage magnitude. If the input ac fails or droops, the dc link power is provided by the battery via diode
DB. The output inverter is usually operational in a pwm mode, which allows precise frequency control,
voltage control, ac mains phase synchronisation, and minimisation of low frequency output harmonics.
With pwm control minimal filtering is required, which minimises the filter weight, cost, size, and losses. A
three-phase UPS can utilise third harmonic injection (17.1.4(iv)).
A three-phase boost input converter can be used to maintain sinusoidal ac supply input currents at unity
power factor.

17.6 Power filters

Voltage sourcing converter outputs

Power L-C filters are used to reduce harmonics or ripple from voltage sourcing outputs, namely
 the rectifier output (dc filter)
 the inverter output (ac filter).

L-C low-pass, second-order filters are shown in figures 17.45, 17.48, and 17.49. In figure 17.49, the L-C
smoothing filter at the rectifier output, filters the ac mains frequency components leaving dc. The same
type of filter is used in the inverter output to filter pwm harmonics, leaving the relative low-frequency
modulation frequency. In voltage sourcing outputs, the inductor is first (always in series) filter
component, whether first order L only, second order L-C, or higher, L-C-L, etc.
The L-C filter fundamental cut-off frequency is dependent on L, C, and the load impedance ZL
vo 1 1
  (17.100)

v i 1  j L Z  j C
1
L
 2 L
1   LC  j Z L

The simplest design approach is to assume a no-load condition, ZL → ∞, whence the filter cut-off

frequency is f o  1 / 2 LC .
As a first pass, determine the necessary inductance as follows. Based on the assumption that all the
source voltage is across the inductor because the capacitance tends to short the load (and maximum
di/dt occurs at zero load voltage for a purely resistive load), then the inductance must allow the
necessary maximum load di/dt at the maximum output frequency.
If the maximum fundamental current through the filter is
i t   2Iˆ sin ˆt  2Iˆ sin 2 fˆt
where fˆ  f o
then the current di/dt controlled by the filter inductance is
di
 2Iˆ ˆt  2 2 fˆ Iˆ cos 2 fˆt
ˆ cos 
dt
which has a maximum value at 0 radians, when cos ωt = 1. That is, using V = Ldi/dt rearranged
  
V V V
Lˆ    (17.101)
di dt 2Iˆ
ˆ 2 2 fˆ  Iˆ
 
Then f o  1 / 2 LC is used to calculate the necessary capacitance.
Frequency components below fo, including dc, are passed. Those components above fo are attenuated
by a second order fall-off in gain. Any frequency components inadvertently around the resonant
frequency, fo, will be amplified. For this reason, the filter may be damped with parallel connected R-C
snubbers.

Other constraints on the filter L, may include output dynamic response and rate of rise of fault current.

Example 17.6: L-C filter design, for voltage sourcing converter output

A 220V ±10% dc sourced H-bridge inverter, switching at 100kHz outputs 1Hz to 5kHz, 100A rms
maximum. Design an L-C filter to give maximum attenuation of the 100kHz carrier frequency.

Solution
The maximum current, 100A rms, at maximum frequency, 5kHz, is given by
i 2 5kHz  t   2  100A  sin2 5kHz  t
773 Power Electronics

Differentiating leads to the maximum di/dt experienced by the series filter inductor, specifically
ˆ  2 2  fˆ Iˆ
2Iˆ
 2 2   5kHz  100A = 4.44A/μs
Assuming the filter capacitor tends to short the load at 100kHz and zero load voltage occurs at
maximum di/dt, the source voltage is impressed across the filter inductor. Rearranging V = Ldi/dt, gives

V
Lˆ 
2 2 fˆ  Iˆ
200V
  45μH
4.44V/μs
The maximum usable inductance is 45μH up to 100kHz, rated at 100A rms. These requirements imply
using cores with an air gap to avoid saturation with a minimum volume. Amorphous strip C cores wound
with copper foil are suitable. Use half the inductance in each output pole for pseudo s/c protection.
In spite of the expected filter high resonance Q, a filter cut-off frequency equal to the maximum output
frequency of 5kHz can be used, provided output voltage feedback is used to compensate for the near
resonance effects. Using a 5kHz cut-off frequency gives maximum attenuation of the 100kHz carrier.
Using f o  1 / 2 LC gives
L
C 
2 f o 
2

45μH
  45.6nF  47nF
2 5kHz 
2

The capacitor requirements include low resistance, implying metallised polypropylene. The voltage
rating is related to the maximum rms voltage associated with a 220V squarewave, which is 4×220/√2×π
= 198V rms at 5kHz. Given modulation is used, 220V ac is conservative. A double metallised
polypropylene capacitor should have an adequate dv/dt rating, hence 100kHz ripple current rating.
♣

Current sourcing converter outputs

In current sourcing outputs, as in figure 17.30, the filter capacitor is first (always in shunt) filter
component, whether first order C only, second order C-L, or higher, C-L-C, etc. The shunt C capacitance
is based on the maximum output voltage (dv/dt) requirement of the converter and i  C dv/dt .
Other constraints on the filter C, may include output dynamic response and rate of rise of fault voltage.

Reading list

See chapter 15 reading list.

Hart, D.W., Introduction to Power Electronics,

Prentice-Hall, Inc, 1994.

Mohan, N., Power Electronics, 3rd Edition,

Wiley International, 2003.

Problems

17.1. The inverter in figure 17.7 is supplied from a 340 V dc source. The load has a resistance of 10Ω
and an inductance of 10mH. The basic operating frequency is 50 Hz, with three notches per half
cycle giving half the maximum output, similar to that shown in figure 17.14.
Determine the load current waveform over the first two cycles and determine the power
delivered to the load based on the current waveform of the final half cycle.

17.2. The inverter and load in problem 17.1 are controlled so as to eliminate the third and fifth
harmonics in the output voltage.
Determine the load current waveform over the first two cycles and the power delivered to the
load based on the current waveform of the last half cycle.
Chapter 17 DC to AC Inverters – Switched Mode 774

17.3. Output voltage harmonic reduction can be achieved by employing multiphase, selected notching
modulation control on a three-phase bridge as discussed in 17.1.4. An output as in figure 17.15b
with α1 = 16.3° and β1 = 22.1° eliminates the 5 th and 7 th harmonics.
Determine the fundamental voltage output component and compare it with that of a square
wave. Determine the output rms voltage.

17.4. With the aid of figure 17.12 determine the line-to-neutral and line-to-line output voltage of a dc to
three-phase inverter employing 120° device conduction.
Calculate the interphase:
i. mean half-cycle voltage
ii. rms voltage
iii. rms voltage of the fundamental.

17.5. The three-phase inverter bridge in figure 17.4 has a 600V dc rail and a 10Ω per phase load. For
180° and 120° conduction calculate:
i. the rms phase current
ii. the power delivered to the load
iii. the switch rms current.
[24.5 A, 18 kW, 17.3 A; 28.3 A, 24 kW, 14.15 A]

17.6 A single-phase square-wave inverter is supplied from a 340V dc source and the load is a 17Ω
resistor. Determine switch average and rms current ratings. What power is delivered to the
load?

17.7 A single-phase square-wave inverter is supplied from a 340V dc source and the series R-L load
is a 20Ω resistor and L=20mH. Determine:
i. an expression for the load current, hence the maximum switch current
ii. rms load current
iii. average and rms switch current
iv. maximum switch voltage
v. average source current, hence power delivered to the load
vi. load current total harmonic distortion.

17.8. Compare the phase and line voltage spectrum of a 50Hz modulation process using 2.1kHz saw-
tooth and triangular carriers.

Triangular carrier, 2.1kHz

Saw-tooth carrier, 2.1kHz