Introduction
Integrated circuits (ICs) must operate across environments ranging from milli-kelvin cryogenic labs to
harsh high-temperature settings (downhole oil wells, aerospace engines). Temperature dramatically
alters semiconductor physics – affecting carrier concentration, mobility, and bandgap – so device design
and fabrication are tailored for each regime. For example, silicon devices at room temperature follow
conventional CMOS scaling, but at cryogenic temperatures steep subthreshold slopes and carrier freeze-
out emerge 1 2 , whereas at high temperature standard Si leaks excessive current 3 and must often
be replaced by wide-bandgap (WBG) devices (SiC, GaN, β-Ga₂O₃) that tolerate extreme heat 4 5 . This
review surveys fundamental and advanced device structures (e.g. planar CMOS, FinFET, JFET, HEMT) and
material systems (Si, SiC, GaN, β-Ga₂O₃) developed for cryogenic, ambient, and high-T ICs. We discuss
how temperature affects key electrical parameters (leakage, mobility, threshold, subthreshold swing,
etc.) and reliability, and we highlight packaging and integration methods that enable ultra-low-power
cryo operation and high-temperature stability.
Temperature Effects on Device Physics
Semiconductor behavior is highly temperature-dependent. As temperature decreases, thermal energy
(~kT) shrinks, reducing intrinsic carrier concentration and steepening the MOSFET subthreshold swing
(ideal SS ≈ (kT/q)·ln(10) becomes very small) 1 . In practice, cryogenic CMOS exhibits ultra-steep SS
and very low leakage, enabling extremely low-power switching 1 6 . For instance, Saligram et al.
report that lowering temperature can be used as a “knob” to steepen the subthreshold slope, allowing
supply voltage reduction without loss of speed 6 . However, dopant ions freeze out at low T: threshold
voltages rise (often nearly linearly with decreasing T) because fewer carriers are available in the channel
2 . This impurity freeze-out (notable below ~150 K in Si) can also cause anomalous “kink” effects
from floating substrates or LDD regions 2 1 . Meanwhile, low-T lattice scattering is suppressed so
carrier mobilities increase and series resistances drop 7 . For example, measured MOSFET series and
contact resistances shrink dramatically at 4 K (Al metallization resistance falls ~3×), enhancing drive
current and lowering noise 7 .
As temperature increases, thermal generation of carriers and phonon scattering both rise. In MOSFETs,
higher T reduces the bandgap and increases intrinsic carriers, so the threshold voltage decreases and
subthreshold leakage grows exponentially (leakage roughly doubles every +10 °C in standard Si
processes) 3 . The subthreshold swing degrades (kT term increases), and mobility falls (µ ∼T⁻m with
m~1–2), so on-current drops. Increased lattice vibrations and thermionic emission also raise off-state
currents and gate leakage. Interconnects and contacts face electromigration and metal diffusion at high T
8 . Overall, standard Si CMOS becomes unreliable much beyond ~150 °C without special measures 3 .
In contrast, wide-bandgap semiconductors (e.g. SiC, GaN, Ga₂O₃) have much higher bandgaps (2.3–4.8 eV)
and intrinsic carrier freeze-out that suppresses leakage up to ~300–600 °C 4 9 . Table 1 (below)
summarizes typical temperature trends for key parameters in Si CMOS:
· Leakage current (I_off): Increases sharply with T due to thermally activated carriers (I_off ∝ e^(-
E_gap/2kT)); roughly doubles per 10 °C 3 .
· Mobility (μ): Drops at high T (phonon scattering ∼T^-m) but rises at low T until impurity scattering
limits it 7 .
1
· Threshold voltage (V_th): Decreases with increasing T (weaker bandgap, more carriers) and
increases at low T (freeze-out) 2 3 .
· Subthreshold slope (SS): Proportional to kT; approaches zero at cryo (ideal) improving
switching, but saturates above T~0 K due to interface traps and incomplete ionization 1 2 .
Cryogenic IC Technology (≈4–200 K)
Cryogenic electronics are emerging for quantum computing, space instruments, and scientific sensors
10 11 . The goal is ultra-low-power, low-noise operation in a cold environment where cooling power
is severely limited. Standard Si CMOS (bulk, SOI, FDSOI) can be used at cryo: experiments in 28 nm bulk
CMOS and 22 nm FDSOI chips have demonstrated functioning memories and analog circuits at ~4 K 12 .
Advanced device structures like FinFETs are similarly promising at low T, offering tight gate control (steep
SS) and high drive with minimal leakage. Key cryo-device features:
- Steep Subthreshold Slope: At 4 K, a MOSFET’s SS can be orders of magnitude better than at 300 K,
enabling operation at near-threshold voltages 6 1 . This significantly lowers dynamic energy
(E∼C·V²) and leakage power.
- Threshold Tuning: Because V_th rises at cryo (due to dopant freeze-out) 2 , processes must engineer
doping or use body bias to set appropriate V_th. Optimal threshold engineering can recover drive current
even as T→0 6 .
- Low Resistances: Metal films and heavily doped regions become more conductive at 4 K 7 , reducing
noise and IR drops. For example, Al metallization resistance falls to ≈⅓ its 300 K value 7 .
- Material Choices: Silicon remains dominant, but III-V HEMTs (e.g. GaAs or InP pHEMTs) are often used
for cryogenic low-noise amplifiers in radio astronomy or qubit readout. Cryogenic GaAs pHEMTs have
been characterized at 15–77 K showing higher transconductance and slightly lower current density 13 ;
such devices underpin LNAs reaching 5 K noise figures 14 . Moreover, emerging approaches use
superconductors (Nb) or 2D electron gas (e.g. InGaAs HEMTs) hybrid-integrated with Si to cut power
consumption massively 15 .
Cryogenic packaging: Because mismatches in thermal contraction can crack devices, special packaging
is needed. Commercial solder alloys and materials generally behave well down to 4 K: Pb-rich Sn–Pb
solder or indium solder remain ductile at cryo 16 , and common PCB substrates and insulators (FR-4,
some epoxies, NP0 ceramic capacitors and thin-film resistors) are cryo-compatible 17 16 . Wire bonds
and flex cables using materials like Cu or BeCu can handle repeated cooling cycles. Cryogenic IC
packages often use minimal potting (vacuum or open capping) to avoid trapped gases. For high
integration, 3D chiplets or through-silicon vias are being explored to place control ASICs next to quantum
chips 11 .
Ultra-Low-Power Innovations: In cryo-CMOS design, leveraging the physics above leads to new
architectures. Designs use near-threshold logic and aggressive voltage scaling; Saligram et al. show
supply voltages can drop with no speed loss due to steeper SS 6 . Cryo-specific circuits include low-
power RF oscillators and LNAs optimized for 4 K, as demonstrated in recent experiments 18 19 . For
large-scale qubit control, it’s imperative to minimize dissipation: Nature Communications recently
reported III-V/BiFET and superconducting cryogenic circuits on silicon achieving over 10× lower power
at 4 K than equivalent CMOS designs 15 . These include extremely fast (>600 GHz f_T) MESFETs and cryo-
compatible comparators that consume nanowatts per gate. Overall, ultra-low-power cryo ICs exploit
steep subthreshold swing and low noise to function with only microwatts of power, enabling thousands
of qubits per cryostat 15 11 .
2
Ambient-Temperature (Consumer/Automotive) IC Technology
At room temperature (≈−55 °C to +125 °C for industrial/automotive), silicon CMOS dominates. Modern
logic is built on FinFET and Gate-All-Around FETs (sub-10 nm nodes) to suppress leakage and variability.
FinFETs’ 3D gate geometry provides excellent electrostatic control and lower subthreshold leakage than
planar MOSFETs 4 20 . Standard processes use high-k/metal-gate dielectrics, strained silicon channels,
and heavy doping to tune thresholds; these techniques balance on-current against leakage at room T. By
design, typical ICs must tolerate up to ~125 °C (with commercial Si up to ~150 °C). In conventional silicon,
leakage roughly doubles every +10 °C 3 , so industrial grades limit junction temperature to ~150 °C. To
push beyond this, specialized silicon (SOI) or wide-bandgap devices are used (see below).
Packaging and Integration: Ambient ICs use conventional package types (plastic QFP, BGA, etc.) on FR-4
PCBs, with Sn–Ag–Cu solders (melting ~217 °C) and polymer passivation. Heterogeneous integration
(chiplets, 2.5D/3D stacks) is increasingly used for power and RF. For example, hybrid bonding (Cu–Cu
interconnects) and extreme wafer thinning are advancing power ICs: thinned chips (<10 µm) with copper
backside metallization dramatically improve heat dissipation and reduce parasitics 21 . These
techniques allow combining Si and WBG dies in a single package, essential for next-generation
electrification 22 21 .
High-Temperature IC Technology (>150 °C)
In extreme environments, silicon yields to wide-bandgap semiconductors with higher thermal budgets.
Key material systems and devices include:
· Silicon Carbide (SiC): 4H–SiC has a bandgap of ~3.26 eV and thermal conductivity >300 W/mK,
allowing MOSFETs and JFETs rated for 600–1700 V to operate reliably up to ~300 °C. Commercial
discrete SiC MOSFETs (1200 V, 1700 V) are specified to ~175 °C, and research shows they can
survive beyond 250 °C under bias 23 . SiC’s superior breakdown field and thermal conductivity
(see Table 1) enable high-voltage switching with low on-resistance 23 . For integrated circuits,
Silicon-on-Insulator (SOI) CMOS is often used for SiC-based systems: e.g. Honeywell developed
SOI CMOS ASICs (A/D converters, FPGAs, op-amps) rated to 225 °C ambient 24 . The SOI structure,
with reduced junction volume, inherently suppresses leakage at high T – experiments show two
orders-of-magnitude lower leakage at 225 °C compared to bulk Si 20 .
· Gallium Nitride (GaN): AlGaN/GaN HEMTs have a bandgap ~3.4 eV and excellent electron mobility
(∼1500–2000 cm²/V·s). They are widely used in RF power amplifiers (5G, radar) and power
conversion. GaN HEMTs maintain gain up to ~200 °C, and GaN-on-SiC integrated circuits (MMICs)
have been demonstrated at 250–300 °C. However, GaN IC reliability can be challenging: self-
heating is severe in GaN (due to lateral geometry), and traps can cause long-term threshold shifts
under RF stress 25 . Recent studies of GaN HEMTs under high-T RF stress report gradual
degradation of current and transconductance above 100 °C 26 . Ongoing research targets
improved gate dielectrics and packaging to mitigate hot-carrier and trapping effects in GaN
devices.
· Gallium Oxide (β-Ga₂O₃): An ultrawide-bandgap (≈4.8 eV) semiconductor with critical field
≈8 MV/cm 5 . β-Ga₂O₃ diodes and MOSFETs promise extremely high blocking voltages (multi-kV)
and operation at >500 °C. Its mobility (∼100–300 cm²/V·s when doped) is lower than GaN/SiC, but
Ga₂O₃ can be grown in bulk by melt methods at low cost 5 . A major challenge is high-
temperature stability of contacts: typical Ti/Au ohmic contacts dissolve above ~300 °C. Recent
work by Callahan et al. demonstrates ultrathin Ti/Au contacts that fully oxidize into stable TiO₂,
3
achieving low-resistance ohmic behavior and continuous operation at 500–600 °C 27 . This opens
the door to practical Ga₂O₃ power devices for the hottest environments.
· Silicon-on-Insulator (SOI) CMOS: As noted, SOI CMOS is often optimized for wide temperature
range. The Deep-Trek program’s SOI process runs to 225 °C, and NASA has tested SOI FPGAs and
ADCs to 240 °C. SOI’s insulating substrate also resists single-event radiation – useful in high-
altitude or space.
· Other Devices: Silicon-based JFETs and bipolar transistors have been used in some high-T
designs (e.g. SiC JFETs for millimeter-wave amplifiers). In some cases, specialized packaging for
thermal expansion matching (see below) is as important as the semiconductor itself.
High-Temperature Packaging and Integration
Packaging for extreme heat must address thermal expansion and material limits. Conventional PCB
materials (FR-4 epoxy) and solders (Sn–Pb, Sn–Ag–Cu) fail above ~150–200 °C. High-T systems use
ceramic substrates (e.g. AlN, Si₃N₄), polyimide PCBs, or even metal carriers. NASA Glenn’s MEMS-DCA
approach bonds SiC chips to SiC ceramic substrates with no wire bonds, using CTE-matched thick pins
and glass-free seals 28 . This “glueless” package withstands 600 °C by eliminating CTE mismatch: the
top and bottom substrates are both SiC (similar expansion to the devices), significantly reducing stress
28 . Analog Devices notes that hermetic sealing and matched-coefficient materials can double reliable
operating temperature (to ∼600 °C vs. ∼300 °C conventional) 29 28 .
Key packaging points for high T:
- Interconnects: Wire bonds often fail above ~200 °C. Direct-bonded copper (DBC) or ribbon bonds of
high-melting alloys (Au, Pt–Au) are used. Flip-chip or through-silicon vias with high-T underfill can bypass
wires.
- Substrate and Housing: Ceramics or high-expansion plastic (PPS, LCP) are used. Die attach adhesives
must not outgas or creep – silver-filled epoxies with >300 °C rating are common.
- Thermal Management: Heat spreaders (diamond or CuW) and heat sinks are integrated into the
package. In some extreme cases (Venus lander electronics), chips are designed to dissipate minimal
power to stay below 460 °C.
For cryogenic packaging, the challenges are different. Parts become brittle and materials contract. As
noted, Pb–Sn and In solders, as well as many polyimides and epoxies, remain functional down to 4 K 16 .
Cryogenic packages often use hermetic metal cans or ceramic packaging to avoid trapped gas. Thermal
cycling tests (room↔4 K) are necessary; devices are often glued with cryo-compatible epoxy (e.g. cyanate
esters) and use flexible printed circuits or coax. A key advantage is that thermal expansion issues are
smaller (materials usually shrink rather than melt).
Reliability and Design Considerations
Temperature stresses can impact IC reliability. At cryo, carriers freeze out rather than diffuse, so long-
term reliability (electromigration, dielectric breakdown) is usually improved. However, device modeling
must account for charge trapping and “kink” effects 30 . SOI CMOS often mitigates substrate bias drift.
At high T, failure modes accelerate: electromigration in interconnects follows an Arrhenius law (time-to-
failure ∼exp(1/T)), so hotter operation dramatically shortens wire life 8 . Analog Devices notes that
metal-line electromigration and dielectric breakdown are key high-T concerns 8 . Hot electrons and
Fowler–Nordheim tunneling in the gate oxide become more severe, limiting device lifetime. Thus, high-T
4
IC design uses thicker gate oxides and wider channels (weaker drive) to improve reliability; biasing is
chosen to limit channel hot-spot heating.
For silicon CMOS, the data sheet often cites 125 °C max, but actual silicon chips can operate up to ~200 °C
in short bursts 3 . NASA and industry studies show that careful layout (large transistors, well spacing)
and ruggedization (SOI, thicker oxides) can extend life. Silicon carbide and GaN devices have higher
intrinsic limits, but still suffer from aging: e.g. SiC MOSFETs under high current can see threshold shifts
and bond-wire lift-off 31 . In one study, repeated short-circuit events in a SiC power MOSFET showed that
drain and gate leakage currents grow with each event, and the number of cycles to failure depends
strongly on case temperature 31 . This means high-T operation not only increases steady-state stress but
also reduces tolerance to spikes.
Emerging materials also have unique concerns: β-Ga₂O₃’s wide bandgap means junctions are very
sensitive to crystal defects, and its low thermal conductivity can cause self-heating. Therefore, packaging
for Ga₂O₃ often includes heat-spreading substrates (diamond or AlN) and graded buffer layers to reduce
dislocations. Reliability research is active: for example, long-term biasing of GaN HEMTs at 200 °C has
been studied to model time-dependent breakdown 32 , and Ga₂O₃ devices require novel gate dielectrics
to avoid threshold shift at high T.
Conclusion
The principles of IC technology span a wide thermal landscape. At cryogenic temperatures, specialized
semiconductor processes exploit steep subthreshold slopes and low noise for ultra-low-power operation
6 15 , but must contend with dopant freeze-out and unconventional device physics 2 . At room
temperature, silicon CMOS (including FinFET and future gate-all-around) provides the backbone of
digital and analog ICs, with design focus on leakage control and power efficiency under ∼125 °C ambient.
At high temperatures, wide-bandgap materials (SiC, GaN, β-Ga₂O₃) and SOI architectures are tailored to
sustain reliable function in extreme heat 4 9 . In all cases, packaging and integration are crucial:
matched-CTE substrates, high-temperature interconnects, and hybrid bonding ensure that devices
survive the thermal environment 28 16 . Innovations continue to push these limits – for example, recent
Ga₂O₃ power MOSFETs with stabilized ohmic contacts operate beyond 500 °C 27 , while cryogenic mixed-
signal ASICs approach nanowatt power budgets 15 .
Sources: Foundational semiconductor texts and recent literature highlight these trends. Key reviews and
studies span classic device physics and the latest papers (2023–2025) on cryogenic CMOS 6 2 15 ,
wide-bandgap materials 4 9 5 , and high-reliability packaging 28 3 , among others. A
representative sampling of this literature is cited above.
1 More Compelling Device Physics Based Insights over Subthreshold Slope (Swing) Saturation Near
Cryogenic Temperatures for n-FET and p-FET
[Link]
saturation-near-cryogenic-temperatures-for-n-fet-and-p-fet
2 7 30 [1811.11497] Cryogenic Characerization and Modeling of Standard CMOS down to Liquid
Helium Temperature for Quantum Computing
[Link]
3 8 High-Temperature Electronics Pose Design and Reliability Challenges | Analog Devices
[Link]
5
4 21 22 Electrifying Everything: Power Moves Toward ICs
[Link]
5 Comparison of the physical properties of Si, GaN, SiC, and β-Ga 2 O 3... | Download Table
[Link]
semiconductor-5_tbl1_327759061
6 12 Researching | The future is frozen: cryogenic CMOS for high-performance computing
[Link]
9 27 Ultrathin stable Ohmic contacts for high-temperature operation of β-Ga2O3 devices
[Link]
10 18 19 (PDF) Cryo-CMOS Circuits and Systems for Quantum Computing Applications
[Link]
CMOS_Circuits_and_Systems_for_Quantum_Computing_Applications
11 15 Cryogenic III-V and Nb electronics integrated on silicon for large-scale quantum computing
platforms | Nature Communications
[Link]
error=cookies_not_supported&code=72c1366a-4d85-4d9c-9036-1729fd211c54
13 14 Cryogenic MMIC Low-Noise Amplifiers for Radio Telescope Applications
[Link]
16 17 Review of Power Electronics Components at Cryogenic Temperatures - PMC
[Link]
20 24 SOI CMOS for Extreme Temperature Applications
[Link]
[Link]
23 31 Paper Title (use style: paper title)
[Link]
25 26 32 Electrical Properties and Reliability of AlGaN/GaN High Electron Mobility Transistor under RF
Overdrive Stress at High Temperature
[Link]
28 29 Packaging for SiC Sensors and Electronics | T2 Portal
[Link]