ICEP-IAAC 2015 Proceedings WEl-2
Ultra-thin Line Embedded Substrate Manufacturing
for 2.1DI2.5D SiP Application
Yu-Hua Chen, Shyh-Lian Cheng, Dyi-Chung Hu, Tzvy-Jang Tseng
Unimicron Technology Corp.
No. 290, Chung-Lun Village, Hsin-Feng, Hsinchu, Taiwan, 304
Abstract-For high density interconnection IC packages of cannot be matched by current laminate substrate technology.
the future, the outlook is for thinner packages with higher But the challenge of Si interposer is the high cost. We have
routing densities_ With that, fine line substrate technology developed an ultra-thin line embedded substrate for 2. 1D/2.5D
becomes critical_ Current organic substrates are limited to
SiP application.
line/space larger than 8/8 [Link] for by conventional semi-additive
There are two types of approach to meet the requirement
plating (SAP) technology_ It may have yield loss issue due to
of line/space less than 5/5f,lm in the organic substrate. One is
weak adhesion of line/space less than 5/5 [Link], especially in long
distance line_ But the impact of weak adhesion of fine line is very
the conventional Semi-Additive Process (SAP) and another is
small in line embedded (LE) substrate because of it is in laser embedded technology. The advantage of SAP is the good
embedded structure. Line embedded is made by laser patterning compatibility with current process but the problem is yield and
of dielectric. Dry film material, chemicals for lithography like reliability issue for narrow copper trace on the dielectric
developer, and stripper are not needed. The circuits are surface. From the current status, line/space of 8/8 f1 m will be
embedded, and capable of stereo copper features. It can cover FC,
the process limitation of SAP and 5/5 f1 m need to be further
CSP, CIS, coreless structures. Line embedded technology can
verified for HVM.
provide better electric performance with lower variation of
trench width/depth. It can form fine pitch trench line/space less Another solution is laser embedded (LE) technology with
than 5/5 [Link]. It also has better design flexibility & reliability than the different structure as shown at Figure 1. LE technology is
SAP process. different from SAP includes ablation of trench by laser and
panel plating with electroplating copper and then removing
In this paper, we will discuss the key of the processes and copper above dielectric surface for formation of Cu pattern.
demonstrate the fabrication of fine line substrate in the coreless There are several advantages of laser embedded comparing to
process of build-up 5/5 [Link] line/space by adopting line embedded
SAP. First, the laser embedded substrate provides a flat
technology. Line embedded was made by laser direct ablation
surface after formation of pattern which is helpful for covering
(LDA) on organic build-up dielectric material. By using core as
a thinner solder mask with better uniformity of thickness. It
carrier and build-up dielectric material with finer filler size, the
can avoid the voids formation while filling molding compound.
coreless structure has demonstrated lower warpage and good
trench capability. Laser ablation process capability also shows Second, the laser embedded substrate not only allows the
excellent trench depth control. In order to get better copper design of pad-less via to reduce both package size and format
thickness uniformity, novel uniform Cu plating technology on but also can put more traces near these vias as shown in Figure
trench, pad, and via has development. Low cost and uniform Cu l.
reduction process was also evaluated and developed. We also
evaluated the feasibility of separation after molding. Different
types of molding compounds are evaluated and good flatness
material is found.
Keywords-line embedded; laser direct ablation
I. INTRODUCTION
Today's packaging and assembly technologies are
challenged by a variety of new products requirement. They
include very small and thin outlines, several GHz operating
Figure I(b). Structure of substrate by SAP
frequencies, high power dissipation, and low production cost.
Panel level embedded substrate is one of the solutions for the Figure 1 Structure compmison of laser embedded and SAP technology
trend of electronic packaging development. In this study, several key technologies of laser embedded
Current organic substrates are limited to lines/space of are successfully integrated in the current substrate process. By
101lOf,lm and via size around 50f,lm. However, the the selection of the advanced dielectric film with a suitable
semiconductor with advance node needs fine line/space of 5/5 design as a test vehicle to verify the feasibility of laser
or 3/3 and even 2/2 f,lm in the future. Si Interposer provides a embedded technology with line/space of 717f,lm and 5/5f,lm
high density interconnection with fine line and small via that design.
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ICEP-IAAC 2015 Proceedings WEl-2
II. PROCESS FLOW OF EMBEDDED TRACE size and ablated depth not on pattern features. Excimer laser
SUBSTRATE system is operated at typical 248nm or 308nm wavelengths
which can provide higher resolution and better depth control.
The general process flow for laser embedded subsrtate is
In this study, 308nm wavelength was used for excimer
shown in Figure 2_ The inner-layer is formed and then ABF
laser system and the resolution of designed in features was ±
type dielectric material is laminated_ In this test vehicle, the
thickness of ABF-type dieletric material with finer filler was 1f.-Lm and registration is better than 10/lm. Figure 3 shows an
50/lm. Laser via drilling was used for forming the blind with example of excimer laser system ablated signals paths with
topibottom via diameters of 65/50/lm. After that excimer laser 5/5/lm line/space in dielectric film.
(/� I) l
was used to ablate the trench patterns of line/space with 5/5/lm.
After via and patterns formed by laser ablation, conventional ( I
substrate processes including de-smear, electro-less seed layer ( I I (
( II'�
I
and electroplating copper was used for the circuit patterns. In
this study, low cost and uniform Cu reduction technology was
I 1 I I I / : /
j' I I I
/
used to reomve the copper above dielectric to form the circiuit.
"',, \1 . , ::"", 1 1 I
�
("
I r-
Inner-Layer formation
ABF Lamination I Blind via formation
Repeat for multi-layer deielectric build-up
----------- ------------------------------------------------------\
H
:
Excimer laser t-+ DeSO'lear I
JI
150kVl�3mn'lll:2S SE 211
, IS
I ..I. "',,,
[60Oum
l'SOkV!l�m):I�OkSE 2I1er.?01
i
\
. j
I:
: __ L AOI Micro etching Cu Reduction Cu Plating : Figure 3 Excimer laser system ablated signals paths with 5/51lm
line/space in dielectric film.
\.. _--------- ----------------------------------------------------- -)
Solder mask formation
Surface finishing
Item Unit BF-A BF-B
Singulation
Tg(byDMA) °
c 200 220
Tg(by TMA) °
c 1 68 1 95
Figw'e 2 Process Flow for Laser Embedded Substrate CTE-al ppmtC 40 30
Tensile Modulus(R.T.) GPa 6 8
The process from ABF-type dieletric material lamination to Tensile Modulus(250 degC) GPa 0.2 0.2
AOI can be repeated for multi-layer built-up. Finally solder Dielectric constant (lG Hz) 3.2 3.3
mask was covered and pad opening was formed followed by Dielectric Dissipation Factor (lG Hz) 0.0 1 2 0.0 1 1
the surface finishing using ENEPIG were performed. Moisture Absorption
wt% 0.9 0.8
(0.2t) (PCT-2hrI1 2 1 °C )
There were several important items should be addressed in
this study. Table 1 Propelty of build-up dielectlic film
1. The total thickness variation (TTV) of panel. The The main issue of laser embedded technology is the trench
depth of focus was an important factor of laser to shape of V-shape instead of U-shape from Figure 4.
control the ablation depth. Large TTV will make laser
out the focus and cause higher depth variation.
". �-�-----
--
2. The copper thickness uniformity of electrplating will I
I
impact the yield. Bad Cu plating uniformity will cause
serious short issue after Cu reduction process.
_
I t.I
___
IS
_
II JJ
LL$ = 55
BF-A (max.2Ilm) J
3. Low cost and uniform Cu reduction is the key process
for removing the copper above the dielectric surface
for forming circuit pattern. -- .
, "T
I
t
III. EXPERIMENT -���
BF-B (max.O.5Ilm)
A. Excimer Laser Technology LDA Results
The laser embedded technology is predicated upon the
Figw'e 4 Fine capable compmison of build-up dielectJic film
use of a laser to create trenches within the dielectric material
for subsequent signal formation. In the past, multiple laser Adhesion of the subsequent copper layer is very important
system have been tried and evaluated, including excimer laser in the laser embedded process sequence but the absolute
and UV YAG laser systems. In general, UV YAG laser has adhesion value can be less because of increased surface area
several benefits such as providing a broad choice of dielectric (three sides are attached to the dielectric). In general, the
material, allowing for a maskless ablation process, facilitating minimum required adhesion, as measured by surface peel
the ablation of trenches and blind microvias simultaneously. strength, is probably 6 N/cm for the conventional Semi
Additive Process (SAP), because only one side of the
But the throughput will slow down as the pattern has larger
conductor is attached to the dielectric. But for laser embedded
features. On the other hand, the throughput of excimer laser
process, the minimum peel strength requirement is in the order
systems is independent of pattern features owing to the pattern
of 3�5 N/cm. De-smear is applied in order to remove laser
being defined by mask. The throughput is depended on body
ablation debris and roughen the dielectric material surface
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ICEP-IAAC 2015 Proceedings WEl-2
uniformly to provide enough adhesion of the subsequently to ensure complete copper removal across the entire panel.
applied electro-less copper layer, but also impact the trench Copper dishing is defined as the difference in height between
definition if the parameter is too strong_ The path finding of the center and edge of the copper trace. This dishing value will
creating maximum adhesion value with minimum roughness impact the trace thickness. The quality of Cu reduction is not
will be a challenge especially for line/space less than S/[Link]. dependent on the condition of Cu reduction system but also
the quality of polished panel such as flatness of dielectric
B. Electro Copper Plating Process surface after lamination and the thickness variation of
The electro copper plating is the utmost importance and electroplating copper above dielectric surface.
difficulty for laser embedded circuit process. The difference
from conventional Semi-Additive Process is the panel plating Dishing
Erosion
with requiring uniform copper thickness above the dielectric
surface but different start point as shown in Figure S.
In this study, the horizontal plating has been adopted for
electroplating copper. Superior results have been obtained by
adopting Via2 chemistry by sophisticated pulse and the latest
technology including several individually controlled anodes
combined with optimized foil transportation systems, modified
Figure 6 Definition of dishing and erosion
electrolyte flow control to optimize surface distribution. The
range of electroplating copper thickness above dielectric IV. RESULTS
surface was higher than 8 [Link] and in the average of 10 [Link]. But • Warpage control
this result depends on the copper filling ratio and the pattern The process flow of test vehicle in this study was shown at
features. In general, higher filling ratio and bad uniform of Figure 7.
layout will cause higher electroplating copper thickness
Core
variation. .SAP
L2
L2
Cu remove
_SIR & NiJAu
.SF lamination
{
carrier . t=====:j
...J..
_ Finished board
Via drilling
...a IExcimer laser - imolding
Electro-less I Electroplating leu plating
Se arate after moldin
Figure 7 Process flow for test vehicle by laser embedded technology
Although the structure of laser embedded substrate is
Figure 5Diagram of electro-less/electroplating symmetrical during the built-up process. But the final product
after package is an asymmetrical structure and might be
warped due to the stress generated during the lamination of
C. Low cost and Uniform Cu Reduction Process
dielectrics. In this study, the structure of test vehicle used in
After electroplating copper in average of lOf.!m, the this study was shown in Figure 8. After built up, two different
thickness of copper above dielectric surface is higher than types of molding compound were evaluated without die attach
[Link]. It means if ablates ISf.!m of depth in average and only for the laser embedded substrate. The property of molding
etching process is applied to remove the copper above compound was shown at Table 2. Figure 9 shows low warpage
dielectric surface. Then the minimum copper thickness of the below 1.S mm after molding and departing.
trench will be below [Link] if the ablation depth range is about
[Link] and the trace width will be one-third of design value. It is �
why we developed low cost and uniform Cu reduction
technology to remove copper above dielectric surface to form
pattern circuits.
Low cost and uniform Cu reduction technology is the
process used to remove copper above dielectric surface. In
principle, it is combination of mechanical and chemical
treatment.
Figure 8 Structure of test vehicle
There are two phenomena -dishing and erosion - lead to
deviations from the ideal case depicted in Figure 6 during the
Cu reduction of patterned copper panel. In fact, copper dishing
and erosion occur during the over treatment which is required
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ICEP-IAAC 2015 Proceedings WEl-2
Type MC-S MC-A The laser embedded circuit patterns and x-section of
Item Unit
717/lm was shown in Figure 10. The trace width was about
al-X,Y ppm 13 6.5
a2-X,Y ppm 45 20 7.2/lm and about II/lm copper thickness in average.
Tg(TMA) °c 140 I55(DMA)
Yowlg'S Modulus(23°C) GPa 18.7 5.5
Breaking Strength(25'C) MPa 2.7
F\ex1ll1l1Strength(25°C) Nlmm' 145
F\ex1ll1lIStrength(260°C) Nlmm' 30
F\ex1ll1l1 Modulus(25°C) GPa 14.5
F\ex1ll1l1 Modulus(260°C) GPa 1000
Si02 AmolUll wt% 84
l11ickness fun 100 100
Warpage afier departing in Strip mm < 1.5 <3
Warpage direction - Crying Smiling
Figure II Laser embedded circuit pattellls and x-section of 5/511tn
M old ing compound
The laser embedded circuit patterns and x-section of
Smiling Crying
5/5/lm was shown at Figure 1 1. The trace width was about
Substrate
5.0/lm and about 9.0/lm copper thickness in average. The
Table 2 Property of molding compound dishing value was controller below O.5um and no significant
erosion was found after Cu reduction.
V. CONCLUSION
MC-S
In this study, two sets of dielectric film of different filler
I
� - , size were identified for a successful evaluation of line/space in
717/lm and 5/5/lm respectively. The integration of excimer
laser, electroplating and Cu reduction in laser embedded
technology was successfully demonstrated. By good properties
MC-A combination of dielectric film and carrier, the warpage of
------- - finished board after molding without die was controlled below
1.5 mm. This achievement also demonstrated the foundation
Figure 9 Top view after moldingldepmting
of the feasibility of line/space less than 5/5/lm by laser
• Laser embedded trace formation embedded technology in the future .
ACKNOWLEDGMENT
The authors would like to thank Unimicron's NED LE
team for their efforts in this study, also the support from
Unimicron's management team.
REFERENCES
[ I] Ron Huemoeller, "Via' - Laser Embedded Conductor Technology", in
2008 The 3rd IMPACT and 10th EMAP Joint Conference.
[2] Ron Huemoeller , Sukianto Rusli, Steve Chiang , Tsung Yuan Chen,
Dave Baron, Lutz Brandt and Bellld Roelfs," UNVEILING THE NEXT
GENERATION IN SUBSTRATE TECHNOLOGY", in Pan Pacific
Symposium 2007 Proceedings
Figure 10 Laser embedded circuit pattellls and x-section of 717I11ll
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