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VLSI Physical Design Engineer Resume

Surabhi R is a Bachelor of Engineering graduate with a certification in Physical Design Engineering, seeking opportunities in VLSI PD Engineering. She has hands-on experience in physical design flow, particularly with 28nm technology, and is proficient in tools like ICC. Her skills include digital electronics, CMOS fundamentals, VHDL/Verilog, and C programming, along with a strong academic background and experience in various design responsibilities.

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himani
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16 views2 pages

VLSI Physical Design Engineer Resume

Surabhi R is a Bachelor of Engineering graduate with a certification in Physical Design Engineering, seeking opportunities in VLSI PD Engineering. She has hands-on experience in physical design flow, particularly with 28nm technology, and is proficient in tools like ICC. Her skills include digital electronics, CMOS fundamentals, VHDL/Verilog, and C programming, along with a strong academic background and experience in various design responsibilities.

Uploaded by

himani
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Surabhi R

Bachelor of Engineering with Certification in PHYSICAL DESIGN


ENGINEERING

Phone:+91 8660388378, +91 9738989084 Email: surabhir.8793@[Link]


Bangalore, Karnataka.

OBJECTIVE

Willing to work in a national or multinational organization relating to VLSI PD Engineering


field where success comes through hard work, creativity & devotion to duty.

SKILL SUMMARY

 Good knowledge of Digital Electronics.


 Good Knowledge of CMOS Fundamentals.
 Good knowledge of VHDL/Verilog.
 Good knowledge on ASIC and PD physical design flow.
 Good knowledge of C programming.

CAREER SUMMARY

 Completed professional course on Physical Design Engineering in January 2018.


 Hands On experience in PD flow equivalent to 2 years of experience in industry.

EXPERIENCE DETAILS

 Experience in PnR ICC tool.


 Experience in Block level Floorplanning, Hierarchical Design, Placement, CTS, Power
distribution, Routing, and fundamentals of STA.
 Handled Physical Design responsibilities for 28nm technology including Floorplan, Placement, CTS,
fundamentals of STA and Routing.

EDUCATION

 Bachelor of Engineering from Visvesvaraya Technological University (VTU) from Belgaum


With specialization in Electronics and Communication (EC) engineering, 2015, with 70%
aggregate
 Pre-University in PCMC , Board of Karnataka, 2011, with 88.33%.
 X std from Central Board, Delhi, 2009, (93.4%)

Job Profile

Organization: TechMahindra

Project 1: Physical Design


 Duration: August 2015 to September 2016
 Designation: Physical Design Engineer
 Client : SanDisk

Objective : To do the FloorPlanning, PowerPlanning, Placement, CTS, Routing, Design signoff,


Generating GDS II for block level.

 Tools : ICC
 No. of Clocks : 2
 Macro count : 24
 Frequency : 125 MHz
 Utilization : 70%
 Technology / Layers : 28nm / 9 Metal Layers

Role:
 Floor Plan, Power Plan, Placement.
 Timing Analysis, CTS, Detail Routing.
 To observe the relation between core utilization, wire length and number of metal layers

Hobbies and Extra curricular

 Playing Carrom and Chess in leisure.


 Swimming and playing badminton.

PERSONAL DETAILS

Father’s Name : Surabhi R


Address : #1154, 1st floor, 6th main, 4the cross, DC Halli, BTM 4th stage,
Bengaluru
Languages Known : English, Hindi, and Kannada
Date of Birth : 8th July 1993

DECLARATION

I hereby declare that the above information is true to the best of my knowledge and belief.

Yours Faithfully,
Surabhi R

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