PUDI ASHISH Mail: ashishpudi4@gmail.
com
Ph. No: 9003696477, 8897169854.
OBJECTIVE:
To become a successful professional by honing my skills and to work in an innovative and competitive environment
for utilizing my skills to their full potential. Committed to excel in whatever I do and passionate about achieving
results that exceed expectations.
EDUCATION:
May 2017 - [Link] (VLSI – Design), Vellore Institute Of Technology Vellore, 7.5 CGPA.
April 2014 - [Link] (Electronics and Instrumentation), Bapatla Engineering College, ANU Guntur, 75%.
April 2010 - Intermediate/12th (MPC), Sri Chaitanya Jr. College – Vizag, 87.8%.
May 2008 – 10th (SSC), Sri Sai Sarvani High School - Vizianagram, 86.00%.
SUMMARY OF CREDENTIALS:
In depth knowledge on Digital VLSI circuits and ASIC design, Perl and Tcl.
Comprehensive Knowledge on Verilog Coding, DFT, Analog Circuit Design.
Strong fundamentals over STA (Static Timing Analysis) analysis and Routing Algorithms for Backend Design.
TRAINING STATUS :
Having a 6months training experience of RTL Design and verification at Maven silicon Pvt Ltd, Having knowledge
on Digital design, Designing of FSM, Verilog coding, XST Tool. I have done project of Router 1x3 with HDL language
Verilog and HVL language SV by using with EDA tools Xilinx ISE and Aldec Riviera-PRO. In this project I have done
Architected the design Implemented RTL using Verilog HDL, Architected the class based verification environment
using system Verilog, Verified the RTL model using System Verilog, Generated functional and code coverage for
the RTL verification sign-off, Synthesized the design.
Trained on Physical Design at UDEMY Online E-learning. Having Knowledge on Floorplanning, Placement,
Routing, Clock Tree Synthesis(CTS). I have done project on “A High Speed And Low Power 16*16 Vedic Multiplier”
by using with SYNOPSYS IC Compiler 45nm Technology, in that project placed macro cells in floorplanning and
implemented power planning techniques later done placement and timing analysis, in that timing analysis I
observed setup time and hold time later done CTS to obtain zero skew, finally done routing and observed is there
any setup and hold time violatons, DRC, LVS or not
TECHNICAL SKILLS:
H/W Description Language : Verilog, SV.
Programming Languages :Perl, Tcl, C.
EDA, Layout Tools : VCS (synopsys), Xilinx, Modelsim, Cadence.
Platforms : Unix, Linux, Windows.
ACADEMIC PROJECTS:
Project Title : “Self-gated Resonant-clocked Flip-flop Optimise For Power Efficiency And Signal
Integrity”
Tools used : Cadence .
Description : Power consumption of the clock tree dominates over 40% of the total power in
modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power
clocking schemes are promising approaches for low-power design. We propose four novel energy recovery
clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy
savings. These flip-flops operate with a single-phase sinusoidal clock which can be generated with high
efficiency. In the Tanner 45nm CMOS technology.
Project Title : “Design And Implementation Of A Highly Efficent MAC Unit In FPGA”
Tools used : Xst Tool.
Description : In this paper, an architecture for a power and area efficient Multiply and
Accumulate(MAC) unit is presented. MAC is the most important block in DSP system. In the design of MAC,
various multipliers and adders were considered and researched. The proposed architecture is designed
using power and area efficient multiplier and adder. The multiplier uses Shannon based multiplexing logic
which is optimized for low power.
Project Title : “A High Speed And Low Power 16*16 Vedic Multiplier”
Tools used : Synopsys IC Compiler.
Description : A high speed complex 16 *16 multiplier design by using urdhva tiryakbhyam
sutra is presented in this paper. By using this sutra the partial products and sums are generated in one step
which reduces the design of architecture in processor’s. By using this sutra we can reduce the time with high
extent when compare to array and booth multiplier.
ADDITIONAL QUALIFICATION / ACHIEVEMENTS / CERTIFICATIONS:
Published my FPGA project in IEEE journal that project name was “DESIGN AND IMPLEMENTATION OF A
HIGHLY EFFICIENT MAC UNIT IN FPGA”.
Published MATHS project “GEODETIC GRAPH THEORY” in IEEE journal.
Got participation certificate for “Nano Electro Mechanical Systems” in The Event SPIKES 2K12 conducted by
Andhra university.
Got all india rank 1400 in GATE 2016.
Got participation certificate in Event AFOSEC 2K14 conducted by Vr Siddhartha engineering college.
I worked as a member in (CCA) is a cultural student oganisation in my Btech (BAPATLA ENGINEERING
COLLEGE).
Organizer for “EISAAA” a Departmental association.
EXPERIENCE:
Company: CADENCE DESIGN SYSTEMS Designation: Application Engineer intern
Working on Genus Tool for Synthesis and DFT, Xcelium for Simulation, Innovus for Physical design,
Modus for ATPG generation, Assura layout editor for Analog layout designing, Virtuoso tools for Analog
circuit design.
Worked on internal lab setups, external lab setups for Different clients of (Qualcomm, synaptics,
Microsemi) and solving Service Requets for analog circuits, layouts, PnR flow.
PERSONAL ASSETS:
Systematic approach to problem solving.
Homing in on problems from multiple perspectives.
Composure & Discipline.
HOBBIES:
Listining songs, Dancing, Playing Chess.