Chandra Kiran K Email id: chandrakirankondapalli@gmail.
com
Mobile Number: 9739150530
CAREER OBJECTIVE:
To obtain a position within the company that will allow me to utilize my skills and knowledge for
the benefit of the company as well as for personal growth and professional advancement.
CORE COMPETENCY:
• Good understanding of fundamentals of Transistors and circuit theory
• Good understanding of VLSI and FPGA design flows
• Good knowledge of FSM based designs
• Good knowledge of Digital Design Concepts
• Extensive experience in writing RTL models in Verilog
• Knowledge in verification methodologies in SV and UVM
• Experience in using industry standard EDA tools for the front-end design
• Real time experience in manual testing of Fpga boards
ACADEMIC QUALIFICATION:
RESULT
UNIVERSITY / YEAR OF
EXAM INSTITUTE (AGGREGATE)
BOARD PASSING
B.E.
Alliance
(Electrical and Alliance college of
university
electronics engineering and Bangalore 2017 85.15%
engineering) design
Board Of
NRI Junior College.
Intermediate Intermediate, 2013 97.1%
Andhra Pradesh.
Andhra Pradesh
Sri Guru Datta
S.S.C Board Of
Concept school Secondary 2011 93.5%
Education.
VLSI Domain Skills:
HDL: Verilog
HVL: System verilog
Verification Coverage driven verification
Methodologies: Assertion based verification-SVA
TB Methodology: UVM
EDA Tool: Riviera Pro and ISE
Domain: FPGA front-end Design and Verification
Knowledge: RTL Coding, FSM based design, Simulation,
Digital design, Synthesis, Static Timing Analysis.
PROFFESIONAL QUALIFICATIONS:
Maven Silicon Certified Advanced VLSI Design course from Maven
Silicon VLSI training Center,Banglore - June 2016-July 2016.
Maven Silicon Certified Advanced VLSI Verification course from
Maven Silicon VLSI training center,Banglore - March 2018 – till date
EXPERIENCE:
Project Intern, Avench systems [Link], Bangalore.
Worked as RTL design engineer
EXTRA CURRICULAR ACTIVTIES:
• State level participation in wrestling, Hand ball, Softball.
• Won first place in Inter college championship in cricket.
• Holds green belt in Karate
ACADEMIC PROJECTS:
[1]. Design and realization of Welding oscillator using Fpga
HDL: Verilog
EDA Tool: Xilinx ISE
FPGA KIT: Spartan 6
Description: Welding is one of the most popular methods to combine metal pieces in
manufacturing processes. Arc welding, among all welding techniques, is the most
commonly used in manufacturing due to its cost and flexibility. During the manufacturing
process, arc welding is either performed by an operator or by automatic tools such as
welding oscillators .Using automatic tools has advantages over manual use, as the process
will be faster, cheaper, and have less welding flaws. In this project, a homemade welding
oscillator and the method to manufacture it are presented. The presented welding oscillator
can be manufactured for a very low price compared to those on the market. Moreover, it
covers industry-level needs and provides even more functionality with small adjustments if
needed by the application.
Responsibilities:
➢ Architected the design.
➢ Implemented RTL using Verilog HDL.
➢ Verified RTL model using Isim simulator.
➢ Synthesized the design.
➢ Interfacing the design with Spartan 6 board.
[2]. Router 1x3 – RTL design and Verification
HDL: Verilog
HVL: System Verilog
EDA Tools: Xilinx ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one
of the three output channels, channel0, channel1 and [Link] error detection technique
that test the integrity of digital data being transmitted between Server & Client. This
technique ensures that the data transmitted by the Server network is received by the Client
network without getting corrupted. Active low synchronous input signal that resets the router.
Under reset condition, the router FIFOs are made empty and the valid out signals goes low
indicating that no valid packet is detected on the output data bus. Sending and Reading
Packet will be done according to the Protocol.
Responsibilities:
➢ Architected the design
➢ Implemented RTL using Verilog HDL.
➢ Verified the RTL model using System Verilog HVL.
➢ Synthesized the design
[3] A 30 channel adjustable PWM controller
Description: A free running PWM controller with adjustable duty cycle, frequency and
adjustable delay from 0.3 ms to 0.7 ms for driving solenoids in sorting application is
developed. The design can run 30 solenoid drivers at a time. The RTL code in Verilog
include generate statements. The aim is to fit the design in the smallest fpga which
involves a lot of optimization techniques.
[4]. Controller for ELIS 1024 line scan image sensor
Description: The controller is developed for a line scan image sensor ELIS [Link]
objective is to set the resolution and mode of operation for the sensor to capture the
image. The output of the sensor is sent through ADC to obtain the digital output of the
image and that digital data is fed back to the Fpga.
PERSONAL PROFILE:
Name Chandra Kiran K
Date of Birth 26/Aug/1996
Permanent address Plot-No 102,SV Residency, Bypass road , Ongole, Andhra
Pradesh, PIN: 523002.
Father Name Anjaneyulu K
Nationality Indian
Sex Male
Languages Known English, Telugu, Hindi
I hereby solemnly declare that the above written particulars are true to the best of my
knowledge and belief.
Yours faithfully,
(Chandra Kiran K)