Page 1 of 7
Home Whiteboard AI Assistant Online Compilers Jobs Tools Art
SQL HTML CSS Javascript Python Java C C++ PHP Scala C#
Digital Communication - Delta Modulation
Chapters Categories
The sampling rate of a signal should be higher than the Nyquist rate, to achieve better
sampling. If this sampling interval in Differential PCM is reduced considerably, the
sampleto-sample amplitude difference is very small, as if the difference is 1-bit
quantization, then the step-size will be very small i.e., Δ (delta).
Delta Modulation
The type of modulation, where the sampling rate is much higher and in which the
stepsize after quantization is of a smaller value Δ, such a modulation is termed as delta
modulation.
Features of Delta Modulation
Following are some of the features of delta modulation.
An over-sampled input is taken to make full use of the signal correlation.
The quantization design is simple.
The input sequence is much higher than the Nyquist rate.
The quality is moderate.
The design of the modulator and the demodulator is simple.
The stair-case approximation of output waveform.
The step-size is very small, i.e., Δ (delta).
The bit rate can be decided by the user.
This involves simpler implementation.
Delta Modulation is a simplified form of DPCM technique, also viewed as 1-bit DPCM
scheme. As the sampling interval is reduced, the signal correlation will be higher.
[Link] 1/7
Page 2 of 7
Delta Modulator
The Delta Modulator comprises of a 1-bit quantizer and a delay circuit along with two
summer circuits. Following is the block diagram of a delta modulator.
The predictor circuit in DPCM is replaced by a simple delay circuit in DM.
From the above diagram, we have the notations as −
x(nTs ) = over sampled input
ep (nTs ) = summer output and quantizer input
eq (nTs ) = quantizer output = v(nTs )
x̂(nTs ) = output of delay circuit
u(nTs ) = input of delay circuit
Using these notations, now we shall try to figure out the process of delta modulation.
ep (nTs ) = x(nTs ) − x̂(nTs )
---------equation 1
= x(nTs ) − u([n − 1]Ts )
= x(nTs ) − [x̂[[n − 1]Ts ] + v[[n − 1]Ts ]]
---------equation 2
[Link] 2/7
Page 3 of 7
Further,
v(nTs ) = eq (nTs ) = S . sig. [ep (nTs )]
---------equation 3
u(nTs ) = x̂(nTs ) + eq (nTs )
Where,
x̂(nTs ) = the previous value of the delay circuit
eq (nTs ) = quantizer output = v(nTs )
Hence,
u(nTs ) = u([n − 1]Ts ) + v(nTs )
---------equation 4
Which means,
The present input of the delay unit
= (The previous output of the delay unit) + (the present quantizer output)
Assuming zero condition of Accumulation,
u(nTs ) = S ∑ sig[ep (jTs )]
j=1
Accumulated version of DM output = ∑ v(jTs )
j=1
---------equation 5
Now, note that
x̂(nTs ) = u([n − 1]Ts )
n−1
= ∑ v(jTs )
j=1
---------equation 6
Delay unit output is an Accumulator output lagging by one sample.
From equations 5 & 6, we get a possible structure for the demodulator.
[Link] 3/7