aa gst a Bases SHAIL GROUP OF INSTITUTIONS INDORE INSTITUTE OF SCIENCE & TECHNOLOGY DEPARTMENT OF ELECTRONICS & COMMUNICATION ee See ee ey rmaneceasalnyna SUBJECT: Basic Electri ind SUBJECT CODE: B’ Electronics Engineering | | Year: I year | SEM :1 & I Sem Experiment No. 1 OBjBCTIVE: - To Verify Kirchoff’s Current Law (KCL) and Kirchoff’s Voltage Law (KVL) Fig (1). Electrical circuit containing three resistances in parallel Electrical and Electronics Engineering Lab Manual00 ne _ << mn, | fr 000 OF institutions ; ST According 10 Kirehhotts Curent Lay, pie Tt states that in a closed circuit, re m " ie 6 um of all the voluge dng lgebraic sum of all source voltages must be equal to tt closed path in a ven circ ig - PS or in other words, the algebraic sum of the voltage around ar in energy and therefore a voltage es zero, When the current passes through the resistor, there is a lo: series. If V1 is the voltage drop acr occurs, Consider the figure (2), in which there are 3 resistances ‘oss resistance 1, V2 is the voltage drop across resistance 2 and V3 the voltage drop a CTOSs resistance 3 then According to Kirchhoff’ voltage law: V=Vi+ VitV3 ais faa 3 Oo ae - + Se WA ——*__~W = VL eS v2 V3 Vv = ![_-—_——— ical circuit containing three resistances in series he currents through the resistors. it the algebraic sum of the currents at a node B,C, D is zero. Il Kirchhoff’s Voltage law: of Connect the circuit as shown in figure (3). a Measure the voltages across the resistors, a Observe that the algebraic sum of voltages in a closed loop 1,2,3,4 is zero. Electrical and Electronics Engineering Lab Manualgst a fa=- Rem 3 Reza Romo of). RA 100 Sol =f] at Yoo + RB 100 A Fig (3). Circuit Diagram VATION TABLE: KCL: Current in © Current in Curentin | Algebraic sumof | © Error branch 1 branch 2 ranch 3 | current meeting at “Table 1: Branch currents meeting at Node B [Current in Current Curentin’ | Algebraic sum of Error | branch 3 __._ branch branch S | current meeting at ; Node C | < ranch currents meeting at Node C Gurentin | Algebraic sum of Error branch 7 current meeting at Node D ‘Table 3: Branch currents meeting at Node D For KVL: Voltage Vi Voltage V2 | Voltage Vs | Algebraic sum of Error voltage in loop 1 J Table 4: Voltages in loop 1 Electrical and Electronics Engineering Lab ManualHee Voltage Va Voltage V4 | Algebraic sum of Eecot | voltage in loop 2 Table 5: Voltages in loop 2 Votage Vs Votage V7 Table 6: vege f \ Voltage Vs oor ss It is tolerable and in branches meeting at the node is zero hence . Itis tolerable andShai Grove OF institutions |AIL GROUP OF INSTITUT) i F SCIE E LOGY INDORE INS E & TECH & COMMUNICATION DEPARTMENT € SUBJECT: Basic Electrical and Electronics Engineering Experiment No. ih OBJECTIVE: - To Verify Kirchoff’s Current Law ( KCL) and Kirchof?’s Voltage Law (KVL) APPARATUS REQUIRED: - 1. Scientech make practical kit model AB-81 2, External Voltage source to work as battery source 3. A set of Ammeter and Voltmeter or Multimeter a « at any node (junction) in a cireuit the algebraic sum of currents entering and | s be equal to zero. Kirchhoff’s current Jaw states that the sum of the currents entering e of the currents leaving the same node. Consider the figure leaving a node at ar (1) in which there are parallel paths. : Wy ~ ty er vl 2 +n = : Bb Lue ns T=T,thrty Fig (1). Electrical circuit containing three resistances in parallel Electrical and Electronics Engineering Lab Manual- net beryl according © Kitehhof?'s Current Law Tehtheh tn, KVL! It states that in a closed circuit the algebralo num of al aource Volake® must bo equal 1 tt algebraic sum of all the voltage drops or in other words, the algebraic #u"” cof the voltage around close pat ina given circuit is avays zero, When the curent pases hous into, there Iv # 10 in energy and therefore a voltage drop occurs. Consider the figure (2), 0 which there are 3 resistances series. If isthe voltngo drop acrons resistance 1, Van thewolege drop aoront resistance 2 and ¥? the voltage drop across resistance 3 then According 0 Kittin volage In Vevit Vit Vs -as shown in figure (3). nts through the resistors. ¢ sum of the currents at a node B,C, D is zero. , shown in figure (3). the resistors. of voltages in a closed loop 1,2,3,4 is zero.ne 5 anes Grown oF wnatitulions Fig (3), Cireuit Diagram IBSERVATION TABLE: KCL: Current in Currentin | Carrentin |, Algebraic sumof Error branch 1 branch 2 branch3 | current meeting at Table T; Branch currents meeting at Node B Current in | Algebraic sum of Error branch 5 current meeting at Node C nch currents meeting at Node C Algebraic sum of Error current meeting at Node D. Algebraic sum of Error voltage in loop 1 + Table 4: Voltages in loop 1 Electrical and Electronics Engineering Lab ManualVolinge Vi Voltage Vs [ream] = fete voltage in loop 2) Table %; Voltages in loop 2 branches mecting at the node is zero hence . Itis tolerable and in the closed path is zero hence KVL is