VARAYA TECH
NOLOGICAL UNIV
ERSIT
ISVES Y
V
Belagavi
Major Project Synonpsis
6th Semester, B.E.
“Electronic design and automation using python”
Submitted By,
Name of the students: Lavanya K USN:4JN22ET021
Nithyashree Hegde 4JN22ET029
Priyanka P 4JN22ET032
Tejaswini K 4JN22ET050
Under the guidance of:
Anand Raj S.N
Assistant Professor,Dept
Of ETE,JNNCE,Shimoga
Department Electronics and Telecommunication Engineering
Jawaharlal Nehru New College of Engineering, Shivamogga-577204
May 2025
[Link]
Digital VLSI Design primarily involves writing synthesizable RTL code using
Hardware Description Languages (HDLs) like VHDL or Verilog. Among the
various stages of hardware design, verification is the most critical and time-
consuming phase. High-Level Synthesis (HLS) enables designers to describe
hardware in high-level languages like C or C++, which is then automatically
converted into synthesizable HDL code for FPGA implementation. Simulation
ensures that the design adheres to its functional specifications. While co-
simulation allows reuse of high-level language testbenches for verification, it
may not always be feasible due to tool constraints or compatibility issues. In
such cases, manual development of HDL testbenches becomes necessary,
adding to development time and complexity.
To mitigate this, we propose a Python-based automated testbench generation
method. The Python script generates SystemVerilog testbenches for HDL code
produced by HLS tools. This significantly reduces the manual effort involved in
writing verification environments. The approach primarily targets memory
components such as queues and FIFOs designed in C, aiming to streamline and
accelerate the testbench creation process through automation.
2. INTRODUCTION
Verification ensures that a hardware design performs its intended function
correctly and without bugs. It is a crucial step in validating complex systems
and confirming that the specified tasks are executed as expected. For designs
described in HDLs like Verilog or VHDL, testbenches are traditionally written
in the same language. Additionally, dedicated verification languages like e offer
enhanced constructs for functional coverage and constraint-driven verification.
Among the available methodologies, SystemVerilog is widely adopted for
creating testbenches, combining design and verification capabilities into a
unified framework. Standardized by IEEE, it provides powerful features such as
object-oriented programming, assertions, and functional coverage.
However, manual development of SystemVerilog testbenches, especially for
HLS-generated HDL designs, is time-intensive. This paper introduces a Python-
based tool to automatically generate SystemVerilog testbenches, reducing the
need for manual coding and thereby accelerating the verification phase.
[Link] SURVEY
1. “Pyverilog: A Python-based Hardware Design Processing
Toolkit” – Yosuke Hara et al.
This paper introduces Pyverilog, a Python framework for parsing and analyzing
Verilog code. It enables automation in hardware design verification tasks such
as testbench generation, linting, and waveform inspection, making it a useful
tool for Python-SV integration workflows.
2. “Automated Testbench Generation for SystemVerilog Using
Python” – IEEE Conference Paper (2020)
This study demonstrates the generation of functional testbenches using Python
scripting. It highlights how Python can be used to dynamically generate test
scenarios, drive stimulus, and verify outputs in SystemVerilog, reducing manual
coding for design verification.
3. “Design and Simulation of FIFO Memory Using Verilog HDL”
– International Journal of Engineering Research and
Applications (IJERA)
This paper focuses on FIFO memory design and simulation using Verilog HDL.
It explains timing, control logic, and the read/write mechanisms, which are key
to generating Python-driven verification frameworks that simulate such
components in SystemVerilog.
4. “Cocotb: Coroutine-based Cosimulation Library for Writing
VHDL and Verilog Testbenches in Python” – Open-Source
Project Documentation
Cocotb allows writing testbenches in Python for Verilog/SystemVerilog
designs. It simplifies cross-language verification, enabling Python to interact
directly with HDL simulators, making it ideal for memory verification projects
where logic is in SV and control is in Python Cocotb allows writing testbenches
in Python for Verilog/SystemVerilog designs. It simplifies cross-language
verification, enabling Python to interact directly with HDL simulators, making
it ideal for memory verification projects where logic is in SV and control is in
Python.
[Link] , Objective and methodology
Aim:
The aim of this paper is to automate the generation of System Verilog
testbenches using a Python script for verifying designs created in C and
synthesized using High-Level Synthesis (HLS) tools. The focus is on memory
components like FIFO and Queue, which are written in a high-level language
and converted into HDL (such as Verilog) for implementation on FPGA
platforms. Traditional co-simulation methods have limitations due to tool-
specific constraints, often requiring users to write separate HDL testbenches
manually. This project addresses that issue by providing an efficient, automated
approach that saves time and reduces human error. It ensures that the functional
verification of HLS-generated designs can be carried out effectively without
manual intervention, thereby improving productivity, simulation accuracy, and
reusability of test data.
Objectives:
1. Automate the generation of SystemVerilog testbenches using a Python
script to reduce manual effort in verifying HLS-generated HDL code.
2. Enable seamless verification of C-based memory designs like FIFO and
Queue after conversion to HDL through High-Level Synthesis tools.
3. Ensure compatibility with industry-standard simulation tools by
producing synthesizable and reusable SystemVerilog testbenches.
4. Incorporate verification features such as input stimulus, output checking,
and assertions to validate design functionality effectively.
5. Streamline the HLS verification process by reusing high-level test data
and minimizing the need for dual-language testbench maintenance.
Methodology:
The process begins with designing memory elements such as queues and FIFOs
in the C programming language. These designs are then synthesized into HDL
using HLS tools like Xilinx Vivado HLS. Once the HDL code is generated, the
Python script takes over to automatically generate a SystemVerilog testbench.
The script analyzes the I/O ports of the design and uses predefined templates to
build testbenches that include signal declarations, clock generation, input
stimulus application, and output checking mechanisms. It also enables data
comparison between expected and actual outputs, logging results, and optionally
supports waveform generation for visual debugging. The testbenches are then
simulated using standard tools like ModelSim or QuestaSim, ensuring that the
converted HDL functions correctly and meets the intended design behavior.
[Link] Statement
In High-Level Synthesis (HLS), designs written in high-level languages like C
are converted into hardware description languages (HDL) for implementation
on FPGA platforms. Verifying these converted designs is a crucial step, yet it
poses significant challenges. While co-simulation allows reuse of high-level
testbenches, it often fails due to tool limitations and compatibility issues. In
such cases, users are forced to manually write HDL testbenches, which is both
time-consuming and prone to errors. This manual effort slows down the
development cycle and introduces inconsistencies in verification. Currently,
there is no automated solution to generate HDL testbenches directly from high-
level language sources. This lack of automation becomes a major bottleneck,
especially when verifying memory components like FIFO and Queue. Designers
are left with redundant tasks that reduce productivity and delay validation.
Therefore, a reliable and automated method for testbench generation is essential
to streamline the HLS-based design verification process.
[Link] DIAGRAM
[Link] PRINCIPLE
The system starts with designing memory elements like FIFO and Queue in C
language. These designs are converted to HDL (e.g., Verilog) using a High-
Level Synthesis (HLS) tool .The Python script reads the HLS-generated HDL
code to extract input and output port details. Based on the extracted information,
the script generates a corresponding SystemVerilog testbench. The testbench
includes modules for clock generation, input signal application,
and output checking .It simulates the behavior of the HDL design by applying
test vectors derived from the C model. The outputs from the design are
compared with expected values for verification. Simulation tools like Model
Sim oQuestaSim are used to run and analyze the testbench. Waveforms and logs
are produced to help debug and validate functionality. This process automates
verification, reduces errors, and improves efficiency in HLS workflows.
[Link] OUTCOME
The proposed approach is expected to automate the generation of
SystemVerilog testbenches using Python, reducing the manual effort involved
in verifying HLS-generated HDL code. It will allow efficient verification of
memory elements like FIFO and Queue designed in C. The generated
testbenches will be compatible with standard simulation tools, ensuring accurate
functional validation. Designers will benefit from a streamlined workflow with
improved consistency and reduced errors. Simulation waveforms and logs will
help in early bug detection. This solution will eliminate the need for writing
separate HDL testbenches when co-simulation fails. It will support reuse and
easy modification of testbenches. The overall verification process will become
faster and more reliable. This approach will enhance productivity in digital
design environments. Ultimately, it will promote automation in HLS-based
verification for both academic and industry applications.
[Link]
1. “Pyverilog: A Python-based Hardware Design Processing Toolkit” –
Yosuke Hara et al
2. “Automated Testbench Generation for SystemVerilog Using Python” –
IEEE Conference Paper (2020)
3. “Design and Simulation of FIFO Memory Using Verilog HDL” –
International Journal of Engineering Research and Applications (IJERA)
4. “Cocotb: Coroutine-based Cosimulation Library for Writing VHDL and
Verilog Testbenches in Python” – Open-Source Project Documentation