Lecture 5:
DC &
Transient
Response
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
5: DC and Transient Response CMOS VLSI Design 4th Ed. 2
Pass Transistors
We have assumed source is grounded
What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
Transmission gates are needed to pass both 0 and 1
5: DC and Transient Response CMOS VLSI Design 4th Ed. 3
Pass Transistor Ckts
VDD VDD VDD
VDD VDD
VDD
Vs = VDD-Vtn VDD-Vtn
VDD-Vtn VDD-Vtn
VDD
VDD-Vtn
Vs = |Vtp|
VDD VDD-2Vtn
VSS
5: DC and Transient Response CMOS VLSI Design 4th Ed. 4
DC Response
DC Response: Vout vs. Vin for a gate
Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
VDD
– In between, Vout depends on
transistor size and current Idsp
Vin Vout
– By KCL, must settle such that Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
5: DC and Transient Response CMOS VLSI Design 4th Ed. 5
Transistor Operation
Current depends on region of transistor behavior
For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
5: DC and Transient Response CMOS VLSI Design 4th Ed. 6
nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin – Vtn Vout > Vin - Vtn
VDD
Vgsn = Vin Idsp
Vin Vout
Vdsn = Vout Idsn
5: DC and Transient Response CMOS VLSI Design 4th Ed. 7
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD Vtp < 0 Idsp
Vin Vout
Vdsp = Vout - VDD Idsn
5: DC and Transient Response CMOS VLSI Design 4th Ed. 8
I-V Characteristics
Make pMOS is wider than nMOS such that n = p
Vgsn5
Idsn Vgsn4
-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn
Vgsp4 -Idsp
Vgsp5
5: DC and Transient Response CMOS VLSI Design 4th Ed. 9
Current vs Vout, Vin
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
5: DC and Transient Response CMOS VLSI Design 4th Ed. 10
Load Line Analysis
For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin3 Vin2 Vin Vout
Vin4 Vin1 Idsn
VDD
Vout
5: DC and Transient Response CMOS VLSI Design 4th Ed. 11
Load Line Analysis
Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD
Vin0 Vin5
in5
Vin1 Vin4
dsn, |Idsp
Idsn dsp
|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
in0
VDD
Vout
out
DD
5: DC and Transient Response CMOS VLSI Design 4th Ed. 12
DC Transfer Curve
Transcribe points onto Vin vs. Vout plot responeventer
for
Vin0 Vin5 CDC VDD
Vin0
A
Vin1
B
Vin2
Vout
Vin1 Vin4
C
Vin2 Vin3
Vin3
Vin3 Vin2 D Vin4 Vin5
Vin4 Vin1 E
0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin
w̅ 8 time III www.t
Voltage
5: DC and Transient Response CMOS VLSI Design 4th Ed. 13
Operating Regions
Revisit transistor operating regions
A VDD
wt short It is circuit J lils Vin Vout
84510 END Vout
g ÉJ 2
Region nMOS pMOS
GND A Cutoff Linear
Cutoff linear VDD
B Saturation
saturation Linear
linear A B
C saturation
Saturation saturation
Saturation Vout
C
D Linear
linear Saturation
Saturation
E Linear
linear Cutoff
Cutoff
D
E
0 Vtn VDD/2 VDD+Vtp
VDD
Vin
5: DC and Transient Response CMOS VLSI Design 4th Ed. 14
Beta Ratio Lenght Chanel [Link]
channel 319
With the following definitions:
width
as
not I
W
g
Process dependent factors:
Geometry dependent factors: W and L.
5: DC and Transient Response CMOS VLSI Design 4th Ed. 15
Beta Ratio
Transistor beta calculation example:
– Typical values for an n-transistor in 1 micron technology:
– Compute beta:
Bn Bp
– How does this beta compare with p-devices:
j
Bn
Bp EST
n-transistor gains are approximately 2.8 times larger than p-
transistors.
Tg w̅ IT IS
5: DC and Transient Response CMOS VLSI Design 4th Ed. 16
I 81 02
87 E 21 9 nmos s pmos
Beta Ratio
If p / n 1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter
T
VDD
DCWTw
si
p
10
n
Vout 2 voltage [Link]
µ
1
p
n
0.1 Dna
0.5
PMOS
as
Pmos ʰ
VDD
Vin
F I
5: DC and Transient Response CMOS VLSI Design 4th Ed. 17
401
j
Eat
right
s
pete 9
with
I
Noise Margins
not recognize the input?
low
Ishida
How much noise can a gate input see before it does
of
high
Margins s Iip D
matt Output Characteristics
VDD
Input Characteristics
Logical High
Output Range VOH Logical High
Input Range
NMH
Voltage VIH
Indeterminate
max VIL Region
int
Logical Low VOL
NML
Logical Low
Input Range
Wh
Output Range
GND
[Link]
5: DC and Transient Response CMOS VLSI Design 4th Ed. 18
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iwa n th gy noise
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Logic Levels
To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
Unity Gain Points
VDD
Slope = -1
VOH
i
roa
p/ n > 1 2919
88
Vin Vout
Vor
V OL
0
Vin
Vtn VIL VIH VDD- VDD
|Vtp|
5: DC and Transient Response CMOS VLSI Design 4th Ed. 19
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Transient Response
DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa
5: DC and Transient Response CMOS VLSI Design 4th Ed. 20
Inverter Step Response
Ex: find step response of inverter driving load cap
Vin (t ) u(t t0 )VDD
Vin(t)
Vout (t t0 ) VDD Vout(t)
Cload
dVout (t ) I dsn (t )
Idsn(t)
dt Cload
Vin(t)
0 t t0
2
I dsn (t ) 2
VDD V t Vout VDD Vt Vout(t)
t
VDD Vt Vout (t ) V (t ) V V V
out t0
2
out DD t
5: DC and Transient Response CMOS VLSI Design 4th Ed. 21
Delay Definitions
tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
tf: fall time
– From output crossing 0.8
VDD to 0.2 VDD
5: DC and Transient Response CMOS VLSI Design 4th Ed. 22
Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
But simulations take time to write, may hide insight
2.0
1.5
1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5
0.0
0.0 200p 400p 600p 800p 1n
t(s)
5: DC and Transient Response CMOS VLSI Design 4th Ed. 23