PD-94526A

AUTOMOTIVE MOSFET IRF1503

Typical Applications HEXFET® Power MOSFET
● 14V Automotive Electrical Systems
● 14V Electronic Power Steering D
VDSS = 30V
Features
● Advanced Process Technology
● Ultra Low On-Resistance RDS(on) = 3.3mΩ
G
● 175°C Operating Temperature
● Fast Switching ID = 75A
● Repetitive Avalanche Allowed up to Tjmax S

Description
Specifically designed for Automotive applications, this
design of HEXFET® Power MOSFETs utilizes the lastest
processing techniques to achieve extremely low on-
resistance per silicon area. Additional features of this
HEXFET power MOSFET are a 175°C junction operating
temperature, fast switching speed and improved repetitive
avalanche rating. These combine to make this design an
extremely efficient and reliable device for use in Automotive
applications and a wide variety of other applications. TO-220AB

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon limited) 240
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig.9) 170 A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package limited) 75
IDM Pulsed Drain Current  960
PD @TC = 25°C Power Dissipation 330 W
Linear Derating Factor 2.2 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 510 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value† 980
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy mJ
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.45
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62

[Link] 1
12/11/02
IRF1503
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.028 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 2.6 3.3 mΩ VGS = 10V, ID = 140A ƒ
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 75 ––– ––– S VDS = 25V, ID = 140A
––– ––– 20 VDS = 30V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 30V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 130 200 ID = 140A
Qgs Gate-to-Source Charge ––– 36 54 nC VDS = 24V
Qgd Gate-to-Drain ("Miller") Charge ––– 41 62 VGS = 10V
td(on) Turn-On Delay Time ––– 17 ––– VDD = 15V
tr Rise Time ––– 130 ––– ID = 140A
ns
td(off) Turn-Off Delay Time ––– 59 ––– RG = 2.5Ω
tf Fall Time ––– 48 ––– VGS = 10V ƒ
Between lead, D
LD Internal Drain Inductance ––– 5.0 –––
6mm (0.25in.)
nH G
from package
LS Internal Source Inductance ––– 13 –––
and center of die contact S

Ciss Input Capacitance ––– 5730 ––– VGS = 0V

Coss Output Capacitance ––– 2250 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 290 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 7580 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 2290 ––– VGS = 0V, VDS = 24V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance „ ––– 3420 ––– VGS = 0V, VDS = 0V to 24V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
D
IS Continuous Source Current MOSFET symbol
––– ––– 240
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 960

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 140A, VGS = 0V ƒ
trr Reverse Recovery Time ––– 71 110 ns TJ = 25°C, IF = 140A, VDD = 15V
Qrr Reverse RecoveryCharge ––– 110 170 nC di/dt = 100A/µs ƒ
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by „ Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11).
as Coss while VDS is rising from 0 to 80% VDSS .
‚ Starting TJ = 25°C, L = 0.049mH
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
R G = 25Ω, IAS = 140A. (See Figure 12).
avalanche performance.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
† This value determined from sample failure population. 100%
tested to this value in production.
2 [Link]
 IRF1503

1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
100 5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V

100
4.5V
4.5V
10

20µs PULSE WIDTH 20µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 10
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 200
T J = 25°C T J = 175°C
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)

T J = 175°C 160

120
TJ = 25°C
100

80

40
VDS = 25V VDS = 25V
20µs PULSE WIDTH 20µs PULSE WIDTH
10 0
4.0 5.0 6.0 7.0 8.0 9.0 10.0 0 40 80 120 160 200
VGS , Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

Vs. Drain Current
[Link] 3
IRF1503

10000 20
VGS = 0V, f = 1 MHZ
C iss = C gs + C gd , C ds ID= 140A VDS= 24V
SHORTED

VGS , Gate-to-Source Voltage (V)

8000 Crss = Cgd 16
Coss = Cds + Cgd
C, Capacitance (pF)

6000 Ciss 12

4000 8
Coss

2000 4

Crss
0
0
0 40 80 120 160 200
1 10 100
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.0 10000
OPERATION IN THIS AREA
LIMITED BY RDS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.0 1000
T J = 175°C

100 100µsec
10.0

1msec

1.0 10
T J = 25°C 10msec
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.1 1
0.0 0.4 0.8 1.2 1.6 2.0 1 10 100

VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
4 [Link]
 IRF1503

240 2.0
I D = 240A
LIMITED BY PACKAGE

200

1.5

RDS(on) , Drain-to-Source On Resistance

160
ID , Drain Current (A)

(Normalized)
120 1.0

80

0.5

40

V GS = 10V
0 0.0
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

TC , Case Temperature ( °C) TJ, Junction Temperature ( °C)

Fig 9. Maximum Drain Current Vs. Fig 10. Normalized On-Resistance

Case Temperature Vs. Temperature

D = 0.50
(Z thJC)

0.1 0.20

0.10
Thermal Response

0.05

0.02 SINGLE PULSE

0.01 (THERMAL RESPONSE)
P DM

0.01
t1

t2

Notes:
1. Duty factor D = t1/ t 2
2. Peak T J = P DM x Z thJC +T C
0.001
0.00001 0.0001 0.001 0.01 0.1

t 1, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

[Link] 5
IRF1503

1000
15V ID
TOP 59A
100A
DRIVER 800 BOTTOM 140A
VDS L

EAS , Single Pulse Avalanche Energy (mJ)

RG D.U.T + 600
V
- DD
IAS A
20V
VGS
tp 0.01Ω
400

Fig 12a. Unclamped Inductive Test Circuit

V(BR)DSS
200
tp

0
25 50 75 100 125 150 175

Starting T , JJunction Temperature ( °C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
QGS QGD 4.0
VGS(th) Gate threshold Voltage (V)

VG

3.0
Charge ID = 250µA

Fig 13a. Basic Gate Charge Waveform

Current Regulator
Same Type as D.U.T.
2.0
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
1.0
VGS -75 -50 -25 0 25 50 75 100 125 150 175 200
3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
6 [Link]
 IRF1503

10000

Duty Cycle = Single Pulse

1000 Allowed avalanche Current vs
Avalanche Current (A)

avalanche pulsewidth, tav

assuming ∆ Tj = 25°C due to
0.01 avalanche losses. Note: In no
100 case should Tj be allowed to
0.05 exceed Tjmax
0.10

10

1
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current [Link]

600 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at [Link])
BOTTOM 50% Duty Cycle 1. Avalanche failures assumption:
500 ID = 140A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

temperature far in excess of T jmax. This is validated for

every part type.
400
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
300
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
200 avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
100 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
T jmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav ) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
Vs. Temperature EAS (AR) = PD (ave)·t av
[Link] 7
IRF1503

Driver Gate Drive

D.U.T P.W.
Period D=
P.W.
Period
+

ƒ
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
‚ Reverse
Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

RD
VDS

VGS
D.U.T.
RG
+
-V DD

10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

VDS
90%

10%
VGS
td(on) tr t d(off) tf

Fig 18b. Switching Time Waveforms

8 [Link]
 IRF1503
Package Outline
TO-220AB
Dimensions are shown in millimeters (inches)
10.54 (.415) 3.78 (.149) -B-
2.87 (.113) 10.29 (.405) 3.54 (.139) 4.69 (.185)
2.62 (.103) 4.20 (.165)
-A- 1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045) LEAD ASSIGNMENTS
MIN 1 - GATE
1 2 3 2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09 (.555)
13.47 (.530) 4.06 (.160)
3.55 (.140)

0.93 (.037) 0.55 (.022)

3X 3X
0.69 (.027) 0.46 (.018)
1.40 (.055)
3X
1.15 (.045) 0.36 (.014) M B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

Part Marking Information

TO-220AB
EXAMPLE : THIS IS AN IRF1010
WITH ASSEMBLY A
LOT CODE 9B1M INTERNATIONAL PART NUMBER
RECTIFIER
IRF1010
LOGO 9246
9B 1M DATE CODE
ASSEMBLY
(YYWW)
LOT CODE
YY = YEAR
WW = WEEK

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.
This product has been designed and qualified for Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at [Link] for sales contact information. 12/02
[Link] 9