SystemVerilog UNIT-2
and UNIT-3
PART-1
Classes, Interfaces, Clocking,
Randomization and Constrained
randomization
Dr. Sowmya K B
Deptartment of ECE
RVCE, Bengaluru
Dr. Sowmya K B 1
SystemVerilog classes
Classes
• A class is a user defined data type that includes
data (class properties), functions and tasks that
operate on data. functions and tasks are called
methods, both are members of the class.
• classes allow objects to be dynamically created,
deleted, assigned, and accessed via object
handles.
Dr. Sowmya K B 2
Class Declaration
class sv_class;
int x; //class properties
task set(int i); //method-1
x = i;
endtask
function int get(); //method-2
return x;
endfunction
endclass
Dr. Sowmya K B 3
Class handle and Object Creation
• class is a data type, variable (class handles)
can be declared with the class type
sv_class class_1;
class handle
• class properties and methods can be accessed
only after creating the object.
class_1 = new();
• Both declaration of variable and object
creation.
sv_class class_1 = new();
Dr. Sowmya K B 4
Accessing class properties and methods
Dr. Sowmya K B 5
• Simulator Output
class_1 :: Value of x = 10
class_1 :: Value of x = 20
Dr. Sowmya K B 6
SystemVerilog Class Constructors
• Constructor can be used for initializing the
class properties.
• In case of any initialization required, those
can be placed in the constructor and It is also
possible to pass arguments to the constructor,
which allows run-time customization of an
object.
Dr. Sowmya K B 7
Class properties initialization by Constructor
Dr. Sowmya K B 8
class packet;
bit [31:0] addr;
bit [31:0] data; //class properties
bit write;
string pkt_type;
function new();
addr = 32'h10; //constructor
data = 32'hFF;
write = 1;
pkt_type = "GOOD_PKT";
endfunction
function void display(); // methods
$display("---------------------------------------------------------");
$display("\t addr = %0d",addr);
$display("\t data = %0h",data);
$display("\t write = %0d",write);
$display("\t pkt_type = %0s",pkt_type);
$display("---------------------------------------------------------");
endfunction
endclass Dr. Sowmya K B 9
module sv_constructor;
packet pkt;
initial begin
pkt = new();
[Link]();
end
endmodule
Dr. Sowmya K B 10
• Simulator Output
addr = 16
data = ff
write = 1
pkt_type = GOOD_PKT
Dr. Sowmya K B 11
SystemVerilog class this keyword
" this " keyword
The this keyword is used to refer to class
properties.
• If the properties of class and argument to the
constructor are having the same name, this will
lead to an ambiguity in assignment and values
will not be assigned properly.
Dr. Sowmya K B 12
class packet;
bit [31:0] addr; //class properties
string pkt_type;
function new(bit [31:0] addr, pkt_type); // class constructor
addr = addr;
pkt_type = pkt_type;
endfunction
function void display(); //methods
$display("\t addr = %0h",addr);
$display("\t pkt_type = %0s",pkt_type);
endfunction
endclass
module sv_constructor;
packet pkt;
initial begin
pkt = new(32'h10,"GOOD_PKT");
[Link]();
end
Dr. Sowmya K B 13
endmodule
The above problem can be overcome by using
"this" keyword to the class properties.
Dr. Sowmya K B 14
class packet;
bit [31:0] addr; //class properties
string pkt_type;
function new(bit [31:0] addr, string pkt_type);
[Link] = addr;
this. pkt_type = pkt_type; //constructor
endfunction
function void display(); //methods
$display("\t addr = %0h",addr);
$display("\t pkt_type = %0s",pkt_type);
endfunction
endclass
module sv_constructor;
packet pkt;
initial begin
pkt = new(32'h10,"GOOD_PKT");
[Link]();
end endmodule Dr. Sowmya K B 15
Simulator Output
addr = 10
pkt_type = GOOD_PKT
Dr. Sowmya K B 16
SystemVerilog Class Assignment
Object will be created only after doing new to an
class handle,
packet pkt_1;
pkt_1 = new();
packet pkt_2;
pkt_2 = pkt_1;
Dr. Sowmya K B 17
Class Assignment
Here object is created only for pkt_1, pkt_2 is just an handle to the packet. pkt_1 is
assigned to the pkt_2. so only one object has been created, pkt_1 and pkt_2 are two
handles both are pointing to the same object. As both the handles are pointing to the
same object any changes made with-respect to pkt_1 will reflect on pkt_2.
Dr. Sowmya K B 18
ShallowCopy
Dr. Sowmya K B 19
Limitations of Shallow Copy
Dr. Sowmya K B 20
Deep Copy
Dr. Sowmya K B 21
endclass
Ex: Shallow Copy
class A;
int i;
endclass
class B;
A a;
endclass
module main;
initial
begin
B b1;
B b2;
b1 = new();
b1.a = new();
b1.a.i = 123; OUTPUT:
b2 = new b1;
$display( b1.a.i );
$display( b2.a.i );
b1.a.i = 321;
$display( b1.a.i );
$display( b2.a.i );
end endmodule Dr. Sowmya K B 22
Ex: Deep Copy
class A;
int i;
endclass
class B;
A a;
task copy(A a);
this.a = new a;
endtask
endclass
module main;
initial begin
B b1;
B b2;
b1 = new();
OUTPUT:
b1.a = new();
b1.a.i = 123;
b2 = new b1;
$display( b1.a.i );
$display( b2.a.i );
[Link](b1.a);
b1.a.i = 321;
$display( b1.a.i );
$display( b2.a.i );
end endmodule Dr. Sowmya K B 23
Extending Classes – Inheritance
• One of the key features of object-oriented programming
is the ability to create new classes that are based on
existing classes.
• A derived(child) class by default inherits the properties
and methods of its parent or base class. However, the
derived class may add new properties and methods, or
modify the inherited properties and methods.
• In other words, the child class is a more specialised
version of the parent class.
Dr. Sowmya K B 24
In SystemVerilog the syntax for deriving or inheriting one class
from another is this:
class DerivedClass_name extends BaseClass_name;
// New and overridden property and method declarations.
endclass
Ex:
class ShiftRegister extends Register;
task shiftleft; data = data << 1; endtask
task shiftright; data = data >> 1; endtask
endclass
Dr. Sowmya K B 25
Example - 1 : parent class properties is accessed using child class
handle, i.e child class will have(inherit) parent class properties
and methods.
class parent_class;
bit [31:0] addr;
endclass
class child_class extends parent_class;
bit [31:0] data;
endclass
module inheritence1;
initial begin
child_class c = new();
[Link] = 10;
[Link] = 20;
$display("Value of addr = %0d data = %0d",[Link],[Link]);
end
endmodule
Dr. Sowmya K B 26
• Simulator Output
Value of addr = 10 data = 20
Dr. Sowmya K B 27
Overriding class properties
or Methods
Base class or parent class properties and methods can be overridden in the
child class or extended class.
class parent_class;
function display();
endclass
class child_class extends parent_class;
function display();
endclass
module inheritence;
child_class c=new();
[Link]();
end
endmodule
Dr. Sowmya K B 28
Example - 1
parent class method display is overridden in the child class. calling [Link] will call display of child class not the parent
class.
class parent_class;
bit [31:0] addr;
function display();
$display("Addr = %0d",addr);
endfunction
endclass
class child_class extends parent_class;
bit [31:0] data;
function display();
$display("Data = %0d",data);
endfunction
endclass
module inheritence;
initial begin
child_class c=new();
[Link] = 10;
[Link] = 20;
[Link]();
end
endmodule
Dr. Sowmya K B 29
super keyword
The super keyword is used in a child class to refer to
members of the parent class.
It is necessary to use super to access members of a
parent class when those members are overridden by
the derived class.
In child class, method with the same name of parent
class will override the method. By using super
keyword parent class method can be accessed from
child class.
Dr. Sowmya K B 30
Example - 1
parent class method display is overridden in the child class, by calling [Link]()
from child class display method of parent class can be accessed.
class parent_class;
bit [31:0] addr;
function display();
$display("Addr = %0d",addr);
endfunction
endclass
class child_class extends parent_class;
bit [31:0] data;
function display();
[Link]();
$display("Data = %0d",data);
endfunction
endclass
module inheritence;
initial begin
child_class c= new();
[Link] = 10;
[Link] = 20;
[Link]();
end
endmodule
Dr. Sowmya K B 31
class parent ;
int a,b;
function display();
$display(“a=%d,b=%d",a,b);
endfunction
endclass
class subclass extends parent;
function display();
$display("a=%d,b=%d",a,b);
endfunction
endclass
module inharit_overried; OUTPUT:
initial begin a= 0,b= 0
parent p = new();
subclass s = new();
[Link]();
end
Dr. Sowmya K B 32
endmodule
class parent ;
int a,b;
function display();
$display(“a=%d,b=%d",a,b);
endfunction
endclass
class subclass extends parent;
function display();
[Link]();
$display("a=%d,b=%d",a,b);
endfunction
endclass
module inharit_overried;
a= 0,b= 0
initial begin a= 0,b= 0
parent p = new();
subclass s = new();
[Link]();
end
endmodule
Dr. Sowmya K B 33
class parent ;
int a,b;
function new();
this.a=1;
this.b=2;
endfunction
function display();
$display(“a=%d,b=%d",a,b);
endfunction
endclass
OUTPUT:
class subclass extends parent; a= 1,b= 2
function display(); a= 1,b= 2
[Link]();
$display("a=%d,b=%d",a,b);
endfunction Dr. Sowmya K B 34
class parent ;
int a,b; Chaining new()
function new();
this.a=1;
constructors
this.b=2;
endfunction
function display();
$display("x=%d,y=%d",a,b);
endfunction
endclass
class subclass extends parent;
function new();
[Link]();
super.a=4;
super.b=5;
endfunction OUTPUT:
function display(); x= 4,y= 5
[Link](); a= 4,b= 5
$display("a=%d,b=%d",a,b);
endfunction
endclass Dr. Sowmya K B 35
Ex2:
class A ;
integer j;
function new();
begin
j = 10;
end
endfunction
task print();
begin
$display("j is %0d",j);
end
endtask
endclass
Dr. Sowmya K B 36
class B extends A;
integer i = 1;
function new();
begin
// call the parent new
[Link](); // constructor chaining
$display("Done calling the parent new");
i = 100;
end
endfunction
// Override the parent class print
task print();
begin
$display("i is %0d",i);
$display("Call the parent print");
[Link]();
end
endtask
endclass
module class_super;
initial begin
B b1;
b1 = new;
[Link]();
end
endmodule Dr. Sowmya K B 37
• Simulator Output
Done calling the parent new
i is 100
Call the parent print
j is 10
Dr. Sowmya K B 38
Encapsulation in system verilog :
local and protected keywords
• In systemverilog all the properties of the class are
public by default or we can say it be accessed outside
the class directly using the dot operator.
• If we want to protect the access of the class
variables/properties from outside the class we can use
the local keyword. Hiding the properties from being
accessed outside the class is called encapsulation.
• If we want to make the properties accessible in the
child classes but not outside the classes. We can declare
the properties as protected. Then it will be available in
the child classes but not in the main module.
Dr. Sowmya K B 39
Ex1:
Protecting the access of the class variables/properties from
outside the class
class parent_class;
local bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass
module encapsulation;
initial begin
parent_class pc = new();
pc.tmp_addr = 20; //Accessing local variable outside the class
[Link]();
end
endmodule
Dr. Sowmya K B 40
• Simulator Output
Error
Local member 'tmp_addr' of class 'parent_class' is not
visible to scope 'encapsulation'.
Dr. Sowmya K B 41
Accessing local variable within the
class ( Allowed )
class parent_class;
local bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass
Simulator Output
module encapsulation;
initial begin Addr = 15
parent_class pc = new(5);
[Link]();
end
endmodule Dr. Sowmya K B 42
Example-1: Accessing protected variable outside the class ( Not allowed )
class parent_class;
protected bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass
class child_class extends parent_class;
function new(bit [31:0] r_addr);
[Link](r_addr);
endfunction
function void incr_addr();
tmp_addr++;
endfunction
endclass
Dr. Sowmya K B 43
module encapsulation;
initial begin
parent_class p_c = new(5);
child_class c_c = new(10);
// variable declared as protected cannot be accessed outside the
//class
p_c.tmp_addr = 10;
p_c.display();
c_c.incr_addr(); //Accessing protected variable in extended class
c_c.display();
end endmodule
Dr. Sowmya K B 44
• Simulator Output
Error
Protected member 'tmp_addr' of class 'parent_class'
is not visible to scope 'encapsulation'.
Dr. Sowmya K B 45
Example-2: Accessing protected variable in the extended class ( allowed )
class parent_class;
protected bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass
class child_class extends parent_class;
function new(bit [31:0] r_addr);
[Link](r_addr);
endfunction
function void incr_addr();
tmp_addr++;
endfunction
endclass
Dr. Sowmya K B 46
module encapsulation;
initial begin
child_class c_c = new(10);
c_c.incr_addr(); //Accessing protected variable in extended class
c_c.display();
end
endmodule
Dr. Sowmya K B 47
Simulator Output
tmp_addr = 21
Dr. Sowmya K B 48
Constrained Randomization
• Random Variables - rand and randc,
• Randomize( ) Method - Pre/Post Randomize( )
methods
Dr. Sowmya K B 49
Directed Vs Random testing
Directed Random
•Detect the expected bugs •Detects unexpected bugs
(corner cases)
•Time consuming •Tremendously reduce the
efforts
•Enough directed test-cases •Random variables are best
cannot be written when the packaged in a class, since they
design complex is more can be grouped along with their
constraints and reused
So, Shift from directed to
randomized test cases.
Dr. Sowmya K B 50
Random Variables
Class variables can be declared random using the rand and randc type-modifier keywords.
Following types can be declared as rand and randc,
• singular variables of any integral type
• arrays
• arrays size
• object handle's
Variables declared with the rand keyword are standard random variables. Their values are
uniformly distributed over their range.
rand bit [3:0] addr;
addr is a 4-bit unsigned integer with a range of 0 to 15. on randomization this variable shall be
assigned any value in the range 0 to 15 with equal probability.
Variables declared with the randc keyword, their values doesn't repeat a random value until every
possible value has been assigned(Cyclic).
randc bit wr_rd;
In order to randomize the object variables, need to call randomize() method.
[Link]();
Dr. Sowmya K B 51
Random Variables:Example-1
2-variables addr1 and addr2 of same bit type is declared as rand and randc
class packet;
rand bit [2:0] addr1;
randc bit [2:0] addr2;
endclass
module rand_methods;
initial begin
packet pkt;
pkt = new();
repeat(10)
begin
[Link]();
$display("\taddr1 = %0d \t addr2 = 0d", pkt.addr1, pkt.addr2);
end
end
endmodule
Dr. Sowmya K B 52
Dr. Sowmya K B 53
Enabling and disabling the random
variables
•The rand_mode() method can be used to enable or disable the
randomization of variable declared with rand/randc.
•The syntax for the rand_mode() method is:
addr.rand_mode(0); //disable randomization of addr
[Link].rand_mode(0);
•By default rand_mode value for all the random variables will
be 1.
•After setting rand_mode(0) to any random variable, it will get
randomized only after rand_mode(1).
Dr. Sowmya K B 54
SystemVerilog Randomization
The randomize() methods: Methods
•Every class contains built-in pre_randomize() and post_randomize() functions.
•Upon calling randomize(), pre_randomize() and post_randomize() functions will
get called before and after the randomize call respectively.
•Users can override the pre_randomize() and post_randomize() in any classes.
•pre_randomize → function used to set pre-conditions before the object
randomization.
Ex: user can disable the randomization of particular variables based on test
conditions.
•post_randomize → function used to check/perform conditions after the object
randomization.
Ex: user can override the randomized values or can print the randomized
variables.
Dr. Sowmya K B 55
Example 1:
• 2-variables addr and wr_rd
• addr is adress of location
• wr_rd =1 write operation and wr_rd= 0 read operation
• In order to perform write followed by read to the same addr,
randomization of addr is controlled based on the previous
randomization value of wr_rd.
class packet;
rand bit [7:0] addr;
randc bit wr_rd;
bit tmp_wr_rd;
//pre-randomization function - disabling randomization of addr, if the
previous operation is write.
function void pre_randomize();
if(tmp_wr_rd==1)
addr. rand_mode(0);
else
addr.rand_mode(1); Dr. Sowmya K B 56
endfunction
//post-randomization function - store the wr_rd value to //tmp_wr_rd and
display randomized values of addr and wr_rd
function void post_randomize();
tmp_wr_rd = wr_rd;
$display("POST_RANDOMIZATION:: Addr = %0h,
wr_rd = %0h", addr, wr_rd);
endfunction
endclass
module rand_methods;
initial begin
packet pkt=new();
repeat(4)
[Link]();
end
endmodule
Dr. Sowmya K B 57
Dr. Sowmya K B 58
Random weighted case
If we want to Randomly pick one out of the many
statements. Then
• The keyword randcase introduces a case statement that
randomly selects one of its branches.
• The case item expressions are positive integer values that
represent the weights associated with each item.
• Probability of selecting an item is derived by the division
of that item’s weight by the sum of all weights
Dr. Sowmya K B 59
Syntax
randcase
item : statement;
...
endcase
Dr. Sowmya K B 60
Example 1:
module ss;
initial begin
for (int i = 0; i < 10; i++)
randcase
1 : $display ("Wt 1");
5 : $display ("Wt 5");
3 : $display ("Wt 3");
endcase
end
endmodule
Dr. Sowmya K B 61
Output:
Wt 5
Wt 5
Wt 3
Wt 5
Wt 1
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
Note: 5 appeared max time, 1 appeared least time and 3 appeared in moderate
Dr. Sowmya K B 62
Example 2:
module tb;
initial begin
for (int i = 0; i < 10; i++)
randcase
0 : $display ("Wt 1");
5 : $display ("Wt 5");
3 : $display ("Wt 3");
endcase
end
endmodule
Dr. Sowmya K B 63
Output:
Wt 5
Wt 5
Wt 3
Wt 5
Wt 5
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
Dr. Sowmya K B 64
module m1;
task t1();
Example 3:
begin
randcase
20 : begin
$write ("What should I do ? \n");
end
20 : begin
$write ("Should I work\n");
end
20 : begin
$write ("Should I watch Movie\n");
end
40 : begin
$write ("Should I complete selfstudy\n");
end
endcase
end
endtask
initial
begin
repeat(10)
begin
t1();
end
$finish;
end Dr. Sowmya K B 65
endmodule
Output:
What should I do ?
Should I complete selfstudy
Should I watch Movie
What should I do ?
Should I complete selfstudy
Should I watch Movie
Should I complete selfstudy
Should I complete selfstudy
Should I work
Should I watch Movie
Dr. Sowmya K B 66
RANDSEQUENCE
The random sequence generator is useful for
randomly generating sequences of stimulus.
Dr. Sowmya K B 67
Example 1:
module m1();
initial
begin
repeat(5)
begin
randsequence( main1 )
main1 : two one three ;
one : {$write(" thing");};
two : {$write(" any");};
three: {$display(" read");};
endsequence
end
end
endmodule
Dr. Sowmya K B 68
Output:
any thing read
any thing read
any thing read
any thing read
any thing read
Dr. Sowmya K B 69
Constrained Randomization
• Complex designs pose more difficulty as they need a complex set of
stimuli needed to check their complete functionality
• Directed test-cases may be written to check a certain set of features,
but, enough directed test-cases cannot be written when the number
of features keeps doubling
• The solution is to create test-cases automatically using constrained-
random tests (CRT). (the test scenarios may be restricted to those
that are both valid and of interest by using constraints).
• A CRT finds bugs even from corner cases (un-predictable), by using
random stimulus. (A directed test finds the bugs that are predictable)
• A CRT is made of 2- parts: the test code that uses a stream of
random values to create input to the DUT, and a seed to the pseudo-
random number generator (PRNG)
Dr. Sowmya K B 70
SystemVerilog Constraint Blocks
• As the name says random variable will get random
value on randomization, By writing constraints to a
random variable, user can get specific value on
randomization. constraints to a random variable shall
be written in constraint blocks.
• Constraint blocks are class members, like tasks,
functions, and variables. Each constraint block will
have unique name within a class.
constraint addr_range { addr > 5; }
• where addr_range is constraint block name
• addr is constrained in such a way that on randomization addr should get
value greater than 5.
Dr. Sowmya K B
Example-1:
defining of constraint block inside class body.
class packet;
rand bit [3:0] addr;
constraint addr_range { addr > 5; }
endclass
module m1;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
[Link]();
$display("\taddr = %0d",[Link]);
end
end
endmodule Dr. Sowmya K B
Example-2:
defining of constraint block Outside class body.
class packet;
rand bit [3:0] addr;
constraint addr_range; //constraint block declaration
endclass
//constraint implementation outside class body
constraint packet::addr_range { addr > 5; }
module m1;
initial begin
packet pkt; pkt = new();
repeat(10) begin
[Link]();
$display("\taddr = %0d",[Link]);
end end
Dr. Sowmya K B
endmodule
Constraint Inheritance
• As class members, constraints also will get
inherited from parent class to child class. in a
child class, constraint blocks can be overridden
by writing constraint block with same name as
in parent class.
• In the example below,
constraint to an addr > 5 of parent class is overridden
with constraint addr < 5 in child class.
Dr. Sowmya K B
class packet;
rand bit [3:0] addr;
constraint addr_range { addr > 5; }
endclass
class packet2 extends packet;
constraint addr_range { addr < 5; } //overriding constraint of parent class
Endclass
module const_inhe;
initial begin
packet pkt1;
packet2 pkt2;
pkt1 = new();
pkt2 = new();
repeat(5)
begin
[Link]();
$display("\tpkt1:: addr = %0d",[Link]);
Dr. Sowmya K B
end
Simulator Output :
pkt1:: addr = 14
pkt1:: addr = 10
pkt1:: addr = 9
pkt1:: addr = 8
pkt1:: addr = 9
pkt2:: addr = 0
pkt2:: addr = 1
pkt2:: addr = 2
pkt2:: addr = 0
pkt2:: addr = 2
Dr. Sowmya K B
Distribution Constraint
• With dist operator, some values can be allocated
more often to a random variable. A dist operator
takes a list of values and weights, separated by :=
or :/ operator.
• The values and weights can be constants or
variables, value can be single or a range the
default weight of an unspecified value is := 1
• value with the more weight will get allocated
more often to an random variable
Dr. Sowmya K B
The := operator assigns the specified weight to the item, or if the item
is a range, specified weight to every value in the range.
addr dist { 2 := 5, [10:12] := 8 };
addr = 2 , weight 5
addr = 10, weight 8
addr = 11, weight 8
addr = 12, weight 8
The :/ operator assigns the specified weight to the item, or if the item is
a range, specied weight/n to every value in the range. where n is
number of values in the range.
addr dist { 2 :/ 5, [10:12] :/ 8 };
addr = 2 , weight 5
addr = 10, weight 8/3
addr = 11, weight 8/3
addr = 12, weight 8/3
Dr. Sowmya K B
In the example below,
On randomization, the probabality of 'addr' is getting the value of
10 is more than 7 and 2. because of weightage specified to each
value in the constraint.
class packet;
rand bit [3:0] addr;
constraint addr_range { addr dist { 2 := 5, 7 := 8, 10 := 12 }; }
endclass
module constr_dist;
initial
begin
packet pkt;
pkt = new();
repeat(10) begin
[Link]();
$display("\taddr = %0d",[Link]);
end
end
endmodule Dr. Sowmya K B
Simulator Output:
addr = 10
addr = 7
addr = 10
addr = 10
addr = 10
addr = 7
addr = 7
addr = 2
addr = 10
addr = 10
Dr. Sowmya K B
Difference between := and :/
constraint addr_1_range { addr_1 dist { 2 := 5, [10:12] := 8 }; }
constraint addr_2_range { addr_2 dist { 2 :/ 5, [10:12] :/ 8 }; }
addr_1=2 weight=5,
addr_1=10 weight=8,
addr_1=11 weight=8,
addr_1=12 weight=8
addr_2=2 weight=5,
addr_2=10 weight=8/3=2.66,
addr_2=11 weight=2.66,
addr_2=12 weight=2.66
Dr. Sowmya K B
Example: Difference between := and :/
class packet;
rand bit [3:0] addr_1;
rand bit [3:0] addr_2;
constraint addr_1_range { addr_1 dist { 2 := 5, [10:12] := 8 }; }
constraint addr_2_range { addr_2 dist { 2 :/ 5, [10:12] :/ 8 }; }
endclass
module constr_dist;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
[Link]();
$display("\taddr_1 = %0d",pkt.addr_1);
end
repeat(10) begin
[Link]();
$display("\taddr_2 = %0d",pkt.addr_2);
end
end endmodule Dr. Sowmya K B
Simulator Output :
addr_1 = 2
addr_1 = 12
addr_1 = 12
addr_1 = 12
addr_1 = 11
addr_1 = 10
addr_1 = 11
addr_1 = 2
addr_1 = 11
addr_1 = 12
addr_2 = 10
addr_2 = 12
addr_2 = 2
addr_2 = 2
addr_2 = 10
addr_2 = 10
addr_2 = 2
addr_2 = 11
addr_2 = 11
addr_2 = 12 Dr. Sowmya K B
Constraint inside
With inside operator, random variables will get values
specified within the block followed by inside operator.
values within the inside block can be variable, constant or
range.
constraint addr_range { addr inside {1,3,5,7,9}; }
constraint addr_range { addr inside {[5:10]}; }
constraint addr_range { addr inside {1, 3, [5:10], 12,
[13:15] }; }
constraint addr_range { !addr (inside {[5:10]}); }
rand bit [3:0] start_addr;
rand bit [3:0] end_addr;
rand bit [3:0] addr;
constraint addr_range { addr inside
{[start_addr:end_addr]}; }Dr. Sowmya K B
class packet;
rand bit [3:0] addr_1; Example-1:
rand bit [3:0] addr_2;
rand bit [3:0] start_addr;
rand bit [3:0] end_addr;
constraint addr_1_range { addr_1 inside {[start_addr:end_addr]}; }
constraint addr_2_range { !(addr_2 inside {[start_addr:end_addr]}); }
endclass
module constr_inside;
initial begin
packet pkt;
pkt = new();
repeat(3)
begin
[Link]();
$display("\tstart_addr = %0d,end_addr = %0d",pkt.start_addr,pkt.end_addr);
$display("\taddr_1 = %0d",pkt.addr_1);
$display("\taddr_2 = %0d",pkt.addr_2);
end
end Dr. Sowmya K B
endmodule
Simulator Output
start_addr = 12,end_addr = 12
addr_1 = 12
addr_2 = 4
start_addr = 3,end_addr = 7
addr_1 = 6
addr_2 = 8
start_addr = 7,end_addr = 11
addr_1 = 7
addr_2 = 6
Dr. Sowmya K B
Constraint implication
Implication (->)
The implication operator ( –> ) can be used to declare
conditional relations.
expression -> constraint
if the expression is true, then the constraints must be
satisfied
Dr. Sowmya K B
In the example below, if addr_range == small, addr will
get value less than 8.
class packet;
rand bit [3:0] addr;
string addr_range;
constraint address_range { (addr_range == "small") -> (addr < 8);}
endclass
module constr_implication;
initial
begin
packet pkt;
pkt = new();
pkt.addr_range = "small";
repeat(4)
begin
[Link]();
$display("\taddr_range = %s addr = %0d", pkt.addr_range, [Link]);
end
end
endmodule Dr. Sowmya K B
Simulator Output:
addr_range = small addr = 6
addr_range = small addr = 2
addr_range = small addr = 1
addr_range = small addr = 4
Dr. Sowmya K B
Constraint
class packet;
implication if else
rand bit [3:0] addr;
string addr_range;
constraint address_range { if(addr_range == "small") addr < 8;
else addr > 8; }
endclass
module constr_if_else;
initial begin
packet pkt; pkt = new();
pkt.addr_range = "small";
repeat(3) begin
[Link]();
$display("\taddr_range = %s addr = %0d",pkt.addr_range,[Link]);
end
pkt.addr_range = "high";
repeat(3) begin
[Link]();
$display("\taddr_range = %s addr = %0d",pkt.addr_range,[Link]);
end end endmodule Dr. Sowmya K B
Simulator Output :
addr_range = small addr = 1
addr_range = small addr = 4
addr_range = small addr = 6
addr_range = high addr = 12
addr_range = high addr = 15
addr_range = high addr = 9
Dr. Sowmya K B