INTERRUPT STRUCTURE IN 8086

An interrupt is a special condition that arises during the working of a microprocessor.

The microprocessor services it by executing a subroutine called Interrupt Service
Routine (ISR).
So, interrupt may be defined as a request to the processor to suspend the execution
of current program and execute another program (ISR) to serve a purpose.

There are three sources of interrupts for 8086:

A. Hardware interrupt-
These interrupts occur when an appropriate signal is applied on an external interrupt
pin of the microprocessor. 8086 has two pins to accept hardware interrupts, NMI and
INTR.
B. Software interrupt-
These interrupts are caused by executing a software interrupt instruction INTn,
where ‘n’ can be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can
be invoked by software. The value ‘n’ is called interrupt type.

INT0 : TYPE-0 Interrupt

INT1 : TYPE-1 Interrupt
INT32 : TYPE-32 Interrupt ETC.

C. Internal interrupts :Error conditions /Exceptions

The processor automatically generates an interrupt when a specific condition is met.
8086 is interrupted when some special conditions occur while executing certain
instructions in the program. Example: An error in division automatically causes the
INT0 interrupt. An ISR is executed in response to it to handle the problem. Similarly,
interrupt may occur when an overflow occurs, or single stepping feature has been
enabled.

All hardware interrupt and internal interrupt are associated with an interrupt type. For
example
• When an external interrupt is received in NMI line, Type-2 interrupt (INT2) will
be generated
• When divide by zero error is occurred, Tyoe-0 interrupt will be generated
• When single stepping is enabled, Type-2 interrupt will be generated and so on

When an interrupt occurs, for any reason, microprocessor executes an interrupt

instruction that transfer the control to the starting location of the corresponding
ISR. This starting addresses of the ISR are stored in a Table known as IVT
(interrupt Vector Table).
8086 has 256 interrupts and each interrupt is associated with an ISR. For 256
interrupt 256 ISR are required. 1 kilo-Bytes (256*4=1024) of memory are
required to store starting address. Each ISR requires 4 bytes of information. Two
bytes to specify the segment addresses of ISR and two bytes for Offset address
of the ISR. The address will be loaded to CS and IP to transfer the control to the
ISR.
256 interrupts are only available in 8086. The first 1kB (256*4=1024) of memory in
the 1st segment (0th segment) are required to store the staring locations of the ISRs.
This address table is known as Interrupt Vector Table (IVT). So, the address range
of IVT is from 0000H:0000H to 0000H:03FFh (or 00000H -003FFH). The structure of
IVT is shown in the table.

Structure of Interrupt Vector Table (IVT):

Vectored Location
Type Remarks
Decimal HX
1020-1023 002CH-003FFH Type 255 Pointer Available
… … … Available
… … … Available
… … … Available
… … … Available
… … … Available
… … … Available
… … … Available
… … … Available
… … … Available
132-135 00084H-00087H Type 33 Pointer Available
128-131 00080H-00083H Type 32 Pointer Available
124-127 0007CH-0007FH Type 31 Pointer RESERVED
… … … RESERVED
… … … RESERVED
… … … RESERVED
… … … RESERVED
… … … RESERVED
20-23 00014H-00017H Type 5 Pointer RESERVED
16-19 00010H-00013H Type 4 Pointer Overflow
INT Single byte
12-15 0000CH-0000FH Type 3 Pointer instruction
(Break Point)
8-11 00008H-0000BH Type 2 Pointer NMI Interrupt
4-7 00004H-00007H Type 1 Pointer Single Step
0-3 00000H-00003H Type 0 Pointer Divide error

1. The interrupt vector table contain the starting address of ISR (also called as
procedure) and is located in the first 1024 bytes of the memory at address
00000H to 003FFH (0-1023).
2. One vector location is used for an interrupt type.
3. Each interrupt vector reserves four bytes memory locations i.e., two words.
This contains the address of the ISR associated with the interrupts type.
4. The higher addressed word of the pointer contains the segment address of
the code segment containing the procedure. This is loaded to CS to point the
ISR segment. This is known as new CS.

Higher Address new CS (Upper Byte)

Pointer

new CS (Lower Byte)

new IP (Upper Byte)
Lower Address new IP (Lower Byte)
 5. The lower addressed word contains the offset address and loaded to IP. This
offset is normally referred as new IP.
6. Thus, new CS:IP provides new physical address where the ISR routine is
available.
7. As for each type, four bytes (2 for new CS and 2 for new IP) are required;
therefore, interrupt pointer table occupies the first 1k bytes (i.e., 256 x 4 =
1024 bytes) of low memory.
8. The total interrupt vector table is divided into three groups namely,
A. Dedicated interrupts (INT 0 – INT 4)
B. Reserved interrupts (INT 5 – INT 31)
C. Available interrupts (INT 32 – INT 225)

A. Dedicated interrupts (INT 0 – INT 4):

1. INT 0 (Divide Error)-

o This interrupt occurs whenever there is division error i.e., when the
result of a division is too large to be stored. This condition normally
occurs when the divisor is very small as compared to the dividend or
the divisor is zero.
o Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2. INT 1 (Single Stepping)-
o The microprocessor executes this interrupt after every instruction if the
TF is set.
o It puts microprocessor in single stepping mode i.e., the microprocessor
pauses after executing every instruction. This is very useful during
debugging.
o Its ISR generally displays contents of all registers. Its ISR address is
stored at location 1 x 4 = 00004H in the IVT.
3. INT 2 (Non maskable Interrupt)-
o The microprocessor executes this ISR in response to an interrupt on
the NMI (Non maskable Interrupt) line.
o Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4. INT 3 (Breakpoint Interrupt)-
o This interrupt is used to cause breakpoints in the program. It is caused
by writing the instruction INT 03H or simply INT.
o It is useful in debugging large programs where single stepping is
efficient.
o Its ISR is used to display the contents of all registers on the screen. Its
ISR address is stored at location 3 x 4 = 0000CH in the IVT.
5. INT 4 (Overflow Interrupt)-
o This interrupt occurs if the overflow flag is set and the microprocessor
executes the INTO (Interrupt on Overflow) instruction.
o It is used to detect overflow error in signed arithmetic operations.
o Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

B. Reserved interrupts (INT 5 – INT 31):

1. These levels are reserved by Intel to be used in higher processors like 80386,
Pentium etc. They are not available to the user.

C. Available interrupts (INT 32 – INT 225):

1. These are user defined software interrupts associated with the IO device in
the system.
 2. these ISRs are written by the users (System Designer/Programmer) to service
various IO devices.
3. These interrupts are invoked by executing the instruction INTn. Its location in
the IVT is obtained by multiplying the interrupt type with ‘4’ i.e.,𝑛 × 4.

Hardware Interrupts:

1. NMI (Non maskable interrupt)-

o This is a non-mask-able, edge triggered, high priority interrupt.
o On receiving an interrupt on NMI line, the processor executes INT2
instruction.
o Microprocessor obtains the ISR address from location 2 x 4 = 00008H
from the IVT.
o It reads 4 locations starting from this address to get the new values for
IP and CS to execute the ISR.
2. INTR-
o This is a mask-able, level triggered, low priority interrupt.
o On receiving an interrupt on INTR line, the microprocessor generates
two ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴¯ pulses.

̅̅̅̅̅̅̅ pulse: The interrupting device calculates (prepares to send) the

1st 𝐼𝑁𝑇𝐴
vector number.

̅̅̅̅̅̅̅ pulse: The interrupting device sends the vector number ‘𝑛’ to
2nd 𝐼𝑁𝑇𝐴
the microprocessor.

NOTE:
• Microprocessor multiplies the 𝑛 with 4 to get the address where the vector
location is stored. The vector locations are read and loaded to IP and CS.
This transfer the control to the ISR and the ISR is executed.
• INTR is masked or disabled when IF = 0
o CLI instruction resets the interrupt flag.
• It is unmasked or enabled when IF = 1
o STI instruction sets the interrupt flag.

The operation of interrupt

When an internal interrupt is generated, the processor automatically executes the
corresponding interrupt type. For software interrupt, the instruction of the interrupt
type is executed in a program. When an external interrupt is received in NMI line,
processor generates type-2 interrupt by executing INT2 instruction. However, when a
request is received in INTR line, the interrupting device send the interrupt type
related to the device. The steps are as follows.
• On recognizing the request received in INTR line, the processor generates two
INR cycle. An ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse is generated in each INA cycle.
• On receiving the 1st ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse, the interrupting device gets ready to send the
Interrupt Type to be executed.
• On receiving the 2nd ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse, the interrupting device the interrupt type in the
̅̅̅̅̅̅̅ pulse as the read signal.
system data bus. The processor reads it using 𝐼𝑁𝑇𝐴
• The corresponding INTn instruction is executed after reading the information
from the data bus.
• The timing diagram is shown below for reference.
 3-IDLE State
between two INTA
1st INTA cycle cycle in 8086
2nd INTA cycle

𝑇1 𝑇2 𝑇3 𝑇4 𝑇1 𝑇1 𝑇1 𝑇1 𝑇2 𝑇3 𝑇4

𝐶𝐿𝐾

𝐴𝐿𝐸

̅̅̅̅̅̅̅̅
𝐿𝑂𝐶𝐾

̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴

1st ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse 2nd ̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 pulse

𝐷7 − 𝐷0
Int type

Fig : Timing Diagram of Interrupt acknowledgement cycle.

After execution of an interrupt type, due to internal interrupt, hardware interrupt or

software interrupt, the processor performs the following.
• The contents of Flag register are pushed into the Stack
• After pushing the flags, the IF and TF flags are cleared.
o IF=0 disables INTR interrupt.
o TF0 disable single stepping feature.
• Push the content of CS (Code Segment) and IP (Instruction pointer) to stack.
o For Type0 interrupt, it points to the instruction where interrupt occur. So, it
retries the instruction again.
o For other interrupt type it push the address that point to next instruction.
o The new CS:IP (starting address of ISR) is fetched from IVT and loaded to
CS and IP register and start executing the ISR.
• At the end of ISR, it encounters IRET (return from interrupt) instruction. On
executing it
o CS:IP are retrieved from the stack and loaded to corresponding register.
o Retrieves the content of the flags to flag register.
• Thus, the processor start executing the main program from where it has left. The
conditions of Flags are same with the conditions that exists before servicing the
interrupt.

̅̅̅̅̅̅̅̅ signal is activated after 1st INA cycle to prevent Bus access by an
𝐿𝑂𝐶𝐾
external bus master. The signal is externally available in maximum mode.
However, the bus access is not granted in between two INA cycle in minimum
mode operation also.