Chapter-2
■Decoder
■Encoder
■MUX
Decoder
■ Accepts a value and decodes it
■ Output corresponds to value of n inputs
■ Consists of:
■ Inputs (n)
■ Outputs (2n , numbered from 0 → 2n - 1)
■ Selectors / Enable (active high or active low)
The truth table of 2-to-4
Decoder
2-to-4 Decoder
2-to-4 Decoder
The truth table of 3-to-8
Decoder (Remaining values in truth table will be Zeroes)
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
3-to-8 Decoder
3-to-8 Decoder with Enable
Decoder Expansion
■ Decoder expansion
■ Combine two or more small decoders with
enable inputs to form a larger decoder
■ 3-to-8-line decoder constructed from two 2-
to-4-line decoders
■ The (Most Significant Bit) MSB is connected
to the enable inputs
■ if A =0, upper is enabled; if A =1, lower is
2 2
enabled.
Decoder Expansion
Combining two 2-4 decoders to form
one 3-8 decoder using enable switch
The highest bit is used for the enables
2-to-4 Decoder: NAND
implementation
Decoder is enabled when E=0 and an output is active if
it is 0
Encoders
■ Perform the inverse operation of a
decoder
■ 2n (or less) input lines and n output
lines
Encoders
■ Perform the inverse operation of a decoder
■2n (or less) input lines and n output lines
Table: Truth Table for Octal-to-Binary
Encoders
Encoders can be implemented with OR gates whose inputs
are determined directly from the truth table. Output Ao=1 if
the input octal digit is 1 or 3 or5 or 7. Similar conditions
apply for the other two outputs. These can be expresses by the
following Boolean functions with 3 OR gates
A0 = D1 + D3 + D5 + D7;
A1 = D2 + D3 + D6 + D7;
A2 = D4 + D5 + D6 + D7;
Multiplexer (MUX)
A multiplexer can use addressing bits to
select one of several input bits to be the
output.
■ A selector chooses a single data input
and passes it to the MUX output
■ It has one output selected at a time.
Function table with enable
4 to 1 line multiplexer
4 to 1 line
multiplexer
S1 S0 F
2n MUX to 1
0 0 I0
n for this MUX is 2 0 1 I1
1 0 I2
This means 2
1 1 I3
selection lines s0
and s1
Multiplexer (MUX)
■ Consists of:
■ Inputs (multiple) = 2n
■ Output (single)
■ Selectors (# depends on # of inputs) = n
■ Enable (active high or active low)
Multiplexers versus Decoders
• A Multiplexer uses n binary select bits to choose from a
maximum of 2n unique input lines.
•Decoders have 2^n number of output lines while
multiplexers have only one output line.
•The output of the multiplexer is the data input whose index is
specified by the n bit code.
Multiplexer Versus Decoder
I3
I2
X
I1
I0
S1
S0
4-to-1 Multiplexer 2-to-4 Decoder
Note that the multiplexer has an extra OR gate. A1 and A0 are the two inputs
in decoder. There are four inputs plus two selecs in multiplexer.
Registers
• A common sequential device: Registers
– They’re a good example of sequential analysis and design
– They are also frequently used in building larger sequential circuits
• Registers hold larger quantities of data than individual flip-flops
– Registers are central to the design of modern processors
– There are many different kinds of registers
– We’ll show some applications of
these special registers
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What good are registers?
• Flip-flops are limited because they can store only one bit
• A register is an extension of a flip-flop that can store multiple bits
• Registers are commonly used as temporary storage in a processor
– They are faster and more convenient than main memory
– More registers can help speed up complex calculations
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A basic register
• Basic registers are easy to build. We can store multiple bits just by putting a bunch of flip-flops together!
• A 4-bit register is given below
– This register uses D flip-flops, so it’s easy to store data without worrying about flip-flop input
equations
– All the flip-flops share a common CLK and CLR signal
– -With each rising edge of clock pulse data is inputted as Do, D1, D2 and D3 and as D-flip-flop is used
so finally same values are retained in flip-flops so as to be generated as final output values of
Qo,Q1,Q2 and Q3
– Clear input is used for clearing all values of register 0’s before clock operation
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Adding a parallel load operation
• Tranfer of new information into a register is referred to as loading a register
• The input D3-D0 is copied to the output Q3-Q0 on every clock cycle
• How can we store the current value for more than one cycle?
• Let’s add a load input signal LD to the register
– If LD = 0, the register keeps its current contents
– If LD = 1, the register stores a new value, taken from inputs D3-D0
LD Q(t+1)
0 Q(t)
1 D3-D0
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