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Key Terms 177

• Most programmable logic devices (PLDs) are based on some form of AND array.
• Programmable link technologies are fuse, antifuse, EPROM, EEPROM, flash, and SRAM.
• A PLD can be programmed in a hardware fixture called a programmer or mounted on a
development printed circuit board.
• PLDs have an associated software development package for programming.
• Two methods of design entry using programming software are text entry (HDL) and graphic
(schematic) entry.
• ISP PLDs can be programmed after they are installed in a system, and they can be repro-
grammed at any time.
• JTAG stands for Joint Test Action Group and is an interface standard (IEEE Std. 1149.1) used
for programming and testing PLDs.
• An embedded processor is used to facilitate in-system programming of PLDs.
• In PLDs, the circuit is programmed in and can be changed by reprogramming.
• The average power dissipation of a logic gate is
ICCH + ICCL
PD = VCC ¢ ≤
2
• The speed-power product of a logic gate is
SPP = tpPD
• As a rule, CMOS has a lower power consumption than bipolar.
• In fixed-function logic, the circuit cannot be altered.

Key Terms
Key terms and other bold terms in the chapter are defined in the end-of-book glossary.
AND array An array of AND gates consisting of a matrix of programmable interconnections.
AND gate A logic gate that produces a HIGH output only when all of the inputs are HIGH.
Antifuse A type of PLD nonvolatile programmable link that can be left open or can be shorted
once as directed by the program.
Bipolar A class of integrated logic circuits implemented with bipolar transistors; also known as TTL.
Boolean algebra The mathematics of logic circuits.
CMOS Complementary metal-oxide semiconductor; a class of integrated logic circuits that is
­implemented with a type of field-effect transistor.
Complement The inverse or opposite of a number. LOW is the complement of HIGH, and 0 is
the complement of 1.
EEPROM A type of nonvolatile PLD reprogrammable link based on electrically erasable
­programmable read-only memory cells and can be turned on or off repeatedly by programming.
EPROM A type of PLD nonvolatile programmable link based on electrically programmable
read-only memory cells and can be turned either on or off once with programming.
Exclusive-NOR (XNOR) gate A logic gate that produces a LOW only when the two inputs are at
opposite levels.
Exclusive-OR (XOR) gate A logic gate that produces a HIGH output only when its two inputs
are at opposite levels.
Fan-out The number of equivalent gate inputs of the same family series that a logic gate can drive.
Flash A type of PLD nonvolatile reprogrammable link technology based on a single transistor cell.
Fuse A type of PLD nonvolatile programmable link that can be left shorted or can be opened once
as directed by the program.
Inverter A logic circuit that inverts or complements its input.
JTAG Joint Test Action Group; an interface standard designated IEEE Std. 1149.1.
NAND gate A logic gate that produces a LOW output only when all the inputs are HIGH.
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178 Logic Gates

NOR gate A logic gate in which the output is LOW when one or more of the inputs are HIGH.
OR gate A logic gate that produces a HIGH output when one or more inputs are HIGH.
Propagation delay time The time interval between the occurrence of an input transition and the
occurrence of the corresponding output transition in a logic circuit.
SRAM A type of PLD volatile reprogrammable link based on static random-access memory cells
and can be turned on or off repeatedly with programming.
Target device A PLD mounted on a programming fixture or development board into which a
software logic design is to be downloaded.
Truth table A table showing the inputs and corresponding output(s) of a logic circuit.
Unit load A measure of fan-out. One gate input represents one unit load to the output of a gate
within the same IC family.
VHDL A standard hardware description language that describes a function with an entity/
architecture structure.

True/False Quiz
Answers are at the end of the chapter.
1. An inverter performs a NOT operation.
2. A NOT gate cannot have more than one input.
3. If any input to an OR gate is zero, the output is zero.
4. If all inputs to an AND gate are 1, the output is 0.
5. A NAND gate can be considered as an AND gate followed by a NOT gate.
6. A NOR gate can be considered as an OR gate followed by an inverter.
7. The output of an exclusive-OR is 0 if the inputs are opposite.
8. Two types of fixed-function logic integrated circuits are bipolar and NMOS.
9. Once programmed, PLD logic can be changed.
10. Fan-out is the number of similar gates that a given gate can drive.

Self-Test
Answers are at the end of the chapter.
1. When the input to an inverter is LOW (0), the output is
(a) HIGH or 0 (b) LOW or 0 (c) HIGH or 1 (d) LOW or 1
2. An inverter performs an operation known as
(a) complementation (b) assertion (c) inversion (d) both answers (a) and (c)
3. The output of an AND gate with inputs A, B and C is 0 (LOW) when
(a) A = 0, B = 0, C = 0 (b) A = 0, B = 1, C = 1 (c) both answers (a) and (b)
4. The output of an OR gate with inputs A, B and C is 0 (LOW) when
(a) A = 0, B = 0, C = 0 (b) A = 0, B = 1, C = 1 (c) both answers (a) and (b)
5. A pulse is applied to each input of a 2-input NAND gate. One pulse goes HIGH at t = 0 and
goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at
t = 3 ms. The output pulse can be described as follows:
(a) It goes LOW at t = 0 and back HIGH at t = 3 ms.
(b) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.
(c) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.
(d) It goes LOW at t = 0.8 ms and back LOW at t = 1 ms.
6. A pulse is applied to each input of a 2-input NOR gate. One pulse goes HIGH at t = 0 and
goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at
t = 3 ms. The output pulse can be described as follows:
(a) It goes LOW at t = 0 and back HIGH at t = 3 ms.
(b) It goes LOW at t = 0.8 ms and back HIGH at t = 3 ms.
(c) It goes LOW at t = 0.8 ms and back HIGH at t = 1 ms.
(d) It goes HIGH at t = 0.8 ms and back LOW at t = 1 ms.
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Problems 179

7. A pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t = 0 and
goes back LOW at t = 1 ms. The other pulse goes HIGH at t = 0.8 ms and goes back LOW at
t = 3 ms. The output pulse can be described as follows:
(a) It goes HIGH at t = 0 and back LOW at t = 3 ms.
(b) It goes HIGH at t = 0 and back LOW at t = 0.8 ms.
(c) It goes HIGH at t = 1 ms and back LOW at t = 3 ms.
(d) both answers (b) and (c)
8. A positive-going pulse is applied to an inverter. The time interval from the leading edge of the
input to the leading edge of the output is 7 ns. This parameter is
(a) speed-power product (b) propagation delay, tPHL
(c) propagation delay, tPLH (d) pulse width
9. Most PLDs utilize an array of
(a) NOT gates
(b) NOR gates
(c) OR gates
(d) AND gates
10. The rows and columns of the interconnection matrix in an SPLD are connected using
(a) fuses (b) switches
(c) gates (d) transistors
11. An antifuse is formed using
(a) two insulators separated by a conductor (b) two conductors separated by an insulator
(c) an insulator packed beside a conductor (d) two conductors connected in a series
12. An EPROM can be programmed using
(a) transistors (b) diodes
(c) a multiprogrammer (d) a device programmer
13. Two ways to enter a logic design using PLD development software are
(a) text and numeric (b) text and graphic
(c) graphic and coded (d) compile and sort
14. JTAG stands for
(a) Joint Test Action Group (b) Java Top Array Group
(c) Joint Test Array Group (d) Joint Time Analysis Group
15. In-system programming of a PLD typically utilizes
(a) an embedded clock generator (b) an embedded processor
(c) an embedded PROM (d) both (a) and (b)
(e) both (b) and (c)
16. To measure the period of a pulse waveform, you must use
(a) a DMM (b) a logic probe
(c) an oscilloscope (d) a logic pulser
17. Once you measure the period of a pulse waveform, the frequency is found by
(a) using another setting (b) measuring the duty cycle
(c) finding the reciprocal of the period (d) using another type of instrument

Problems
Answers to odd-numbered problems are at the end of the book.

Section 3–1 The Inverter

1. The input waveform shown in Figure 3–76 is applied to a system of two inverters connected in
a series. Draw the output waveform across each inverter in proper relation to the input.

HIGH
VIN
LOW
FIGURE 3–76
fg03_07400
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180 Logic Gates

2. A combination of inverters is shown in Figure 3–77. If a LOW is applied to point A, determine

the net output at points E and F.

B C D
A E

FIGURE 3–77
fg03_07500
3. If the waveform in Figure 3–76 is applied to point A in Figure 3–77, determine the waveforms
at points B through F.

Section 3–2 The and Gate

4. Draw the rectangular outline symbol for a 3-input AND gate.
5. Determine the output, X, for a 2-input AND gate with the input waveforms shown in Figure
3–78. Show the proper relationship of output to inputs with a timing diagram.

A
X
B

FIGURE 3–78
fg03_07600
6. The waveforms in Figure 3–79 are applied to points A and B of a 2-input AND gate followed
by an inverter. Draw the output waveform.

FIGURE 3–79
fg03_07700
7. The input waveforms applied to a 3-input AND gate are as indicated in Figure 3–80. Show the
output waveform in proper relation to the inputs with a timing diagram.

A
A
B B X
C

FIGURE 3–80
fg03_07800
8. The input waveforms applied to a 4-input AND gate are as indicated in Figure 3–81. The
output of the AND gate is fed to an inverter. Draw the net output waveform of this system.

A
B X
C
D

FIGURE 3–81
fg03_07900
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Problems 181

Section 3–3 The OR Gate

9. Draw the rectangular outline symbol for a 3-input OR gate.
10. Write the expression for a 4-input OR gate with inputs A, B, C, D, and output X.
11. Determine the output for a 2-input OR gate when the input waveforms are as in Figure 3–79
and draw a timing diagram.
12. Repeat Problem 7 for a 3-input OR gate.
13. Repeat Problem 8 for a 4-input OR gate.
14. For the waveforms given in Figure 3–82, A and B are ANDed with output F, D and E are ANDed
with output G, and C, F, and G are ORed. Draw the net output waveform.

FIGURE 3–82
fg03_08000
15. Draw the rectangular outline symbol for a 4-input OR gate.
16. Show the truth table for a system of a 3-input OR gate followed by an inverter.

Section 3–4 The NAND Gate

17. For the set of input waveforms in Figure 3–83, determine the output for the gate shown and
draw the timing diagram.

A
X
B

FIGURE 3–83
fg03_08100
18. Determine the gate output for the input waveforms in Figure 3–84 and draw the timing
diagram.

A
B B X
C

FIGURE 3–84
fg03_08200
19. Determine the output waveform in Figure 3–85.

B A
B X
C
C D
D

FIGURE 3–85
fg03_08300
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182 Logic Gates

20. As you have learned, the two logic symbols shown in Figure 3–86 represent equivalent
operations. The difference between the two is strictly from a functional viewpoint. For the
NAND symbol, look for two HIGHs on the inputs to give a LOW output. For the negative-
OR, look for at least one LOW on the inputs to give a HIGH on the output. Using these
two functional viewpoints, show that each gate will produce the same output for the given
inputs.

A
A X
B

B
A
X
B

FIGURE 3–86
fg03_08400

Section 3–5 The NOR Gate

21. Repeat Problem 17 for a 2-input NOR gate.
22. Determine the output waveform in Figure 3–87 and draw the timing diagram.

A
A
B B X
C
C

FIGURE 3–87
fg03_08500

23. Repeat Problem 19 for a 4-input NOR gate.

24. The NAND and the negative-OR symbols represent equivalent operations, but they are func-
tionally different. For the NOR symbol, look for at least one HIGH on the inputs to give a
LOW on the output. For the negative-AND, look for two LOWs on the inputs to give a HIGH
output. Using these two functional points of view, show that both gates in Figure 3–88 will
produce the same output for the given inputs.

A
X
A B

B A
X
B
FIGURE 3–88
fg03_08600

Section 3–6 The Exclusive-OR and Exclusive-NOR Gates

25. How does an exclusive-OR gate differ from an OR gate in its logical operation?
26. Repeat Problem 17 for an exclusive-OR gate.
27. Repeat Problem 17 for an exclusive-NOR gate.
28. Determine the output of an exclusive-NOR gate for the inputs shown in Figure 3–79 and draw
a timing diagram.
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Problems 183

Section 3–7 Programmable Logic

29. In the simple programmed AND array with programmable links in Figure 3–89, determine the
Boolean output expressions.

A A B B

X1

X2

X3

FIGURE 3–89
fg03_09100

30. Determine by row and column number which fusible links must be blown in the program-
mable AND array of Figure 3–90 to implement each of the following product terms:
X1 = ABC, X2 = ABC, X3 = ABC.

A A B B C C

2 X1

5 X2

8 X3

1 2 3 4 5 6
FIGURE 3–90
fg03_09200

31. Describe a 4-input AND gate using VHDL.

32. Describe a 5-input NOR gate using VHDL.
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184 Logic Gates

Section 3–8 Fixed-Function Logic Gates

33. In the comparison of certain logic devices, it is noted that the power dissipation for one particular
type increases as the frequency increases. Is the device bipolar or CMOS?
34. Using the data sheets in Figures 3–65 and 3–66, determine the following:
(a) 74LS00 power dissipation at maximum supply voltage and a 50% duty cycle
(b) Minimum HIGH level output voltage for a 74LS00
(c) Maximum propagation delay for a 74LS00
(d) Maximum LOW level output voltage for a 74HC00A
(e) Maximum propagation delay for a 74HC00A
35. Determine tPLH and tPHL from the oscilloscope display in Figure 3–91. The readings indicate
volts/div and sec/div for each channel.

Input

Output

Ch1 2 V Ch2 2 V 5 ns

FIGURE 3–91
fg03_08700

36. Gate A has tPLH = tPHL = 6 ns. Gate B has tPLH = tPHL = 10 ns. Which gate can be operated
at a higher frequency?
37. If a logic gate operates on a dc supply voltage of 15 V and draws an average current of 4 mA,
what is its power dissipation?
38. The variable ICCH represents the dc supply current from VCC when all outputs of an IC are
HIGH. The variable ICCL represents the dc supply current when all outputs are LOW. For a
74LS00 IC, determine the typical power dissipation when all four gate outputs are HIGH.
(See data sheet in Figure 3–66.)

Section 3–9 Troubleshooting

39. Examine the conditions indicated in Figure 3–92, and identify the faulty gates.

0
1 1 0 0 1 1
0 1 1 0 0 0 0
1 0 0 0 0 1
1
(a) (b) (c) (d) (e) (f)
FIGURE 3–92
fg03_08800
40. Determine the faulty gates in Figure 3–93 by analyzing the timing diagrams.

A A A
A
B B B B

X X X X
(a) (b) (c) (d)
FIGURE 3–93
fg03_08900
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Problems 185

41. Using an oscilloscope, you make the observations indicated in Figure 3–94. For each observa-
tion determine the most likely gate failure.

Input Input
HIGH
HIGH
+VCC +VCC

GND GND
(a)

HIGH HIGH Input HIGH Input

GND GND

+VCC +VCC
(b)
FIGURE 3–94

42. The seat belt alarm circuit in Figure 3–17 has malfunctioned. You find that when the ignition
switch is turned on and the seat belt is unbuckled, the alarm comes on and will not go off. What
is the most likely problem? How do you troubleshoot it?
43. Every time the ignition switch is turned on in the circuit of Figure 3–17, the alarm comes on
for thirty seconds, even when the seat belt is buckled. What is the most probable cause of this
malfunction?
44. What failure(s) would you suspect if the output of a 3-input NAND gate stays HIGH no matter
what the inputs are?
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186 Logic Gates

Special Design Problems

45. Modify the frequency counter in Figure 3–16 to operate with an enable pulse that is active-
LOW rather than HIGH during the 1 ms interval.
46. Assume that the enable signal in Figure 3–16 has the waveform shown in Figure 3–95. Assume
that waveform B is also available. Devise a circuit that will produce an active-HIGH reset pulse
to the counter only during the time that the enable signal is LOW.

Enable

FIGURE 3–95
47. Design a circuit to fit in the beige block fg03_09300
of Figure 3–96 that will cause the headlights of an
automobile to be turned off automatically 15 s after the ignition switch is turned off, if the light
switch is left on. Assume that a LOW is required to turn the lights off.
LOW turns off the lights.

Ignition HIGH = On
switch LOW = Off
Headlight
control
Light HIGH = On
switch LOW = Off

FIGURE 3–96
48. Modify the logic circuit for the intrusionfg03_09400
alarm in Figure 3–25 so that two additional rooms,
each with two windows and one door, can be protected.
49. Further modify the logic circuit from Problem 48 for a change in the input sensors where
Open = LOW and Closed = HIGH.
50. Sensors are used to monitor the pressure and the temperature of a chemical solution stored in a
vat. The circuitry for each sensor produces a HIGH voltage when a specified maximum value is
exceeded. An alarm requiring a LOW voltage input must be activated when either the pressure
or the temperature is excessive. Design a circuit for this application.
51. In a certain automated manufacturing process, electrical components are automatically inserted
in a PCB. Before the insertion tool is activated, the PCB must be properly positioned, and
the component to be inserted must be in the chamber. Each of these prerequisite conditions is
indicated by a HIGH voltage. The insertion tool requires a LOW voltage to activate it. Design a
circuit to implement this process.

Multisim Troubleshooting Practice

52. Open file P03-52. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
53. Open file P03-53. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
54. Open file P03-54. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.
55. Open file P03-55. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.

Answers
Section Checkups
Section 3–1 The Inverter
1. When the inverter input is 1, the output is 0.
2. (a)

(b) A negative-going pulse is on the output (HIGH to LOW and back HIGH).
ua03_00200
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Answers 187

Section 3–2 The AND Gate

1. An AND gate output is HIGH only when all inputs are HIGH.
2. An AND gate output is LOW when one or more inputs are LOW.
3. Five-input AND: X = 1 when ABCDE = 11111, and X = 0 for all other combinations of
ABCDE.

Section 3–3 The OR Gate

1. An OR gate output is HIGH when one or more inputs are HIGH.
2. An OR gate output is LOW only when all inputs are LOW.
3. Three-input OR: X = 0 when ABC = 000, and X = 1 for all other combinations of ABC.

Section 3–4 The NAND Gate

1. A NAND gate output is LOW only when all inputs are HIGH.
2. A NAND gate output is HIGH when one or more inputs are LOW.
3. NAND: active-LOW output for all HIGH inputs; negative-OR: active-HIGH output for one or
more LOW inputs. They have the same truth tables.
4. X = ABC

Section 3–5 The NOR Gate

1. A NOR gate output is HIGH only when all inputs are LOW.
2. A NOR gate output is LOW when one or more inputs are HIGH.
3. NOR: active-LOW output for one or more HIGH inputs; negative-AND: active-HIGH output
for all LOW inputs. They have the same truth tables.
4. X = A + B + C

Section 3–6 The Exclusive-OR and Exclusive-NOR Gates

1. An XOR gate output is HIGH when the inputs are at opposite levels.
2. An XNOR gate output is HIGH when the inputs are at the same levels.
3. Apply the bits to the XOR gate inputs; when the output is HIGH, the bits are different.

Section 3–7 Programmable Logic

1. Fuse, antifuse, EPROM, EEPROM, flash, and SRAM
2. Volatile means that all the data are lost when power is off and the PLD must be reprogrammed;
SRAM-based
3. Text entry and graphic entry
4. JTAG is Joint Test Action Group; the IEEE Std. 1149.1 for programming and test interfacing.
5. entity NORgate is
port (A, B, C: in bit; X: out bit);
end entity NORgate;
architecture NORfunction of NORgate is
begin
X < = A nor B nor C;
end architecture NORfunction;
6. entity XORgate is
port (A, B: in bit; X: out bit);
end entity XORgate;
architecture XORfunction of XORgate is
begin
X < = A xor B;
end architecture XORfunction;

Section 3–8 Fixed-Function Logic Gates

1. Fixed-function logic cannot be changed. PLDs can be programmed for any logic function.
2. CMOS and bipolar (TTL)
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188 Logic Gates

3. (a) LS—Low-power Schottky

(b) HC—High-speed CMOS
(c) HCT—HC CMOS TTL compatible
4. Lowest power—CMOS
5. Six inverters in a package; four 2-input NAND gates in a package
6. tPLH = 10 ns; tPHL = 8 ns
7. 18 pJ
8. ICCL—dc supply current for LOW output state; ICCH—dc supply current for HIGH output state
9. VIL—LOW input voltage; VIH—HIGH input voltage
10. VOL—LOW output voltage; VOH—HIGH output voltage

Section 3–9 Troubleshooting

1. Opens and shorts are the most common failures.
2. An open input which effectively makes input HIGH
3. Amplitude and period

Related Problems for Examples

3–1 The timing diagram is not affected.
3–2 See Table 3–15.

TABLE 3–15
Inputs Output Inputs Output
ABCD X ABCD X

0000 0 1000 0
0001 0 1001 0
0010 0 1010 0
0011 0 1011 0
0100 0 1100 0
0101 0 1101 0
0110 0 1110 0
0111 0 1111 1

3–3 See Figure 3–97.

FIGURE 3–97
3–4 The output waveform is the same as input A.
fg03_09500
3–5 See Figure 3–98.
3–6 Results are the same as example.
3–7 See Figure 3–99.
A

B
A
C
B
X

C = HIGH X

FIGURE 3–98 FIGURE 3–99

fg03_09600 fg03_09700
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Answers 189

3–8 See Figure 3–100.

3–9 See Figure 3–101.

B
A
C
B
X
X C = LOW
FIGURE 3–100 FIGURE 3–101
fg03_09800 fg03_09900
3–10 See Figure 3–102.
3–11 See Figure 3–103.

A B

B C

X X

FIGURE 3–102 FIGURE 3–103

fg03_10000 fg03_10100
3–12 Use a 3-input NAND gate.
3–13 Use a 4-input NAND gate operating as a negative-OR gate.
3–14 See Figure 3–104.

FIGURE 3–104
fg03_10200
3–15 See Figure 3–105.
3–16 See Figure 3–106.

A B

B C

X X

FIGURE 3–105 FIGURE 3–106

fg03_10300 fg03_10400
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190 Logic Gates

3–17 Use a 2-input NOR gate.

3–18 A 3-input NAND gate.
3–19 The output is always LOW. The output is a straight line.
3–20 The exclusive-OR gate will not detect simultaneous failures if both circuits produce the
same outputs.
3–21 The outputs are unaffected.
3–22 6 columns, 9 rows, and 3 AND gates with three inputs each
3–23 The gate with 4 ns tPLH and tPHL can operate at the highest frequency.
3–24 10 mW
3–25 The gate output or pin 13 input is internally open.
3–26 The display will show an erratic readout because the counter continues until reset.
3–27 The enable pulse is too short or the counter is reset too soon.

True/False Quiz
1. T   2. T   3. F   4. F    5. T
6. T   7. F   8. F   9. T   10. T

Self-Test
1. (c)   2. (d)   3. (c)   4. (a)   5. (c)   6. (a)   7. (d)   8. (b)   9. (d)
10. (a)   11. (b)   12. (d)   13. (b)   14. (a)   15. (d)   16. (c)   17. (c)