[Link].

in ASIC Verification using

System Verilog
Presented by:
Dr. Vasudeva Bevara
Dept. of ECE

Humility | Entrepreneurship | Teamwork & Respect for Individual | Deliver the Promise | Learning & Inner Excellence | Social Responsibility | Financial Prudence - Frugality
 Unit-III

11 March 2025 System Verilog 2

 Background
⚫ In a Procedural Programming (PP), program is written in a step by
step approach. At the end of the program or subroutine, tasks get
executed in a sequential manner
⚫ PP focuses on breaking down a programming task into a collection of
variables, data structures and subroutines where the later two can
act on as many variables declared in the program.
⚫ Variables can easily be modified by any member of a program
⚫ Object Oriented Programming (OOP) focuses on breaking down a
task into units known as objects where each one includes its own
variables (data) and subroutines (methods).
⚫ PP uses subroutines and other members to act on program data
structures whereas in OOP, object subroutines act on object data

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 ⚫ Nomenclature varies between the two paradigms but have the same
semantics

PP OOP
variable attribute
function method
argument message
module object

⚫ In OOP, each object is capable of receiving messages, processing

data and sending messages to other objects

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 Advantages of OOP
⚫ OOP simulates real world objects th4us providing easy understanding
and visualization of problems as well as the designs of the solutions.
Complexity of problems is reduced, program structures become clear.
⚫ Easy modification (maintenance) of the system. This is because objects
are interacting through public interfaces allowing modifications in their
implementations without affecting the overall performances of the
system provided that modifications do not affect their functionalities.
⚫ Modularity allows scalability of the system. More functionalities of the
system can be easily added at any time if modeled in form of objects.
⚫ Reusability of code is practiced at highest level with OOP. Objects can be
reused as many times as needed and can also be used to solve similar
problems.
⚫ Security of the program is much enhanced due to limitations of object
data from being accessed by other objects.

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 ⚫ Using OOP ;
o The overall program is made up of lots of different self-contained
components (objects),
o each object has a specific role in the program

o all objects can talk to each other in predefined ways.

Overview of Object and Class

⚫ Object is the smallest element of a program designed to simulate a
real world object presented by the problem.
⚫ A given problem can be broken down into unlimited number of
objects.
⚫ Each object is designed and coded independently according to what
they actually represented in a real world.
⚫ To deliver the overall program task, objects communicate through
messages.

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 ⚫ Objects have a standard structure; must have attributes and methods
(functions).
⚫ Attributes/variables/data define s7pecifications of objects while
methods define the functionalities offered by objects. Methods are
said to explain behaviors of objects.
⚫ Methods make use of attributes of the same object to define different
behaviors of the object.
⚫ For example
 Dog

⯍ Attributes – name, age, colour, breed, etc.

⯍ Behaviour – eat, go for a walk, wiggle tail, etc.
 Car

⯍ Attributes – make, engine size, colour, gear system, speed, etc

⯍ Behaviour – change gear, change speed, stop, etc.
 Person

⯍ ???

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 ⚫ Class is an abstract of objects or can be also defined as a collection of
objects possessing similar general properties.
⚫ Classes have similar structure as t8hat of objects, the difference
between them being the degree of specification.
⚫ Attributes of objects carry specific values while those of classes are
assigned to either general or default ones.
⚫ Several objects can belong to the same class.

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Classes are like “templates” for a particular set of objects
9

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 ⚫ A class is a generic template for a set of objects with similar features.
⚫ Instance of a class = object
⚫ If class is the general (generic) re1p0resentation of an object, an
instance is its concrete representation.
⚫ Another way of distinguishing classes from objects is:
 A class exists at design time, i.e. when we are writing OO code to
solve problems.
 An object exists at runtime when the program that we have just
coded is running.

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 ⚫ Example – address book. For each person we want to store:
 Name
 Age
 Address
 Phone number

⚫ We can write a class called Person which will represent the abstract
concept of a Person.

⚫ We will then be able to create as much Person objects as we like in

order to model our address book.
 All of these objects will be an instance of our Person class.

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SystemVerilog is a object oriented programming and to understand the
functionality of OOP in SystemVerilog, we first need to understand several
fundamentals related to objects. These include class, method, inheritance,
encapsulation, abstraction, polymorphism etc.
Class:
It is the central point of OOP and that contains data and codes with
behavior. In SystemVerilog OOPS , everything happens within class and it
describes a set of objects with common behavior. The class definition
describes all the properties, behavior, and identity of objects present
within that class.
Object:
Objects are the basic unit of object orientation with behavior, identity. As we 12
mentioned above, these are part of a class but are not the same. An object is
expressed by the variable and methods within the objects. Again these
variables and methods are distinguished from each other as instant variables,
instant methods and class variable and class methods.
Methods:
We know that a class can define both attributes and behaviors. Again attributes
are defined by variables and behaviors are represented by methods. In other
words, methods define the abilities of an object.
Inheritance:
This is the mechanism of organizing and structuring program. Though objects are
distinguished from each other by some additional features but there are objects
that share certain things common. In object oriented programming classes can
inherit some common behavior and state from others. Inheritance in OOP allows
to define a general class and later to organize some other classes simply adding
some details with the old class definition. This saves work as the special class
13
inherits all the properties of the old general class and as a programmer you only
require the new features. This helps in a better data analysis, accurate coding and
reduces development time.
Abstraction:
The process of abstraction in SystemVerilog is used to hide certain details and
only show the essential features of the object. In other words, it deals with the
outside view of an object.
Encapsulation:
This is an important programming concept that assists in separating an object's
state from its behavior. This helps in hiding an object's data describing its state
from any further modification by external component. In SystemVerilog there are
three different terms used for hiding data constructs and these are public, private
and protected . As we know an object can associated with data with predefined
classes and in any application an object can know about the data it needs to know 14
about. So any unnecessary data are not required by an object can be hidden by
this process. It can also be termed as information hiding that prohibits outsiders in
seeing the inside of an object in which abstraction is implemented.
Polymorphism:
It describes the ability of the object in belonging to different types with
specific behavior of each type. So by using this, one object can be treated
like another and in this way it can create and define multiple level of
interface. Here the programmers need not have to know the exact type of
object in advance and this is being implemented at runtime.

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 Class
A class is the implementation of an abstract data type . It defines attributes and
methods which implement the data structure and operations of the abstract data
type, respectively. Instances of classes are called objects. Consequently, classes
define properties and behavior of sets of objects.

Syntax for class:

class A ;
// attributes:
16
int i
// methods:
task print ()
endclass
 Object:
An object is an instance of a class. It can be uniquely identified by its name and it
defines a state which is represented by the values of its attributes at a particular
time.

class simple ;
int i, j; obj_1 = new();
task printf(); obj_2 = new();
$display( i , j ); obj_1.i = 2;
// Simulation results:
endtask obj_1.j = 5;
2 5
endclass obj_2.i = 4;
4 0
obj_1.printf();
program main; obj_2.printf();
initial begin end
simple obj_1; endprogram 117
simple obj_2;
 Declaration of objects:
//Example of declaration objects:
Packet pkt;
Driver driv;

If you declare pkt like this, its value will be undetermined until an object is
actually created and assigned to it using the new method. Simply declaring a
reference variable does not create an object. For that, you need to use the new
operator. You must assign an object to pkt before you use it in your code.
Otherwise, you will get a compiler error.

Creating objects:
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//Example of creating objects:
Packet pkt = new();
Driver driv = new();
class packet ; class packet ;
int length = 0; int length = 0;
function new (int l); function new (int l);
length = l; length = l;
endfunction endfunction
endclass endclass

program main; program main;

initial begin initial begin
packet pkt; packet pkt;
[Link] = 10; packet pkt = new(10);
end end
endprogram endprogram
19
// Simulation results: // Simulation results:
Error: null object access Length = 10
 This
‘this’ keyword is used to refer to class properties. this keyword is used to
unambiguously refer to class properties or methods of the current instance. this is a
pre-defined class handle referring to the object from which it is used,
calling [Link] means [Link].

• this keyword shall only be used within non-static class methods

• this keyword refers to the object handle in which it is invoked

12
0
class packet;
byte a
Compiler gets confused on which is the class
byte b;
variable
function void data(byte a, b);
a = a;
a = b; Using this will solve the issue
endfunction this.a = a;
this.b = b;
endclass

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 class packet;
bit [31:0] addr;
bit [31:0] data;
bit write;
string pkt_type;

function new(bit [31:0] addr,data,bit write,string pkt_type);

addr = addr;
data = data; module sv_constructor;
write = write; packet pkt;
pkt_type = pkt_type; initial begin
endfunction pkt = new(32'h10,32'hFF,1,"GOOD_P
KT");
function void display(); [Link]();
$display("\t addr = %0h",addr); end
$display("\t data = %0h",data); endmodule
$display("\t write = %0h",write);
$display("\t pkt_type = %0s",pkt_type);
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endfunction 2
endclass
The addr, data, write and pkt_type are the property of both class and an argument
to the function new, as the name in both are [Link] will lead to an ambiguity
in assignment and values will not be assigned properly.

// simulation result
addr = 0
data = 0
write = 0
pkt_type =

The above problem can be overcome by using “this” keyword to the

class properties.

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3
 class packet; // simulation result
bit [31:0] addr; addr = 10
bit [31:0] data; data = ff
bit write; write = 1
string pkt_type; pkt_type = GOOD_PKT

function new(bit [31:0] addr,data,bit write,string pkt_type);

[Link] = addr;
[Link] = data; module sv_constructor;
[Link] = write; packet pkt;
this.pkt_type = pkt_type; initial begin
endfunction pkt = new(32'h10,32'hFF,1,"GOOD_P
KT");
function void display(); [Link]();
$display("\t addr = %0h",addr); end
$display("\t data = %0h",data); endmodule
$display("\t write = %0h",write);
$display("\t pkt_type = %0s",pkt_type);
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endfunction 4
endclass
 Class Structure
//basic class construct
class ClassName {

//Attributes (identity section)

//Methods (behavior section)
}

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Creating class

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Creating class

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Creating object

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Creating New Objects

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Creating New Objects

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Creating New Objects

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Creating New Objects

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Creating New Objects

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Creating New Objects

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Inheritance

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Inheritance

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Inheritance

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Virtual/Abstract class

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Creating Objects

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Creating Objects

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Accessing Static Variables Through the Class Name

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Static Variables

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Static Variables Vs Global Variables

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this

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super to access the base class methods

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Inheritance

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Inheritance

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Assign Parent class handle to child class handle

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Routines outside the class

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Scope Resolution

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Scope Resolution

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Virtual Method

•Virtual methods allow you to write flexible and reusable code by enabling derived classes to
customize the behavior of methods inherited from a base class.
Using One-Class Inside Another

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Using One-Class Inside Another & Shallow copy
In SystemVerilog, you can define a class inside another class, which is known as a nested class.
This allows you to encapsulate related functionality within a parent class. Here's an example:
class OuterClass; module test;
int outer_var; initial begin
// Nested class definition OuterClass outer_obj = new(); //
class InnerClass; Create an instance of the outer class
int inner_var; outer_obj.outer_var = 10;
function void display(); outer_obj.inner_obj.inner_var = 20;
$display("InnerClass: inner_var = %0d", inner_var);
endfunction outer_obj.display(); // Display values
endclass from both outer and inner classes
// Declare an instance of the nested class end
InnerClass inner_obj; endmodule
function new();
inner_obj = new(); // Create an instance of the inner class
endfunction
OuterClass: outer_var = 10
function void display();
$display("OuterClass: outer_var = %0d", outer_var);
InnerClass: inner_var = 20
inner_obj.display(); // Call the nested class method
endfunction
endclass

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Using One-Class Inside Another

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Using One-Class Inside Another

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Using One-Class Inside Another

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Dynamic Objects
In SystemVerilog, dynamic objects refer to objects that are created at runtime using the
new() constructor. Unlike static objects, which are allocated at compile time, dynamic
objects allow for flexible memory management and are particularly useful when the
number of objects needed is not known in advance.

Key Concepts:
Dynamic Allocation: Objects are created using the new() method.

Memory Management: SystemVerilog does not have automatic garbage collection, so you
must explicitly manage memory (e.g., avoid memory leaks).

Handles: A handle is a reference to an object. You can create multiple handles to

dynamically allocate objects.

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Dynamic Objects

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Dynamic Objects

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Dynamic Objects

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Dynamic Objects

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Copying Objects

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Copying Objects

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Connecting the Test bench and Design

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Clocking block

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 Clocking blocks
SystemVerilog adds the clocking block that identifies clock signals, and captures
the timing and synchronization requirements of the blocks being modeled. A
clocking block assembles signals that are synchronous to a particular clock, and
makes their timing explicit. The clocking block is a key element in a cycle-based
methodology, which enables users to write testbenches at a higher level of
abstraction. Simulation is faster with cycle based methodology.
Depending on the environment, a testbench can contain one or more clocking
blocks, each containing its own clock plus an arbitrary number of signals. These
85
operations are as follows:
• Synchronous events
• Input sampling
• Synchronous drives 10
Syntax for Clocking block:

clocking cb @(posedge clk);

default input #10ns output #2ns;
output read,enable,addr;
input negedge data;
endclocking

In the above example, the first line declares a clocking block called cb that is to
be clocked on the positive edge of the signal clk. The second line specifies that
by default all signals in the clocking block shall use a 10ns input skew and a 2ns
output skew by default. The next line adds three output signals to the clocking
block: read, enable and addr. The fourth line adds the signal data to the clocking
block as input. Fourth line also contains negedge which overrides the skew ,so
that data is sampled on the negedge of the clk.

10
6
 Skew
If an input skew is specified then the signal is sampled at skew time units
before the clock event. If output skew is specified, then output (or inout)
signals are driven skew time units after the corresponding clock event. A
skew must be a constant expression, and can be specified as a parameter.

Signals sampled here Signals driven here

Input skew Output skew

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7
If skew is not specified, default input skew is 1step and output skew is 0. Specifying
a clocking block using a SystemVerilog interface can significantly reduce the
amount of code needed to connect the TestBench without race condition. Clocking
blocks add an extra level of signal hierarchy while accessing signals.

interface intf (input clk);

logic read, enable, logic [7:0] addr,data;

clocking cb @(posedge clock); // clocking block for testbench

default input #10ns output #2ns;
output read,enable,addr;
input data;
endclocking

modport dut (input read,enable,addr,output data);

modport tb (clocking cb);
endinterface :intf
10
8
Skew can be specified in 3 ways.
#d : The skew is d time units. The time unit depends on the timescale of the block.
#dns : The skew is d nano seconds.
#1step : Sampling is done in the preponed region of current time stamp.

Cycle delay:
The ## operator can be used to delay execution by a specified number of
clocking events, or clock cycles. What constitutes a cycle is determined by the
default clocking in effect of module, interface, or program.

// Syntax for clock delay

## <integer expression>;

##3; // wait 3 cycles

##1 tb_if.addr <= 8'h00;// waits for 1 cycle and then writes address.

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9
Clocking block

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Clocking block

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Clocking block

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Clocking block

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Clocking block

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Clocking block

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Clocking block

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Clocking block

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Interface

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Clocking Block

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Clocking Block

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Clocking Block

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Interface Driving and Sampling

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Program-module

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Program-module

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Program-module

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Program-module

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 Thank you …

11 March 2025 VLSI Design & Career Scope