ARM INSTRUCTION SET

1
• The state of an ARM system is determined by the content of visible
registers and memory.
• A user-mode program can see 15 32-bit general purpose registers (R0
-R14) , program counter (PC) and CPSR.
• Instruction set defines the operations that can change the state.
• Note:
• Hexadecimal numbers are represented with a prefix 0x
• Binary numbers are represented with a prefix 0b

2
3
Sample formats
• mem<data_size>[address]
• mem32[1024]
• 32 bit value, with starting address 1KB
• Example Instruction

4
ARM Instruction types

5
Data Processing Instructions

6
7
8
9
10
11
Barrel Shifting example

12
13
14
Register on which
shifting is to be done

15
Shift Instructions

16
Logical Left Shift Instructions  Shift amount 0 to 31 (5-bits)
 Contents of Rm is moved one position to the left
 Least significant bits of Rm are filled with zeroes
 The shifted bits of Rm are discarded
 If the instruction is suffixed with S, then the last
discarded high bit is copied into to Carry flag (C bit) of
the CPSR
 This instruction affects the C, N, Z flag based on the
result in destination register

17
Logical Right Shift Instructions  Shift amount 0 to 31 (5-bits)
 Contents of Rm is moved one position to the right
 Most significant bits of Rm are filled with zeroes
 The shifted bits of Rm are discarded
 If the instruction is suffixed with S, then the last
discarded least bit is copied into to Carry flag (C bit) of
the CPSR
 This instruction affects the C, N, Z flag based on the
result in destination register

18
Arithmetic Right Shift Instructions
 Similar to logical shift right
 The high bits are filled with bit 31 (sign bit) of
Rm instead of zeros
 This preserves the sign in 2's complement
notation

“ Arithmetic L e f t Shift iS NOt Needed becAuSe i t iS SAme AS

LOgicAL Left Shift “
19
Rotate Right Instruction
 Rotate right (ROR) operation reuses the bits
which “overshoot” in a logical shift right
operation
 They are introduced at the high end of the
result, in place of the zeros used to fill the high
end in logical right operations

20
Rotate Right Extended Instruction
 In this form the shift field is RRX
 It is used to encode a special function of the barrel
shifter
 This is a rotate right by one bit position of the 33 bit
quantity
 This is formed by appending the CPSR C flag to the
most significant end of the contents of Rm

21
 Logical Instructions with
Register Specified Shift Amount
(using Rs)

22
 Immediate Value Encoding

MOV R1,#130

MOV R1,R0, LSL #1

MOV R1,R0, LSL R2

23
Immediate Value Encoding

24
Immediate Value Encoding

25
Immediate Value Encoding

26
Immediate Value Encoding

27
28
29
Arithmetic Instructions
• Implement addition and subtraction of 32-bit signed and unsigned values
• Only the programmer/compiler is aware whether the operands are unsigned or
2's complement
signed ◦
• Either C or V flag is checked based on whether Unsigned or Signed
Syntax:<instruction> {<condition>}{S} Rd, Rn, N

If the S bit is set (and Rd is not R15) ◦

V flag in the CPSR will be set if an overflow occurs in the signed arithmetic
result;
C flag will be set to the carry out of bit 31 of the ALU ◦
Z flag will be set if and only if the result was zero ◦
N flag will be set to the value of bit 31 of the result
(indicating a negative result if the operands are considered to be 2's
complement signed)
30
ADD: Add two 32-bit values
• The ADD instruction adds the values in Rn and Operand 2 (Rm or imm12 or
Combination of both after shift operations) and stores the result in destination Rd
• Operation: Rd = Rn + N
Syntax: ADD Rd, Rn, Rm / #immediate value, {shift}

Example
• PRE r0 = 0x1000, PRE r0=0x00000000
r1 = 0x04 r1=0x00000005
ADD r15, r0, r1 ADD r0, r1, r1, LSL #1
• POST r0 = 0x1000 POST r0=0x0000000f
r15 = 0x1004 r1=0x00000005
31
ADC: add two 32-bit values and carry
• The ADC (Add with Carry) instruction adds the values in Rn and Operand2, together
with the carry flag
• Used to perform multiword arithmetic
• Operation: R d = R n + ( N )+ C a r r y
Syntax: ADC Rd, Rn, Rm / #immediate value, {shift}
Example
• PRE r0 = 0x1000, C=1 PRE r0=0x00000000, C=1
r1 = 0x04 r1=0x00000005

ADC r15, r0, r1 ADC r0, r1, r1, LSL #1

POST r0=0x00000010
• POST r0 = 0x1000
r1=0x00000005
r15 = 0x1005
32
SUB: subtract two 32-bit values
• The SUB instruction subtracts the value of Operand 2 (Rm or imm12 or Combination of
both after shift operations) from the value in Rn
• Operation: Rd = Rn – (N)
Syntax: SUB Rd, Rn, Rm / #immediate value, {shift}
Example
PRE r0 = 0x00000000 PRE cpsr = nzcvqiFt_USER
r1 = 0x00000001
r1 = 0x00000002
SUBS r1, r1, #1
r2 = 0x00000001
POST cpsr = nZCvqiFt_USER
SUB r0, r1, r2
r1 = 0x00000000
POST r0 = 0x00000001 33
RSB: reverse subtract of two 32-bit values
• The RSB (Reverse Subtract) instruction subtracts the value in Rn from the
value of Operand2. This is useful because of the wide range of barrel shifter
operations for Operand2
• Operation: R d = N − R n
Syntax RSB Rd, Rn, Rm / #immediate value, {shift}
Example
• Subtracts r1 from the constant value #0 can be used to negate numbers.
PRE r0 = 0x00000000
r1 = 0x00000077
RSB r0, r1, #0 ; Rd = 0x0 - r1
POST r0 = -r1 = 0xffffff89
34
SBC: subtract with carry of two 32-bit values
• The SBC (Subtract with Carry) instruction subtracts the value of Operand2
from the value in Rn. If the carry flag is clear, the result is reduced by one
• Rd = Rn- (N) - !(carry flag)
• Syntax: SBC Rd, Rn, Rm / #immediate value, {shift}
• PRE cpsr = nzcvqiFt; c=0

r2 = 0x00000009, r3=0x00000002

SBC r1, r2, r3, LSL#1

• POST r1 = 0x00000004
35
RSC: reverse subtract with carry of two 32-bit values
• The RSC (Reverse Subtract with Carry) instruction subtracts the value in
Rn from the value of Operand2. If the carry flag is clear, the result is
reduced by one
• Opertaion: R d = ( N ) − R n − ! ( c a r r y f l a g )
• Syntax: RSC Rd, Rn, Rm / #immediate value, {shift}
• PRE cpsr = nzcvqiFt; c=0

r2 = 0x00000002, r3=0x00000004

RSC r1, r2, r3, LSL#1

• POST r1 = 0x00000005

36
37
Using PC (R15) in Data Processing
• Use of PC for Rn in the below instruction is allowed
• ◦ ADD{cond} Rd, Rn, #Constant
• If you use PC (R15) as Rn or Rm, the value used is the address of the current instruction plus 8
• If you use PC as Rd:
• Execution branches to the address corresponding to the result ◦
• If you use the S suffix, CPSR flags will be updated

38
Using SP for Rn in ADD and SUB instructions

39
Logical Instructions
 Logical instructions perform bitwise logical operations on the two source regis
 If the S bit is set
 V flag in the CPSR will be unaffected (used for only arithmetic operation)
 C flag will be set to the carry out from the barrel shifter
 Z flag will be set if and only if the result is all zeros
 N flag will be set to the logical value of bit 31 of the result
Syntax: <instruction>{<condition>}{S} Rd, Rn, N

 The logical instructions update the CPSR flags only if the S suffix is present.
These instructions can use barrel-shifted second operands in the same way as the arithmetic
instructions
40
41
BIC
 This instruction is particularly useful
when clearing status bits
 is frequently used to change interrupt
masks in the cpsr.
 To do the above the suffix S must be
present

42
Comparison Instructions
• Are used to compare or test a register with a 32-bit value.
• They update the cpsr flag bits according to the result
• They do not affect other registers. Results are discarded
• These instructions are generally followed by branch instruction to
change program flow by using conditional execution.
• S suffix is not required for comparison instructions to update the
flags.

43
• CMP : Compare
• Compares if the two operands are equal then the result is zero
• CMP R1,R2  R1-R2; If R1=R2, then set the Zero flag
• CMN : Compare Negate
• Here the two operands are compared but the second operand is negated, i.,e.
• CMN R1, R2  R1-(-R2) ; which implies twos complement arithmetic == R1+R2;
• R1-R2; If R1=-R2, then set the Zero flag
• TST: (TEST BIT)
• performs a bitwise AND operation on the value in Rn and the value of Operand2; same as a ANDS instruction
• TST R1,R2  operation: R1 and R2; based on results CPSR flag bits are updated
• Used to test status of bits by applying suitable mask
• TEQ: (TEST EQUAL)
• performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2
• TEQ R1, R2operation: R1 xor R2; based on results CPSR flags are updated
44
45
Multiply Instructions
• Multiply the contents of a pair of registers and
accumulate the results in another register. There
are two methods
• 32 bit multiplication: MUL, MLA
• Long Multiplication: SMLAL, SMUL,
UMLAL, UMULL
• The long multiplication accumulates onto a pair
of registers representing a 64-bit value. The final
result is placed in a destination register or a pair
of registers.
• The number of cycles taken to execute a
multiply instruction depends on the processor
implementation. 46
MUL/MLA Instruction
 performs 32 bit multiplication
 Performs for both signed and unsigned
 Only the least significant 32 bits of the result is stored
 Rm and Rd cannot be the same register;
 R15 cannot be used as any operand
MUL : Multiply MLA: Multiply and Accumulate
 Syntax: MUL {<cond>}{S} Rd, Rm, Rs  Syntax: MLA {<cond>}{S} Rd, Rm, Rs, Rn
 Operation Rd= Rm* Rs  Operation Rd= (Rm* Rs) +Rn
 Contents of Register Rm and Rs are multiplied  Contents of Register Rm and Rs are multiplied and adds the
 The least significant 32 bits of the product are stored in contents of Rn
destination register Rd  The least significant 32 bits of the product are stored in
destination register Rd

47
MUL/MLA Contd..
• Both forms of the instruction work on operands which may be considered as signed (2’s complement) or
unsigned integers
• The results of a signed multiply and of an unsigned multiply of 32 bit operands differ only in the upper 32
bits - the low 32 bits of the signed and unsigned results are identical
• As these instructions only produce the low 32 bits of a multiply, they can be used for both signed and
unsigned multiplies

PRE r0= 0x00000000;

r1= 0x00000002; r2= 0x00000003
r3= 0x00000003
MLA r0, r1, r2, r3
POST r0= 0x00000009
r1= 0x00000002; r2= 0x00000003
r3= 0x00000003
48
Multiply Long Instructions
• The long multiply instructions are
• SMLAL
• SMULL
• UMLAL
• UMULL
• They produce a 64-bit result
• The result is placed in two registers labeled
• RdLo storing lower 32 bits of the 64bit result
• RdHi  storing higher 32 bits of the 64bit result
• R15 cannot be used as any operand

49
SMULL and UMULL UMULL: Unsigned Multiply long

SMULL: Signed Multiply long  Syntax: UMULL{cond}{S} RdLo, RdHi, Rm, Rs ;

 Operation: RdHi:RdLo = Rm * Rs
 Syntax: SMULL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply the 32 bit data stored in Rm and Rs
 Operation: RdHi:RdLo = Rm * Rs
 The resultant 64 bit product is stored such that
 Multiply the 32 bit data stored in Rm and Rs
 Lower 32 bit is stored in RdLo
 The resultant 64 bit product is stored such that  Higher 32 bit is stored in RdHi
 Lower 32 bit is stored in RdLo  RdHi, RdLo, and Rm must all specify different registers
 Higher 32 bit is stored in RdHi Treats all of the operands as unsigned binary numbers and
 RdHi, RdLo, and Rm must all specify different write an unsigned 64 bit result
registers
 Treats all the operands as two's-complement
signed numbers and write a two's complement
signed 64 bit result
50
SMLAL and UMLAL
SMLAL: Signed Multiply long UMLAL: Signed Multiply long
Syntax: SMLAL{cond}{S} RdLo, RdHi, Rm, Rs Syntax: UMLAL{cond}{S} RdLo, RdHi, Rm, Rs
 Operation: RdHi:RdLo = Rm * Rs + [RdHi:RdLo]  Operation: RdHi:RdLo = Rm * Rs + [RdHi:RdLo]
 Multiply 32 bit data in Rm and Rs and add the product  Multiply 32 bit data in Rm and Rs and add the product
with contents of Rdhi;RdLo with contents of Rdhi;RdLo
 The lower 32 bits is to added to contents of RdLo  The lower 32 bits is to added to contents of RdLo
 The upper 32 bits is to added to contents of RdLo  The upper 32 bits is to added to contents of RdLo
 The resultant 64 bit product is stored such that  The resultant 64 bit product is stored such that
 Lower 32 bit is stored in RdLo  Lower 32 bit is stored in RdLo
 Higher 32 bit is stored in RdHi  Higher 32 bit is stored in RdHi
 RdHi, RdLo, and Rm must all specify different registers  RdHi, RdLo, and Rm must all specify different registers
Treats all the operands as two's-complement signed Treats all of the operands as unsigned binary numbers and
numbers and write a two's complement signed 64 bit write an unsigned 64 bit result
result
51
Signed multiplication - Example

52
Unsigned multiplication - Example

53
54
Branch Instructions
• changes the flow of execution
• is used to call a routine
• These instructions allows the programs to have
• subroutines
• if-then-else structures
• Loops
• Once executed the PC points to a new
address location specified by the instruction
 The address label is a signed pc-relative
offset
 It must be within approximately 32 MB
of the branch instruction.
 T refers to the Thumb bit in the cpsr. 55
BRANCH instruction:
• Syntax: B{<condn>} label
• Operation: jump to location specified in label i.e., PC= label (offset address within 32
MB)

Branch with Link

 Syntax: BL{<condn>} label
 Operation: writes the old PC into the link register (R14) of the current bank
 The PC value written into R14 is Current PC-4 to allow for the prefetch
 Contains the address of the instruction following the branch and link instruction
 To return from a routine called by Branch with Link use
 MOV PC, R14( if the link register is still valid)
 LDM Rn,{PC} if the link register has been saved onto a stack pointed to by Rn
56
57
58
59
60
 The b r a n c h e x c h a n g e (BX) a n d b r a n c h e x c h a n g e w i t h l i n k (BLX)
 are third type of branch instruction.
 Performs a branch by copying the contents of a general register, Rm, into the PC
 Permits the instruction set to be exchanged ie., determines whether the new instruction stream pointed to by
[Rm] will be ARM or Thumb instruction set
 When executed if the value of
 Rm[0] bit =0  ARM state
 Rm[0] bit =1  THUMB state
BX instruction
Syntax:BX{<condn>} Rm
Operation: pc = Rm & 0xfffffffe, T = Rm & 1
BLX Instruction
Additionally sets the link register with the return address.
Syntax:BX{<condn>} LABEL | Rm
Operation: pc = label, T = 1
pc = Rm & 0xfffffffe, T = Rm & 1
lr = address of the next instruction after the BLX
61
Load-Store Instructions

62
Load-Store Instructions
• transfer data between memory and processor registers
• There are three types of load-store instructions:
• single-register transfer
• multiple-register transfer
• swap

Single-Register Transfer
 used for moving a single data item in and out of a register
 datatypes supported are
 signed and unsigned words (32-bit),
 halfwords (16-bit),
 bytes 63
Single-Register Transfer contd..

64
Example:

Here R1 is the base

address register

65
Address is calculated by base
address register and 12 bit offset

Address is calculated by base

address register and specific
register contents

Address is calculated by base

address register and barrel
shift operation

66
Single-Register Load-Store Addressing Modes

 The ARM instruction set provides different modes for

addressing memory.
 These modes incorporate one of the indexing methods:
 preindex with writeback,
 Preindex
 postindex

67
Pre-index with writeback

Here base register is not updated with the new address {R1
has not changed after execution}
Useful for traversing an array 68
Pre-indexing

Here base register is not updated with the new address {R1 has not
changed after execution}
Useful for accessing the elements in a data structure 69
Post indexing

Only updates the address base register after the address is used {R1
has changed after execution but r0 has the value stored in the initial
memory location pointed by r1}
70
Useful for traversing an array
71
Single-register load-store addressing for 32 bit word

72
Addressing of LDR instruction using different addressing modes

73
Single-register load-store addressing, halfword, signed halfword,
signed byte

74
 Variations of STRH Instruction
Barrel shifting operation cannot be done using STR instruction as they store both signed and unsigned
data

75
Multiple Register Transfer
 Transfer multiple registers between memory and processor in a single instruction
 The transfer is from base address register Rn pointing into memory
 More efficient than single register transfer

76
Addressing modes for Load Store Multiple Register Instructions

N No. of registers in the list of Registers

77
78
79
80
81
82
Example: LDMFA is a pseudo-instruction for LDMDA, referring to its use for popping data from Full Ascending
stacks.

83
84
85
86
87
88
89
90
91
92
 Software interrupt instruction
• Software interrupt (SWI) instruction is used to enter Supervisor mode, usually to request a
particular supervisor function.

• The SWI handler reads the opcode to extract the SWI function number.

93
Software interrupt instruction

• Here, R0 is used to pass the

parameter for the subroutine
called by SWI

• PC will be loaded with the

offset 0x08 in the vector
table

94
95
96
97
Assembler directives
Sloss: Appendix A4.4

98
AREA - The AREA directive instructs the assembler to assemble a new code or data area.
Areas are independent, named, indivisible chunks of code or data that are manipulated
by the linker.
ALIGN - This causes the assembler to pad the binary with bytes of zero value, in data
sections, or NOP instructions in code, ensuring the next location will be on a word
boundary. .align n gives 2^n alignment on ARM cores.
DATA - Causes the following statements to be placed in the data section of the final
executable.
END - Marks the end of this source code file. The assembler does not process anything in
the file after this point.
EQU symbol, expression - Sets the value of symbol to expression. The "=" symbol
and .set have the same effect.
EXTERN symbol - Indicates that symbol is defined in another source code file.
GLOBAL symbol - Tells the assembler that symbol is to be made globally visible to other
source files and to the linker.
INCLUDE "filename“ - Inserts the contents of filename into the current source file and is
typically used to include header files containing shared definitions. 99
The DCB directive allocates one or more bytes of memory, and defines the initial runtime
contents of the memory. = is a synonym for DCB.

The DCW directive allocates one or more halfwords of memory, aligned on 2-byte boundaries,
and defines the initial runtime contents of the memory.

The DCD directive allocates one or more words of memory, aligned on 4-byte boundaries,
and defines the initial runtime contents of the memory. & is a synonym for DCD.

The DCWU directive allocates one or more unaligned halfwords of memory, and defines the
initial runtime contents of the memory.

The DCDU directive allocates one or more words of memory, not necessarily aligned, and
defines the initial runtime contents of the memory.

code [16|32]This directive selects the instruction set being generated. The value 16 selects
Thumb, with the value 32 selecting ARM.
100
ARM-Thumb interworking
Sloss: 4.2

101
BX instruction

102
BLX instruction

103