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Understanding Interrupts in Microcontrollers

The document discusses the concept of interrupts in microcontroller programming, explaining their role in allowing a CPU to respond to significant external events without relying on program control. It covers various aspects of interrupts including classifications, handling, prioritization, and the use of interrupts in timing and power management. Additionally, it highlights the importance of managing shared data and provides insights into practical applications such as timers and sleep modes in embedded systems.

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0% found this document useful (0 votes)
13 views30 pages

Understanding Interrupts in Microcontrollers

The document discusses the concept of interrupts in microcontroller programming, explaining their role in allowing a CPU to respond to significant external events without relying on program control. It covers various aspects of interrupts including classifications, handling, prioritization, and the use of interrupts in timing and power management. Additionally, it highlights the importance of managing shared data and provides insights into practical applications such as timers and sleep modes in embedded systems.

Uploaded by

sigma.elev
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Lec5 : Interrupts

For more details, refer to:


• Chapter 6, T. Wilmishurst, Designing Embedded Systems with PIC
Microcontrollers, 2010.

1
+ 2

Interrupts

n Fundamental concept in computation


n Interrupt execution of a program to handle an event
n Don’t have to rely on program relinquishing control
n Can code program without worrying about others
n Issues
n What can interrupt and when?
n Where is the code that knows what to do?
n How long does it take to handle interruption?
n Can an interruption be, in turn, interrupted?
n How does the interrupt handling code communicate its results?
n How is data shared between interrupt handlers and programs?
+ 3

main idea of interrupts


n Computer CPU is a deeply orderly entity, following the instructions of the program one
by one and doing what it is told in a precise and predictable fashion.
n An interrupt disturbs this order.
n Its function is to alert the CPU in no uncertain terms that some significant external
event has happened, to stop it from what it is doing and force it (at the greatest speed
possible) to respond to what has happened.
n Originally interrupts were applied to allow emergency external events, such as power
failure, the system overheating or major failure of a subsystem to get the attention of
the CPU.
n But the concept of interrupts was recognized as being very powerful.
+ Interrupt Classifications
4

n Some categories are:


n Internal/ External
n Hardware/ Software
n Maskable/ Non-maskable
+ 5

What is an Interrupt?

n Reaction to something in I/O (human, comm link)


n Usually asynchronous to processor activities
n interrupt handler or interrupt service routine (ISR)
n invoked to take care of condition causing interrupt
n Change value of internal variable (count)
n Read a data value (sensor, receive)
n Write a data value (actuator, send)
+ Interrupt structures
6

n Differentmicrocontrollers have rather different interrupt structures.


n They have more than one interrupt source, usually with some internally
generated and others external.
n A simple generic interrupt structure
+ 7

Example:
The 16F84A interrupt structure
+ 8

INTCON register (16F84A )


+ 9

Saving and Restoring Context


n How much context to save?
n Registers, flags, program counter, etc.
n Save all or part?
n Agreement needed between ISR and program

n Where should it be saved?


n Stack, special memory locations, shadow registers, etc.
n How much room will be needed on the stack?
n Nested interrupts may make stack reach its limit – what then?

n Restore context when ISR completes


+ 10

Prioritizing Interrupts

n When multiple interrupts happen simultaneously


n Which is serviced first?
n Fixed or flexible priority?

n Priority interrupts
n Higherpriority can interrupt
n Lower priority can’t

n Maskable interrupts
n Don’t bother me with that right now
n Not all interrupts are maskable, some are non-maskable
+ 11

Interrupt Jump Vector Table

n Fixed location in memory to find


first instruction for each type of
interrupt
n Only room for one instruction
n JMP to location of complete ISR
n On system reset, the vector
table is fixed at address
0x00000000.
+

Interrupt Response Sequence of


Events
+ 13

Chain of Events on Interrupt


+ 14

Working with Interrupts (for PIC16F84A)

n Itis easy to write simple programs with just one interrupt.


n Using Assembly language!
n For success, the essential points to watch are:
n Start the ISR at the interrupt vector, location 0004.
n Enable the interrupt that is to be used by setting the enable bit in the
INTCON register.
n Set the Global Enable bit, GIE.
n Clear the interrupt flag within the ISR.
n End the ISR with a retfie instruction.
n Ensure that the interrupt source, for example Port B or Timer 0, is actually
set up to generate interrupts!
+ 15

Shared Data Problem

n When you use interrupts you create the opportunity for


multiple sections of code to update a variable.
n This might cause a problems in your logic if an interrupt
updates a variable between two lines of code that are directly
dependent on each other (e.g. if statement)
n One solution is to create critical sections where you disable
the interrupts for a short period of time while you complete
your logic on the shared variable
+
COUNTERS & TIMERS

16
+ 17

The counter as a timer


n It is extremely useful for a microcontroller to be able to count – widgets
passing on a conveyor belt, for example, coins in a slot machine, or people
going through a door.
n It is, however, especially useful if it can measure time, and the counter
allows us to do this.
n Suppose the input signal of a counter is a stable 1 kHz clock frequency.
n Then the counter would increment exactly every 1 ms.
n After 16 clock cycles, exactly 16 ms would have elapsed, after 31 cycles 31 ms and
so on.
n By starting the clock input at a moment of choice, it is therefore possible to
measure elapsed time.
n The resolution of the measurement is determined by the period of the clock.
n In this example the resolution is 1 ms and we can’t measure anything less
than that, or a fraction of it.
+ The challenge of time measurement
18

n The actual measurement seems easy – start the


counter/timer running when the first event occurs and
stop it at the moment of the second.
n In practice, this poses a number of challenges.
n For an accurate measurement, the start and stop of the
counter/timer must be perfectly synchronized with the
events.
n The best way of doing this is by using an interrupt.
n If we don’t have an interrupt, then we will have to
continuously scan the input to detect when the event
occurs .
+ 19

The Watchdog Timer


nA big danger with any computer-based system is that the software
fails in some way and that the system locks up or becomes
unresponsive.
n In a desktop computer such a lock-up can be annoying and one
would normally have to reboot.
n In an embedded system it can be disastrous, as there may be no
user to notice that there is something wrong and maybe no user
interface anyway.
n The WDT offers a fairly brutal ‘solution’ to this problem.
n It is a counter, internal to the microcontroller, which is continually
counting up If it ever overflows, it forces the microcontroller into
Reset.
+ 20

Sleep Mode
n It is an important way of saving power.
n The microcontroller can be put into this mode by executing the
instruction SLEEP.
n Once in Sleep mode, the microcontroller almost goes into
suspended animation.
n The clock oscillator is switched off, the WDT is cleared, program
execution is suspended, all ports retain their current settings, and
the PD and TO bits in the Status register are cleared and set
respectively.
n If enabled, the WDT continues running.
n Under these conditions, power consumption falls to a negligible
amount.
+ 21

Wakes from Sleep Mode

nThe MCU wakes from Sleep in the following situations:


n External reset through MCLR pin.
n WDT wake-up.
n Occurrence of interrupt.

nOn wake-up, the oscillator circuit is restarted.


nThe Sleep mode is extremely powerful for products that
must be designed in a power conscious way.
n Battery-based devices
n WSN
+ 22

STM32 Sleep Mode


In Sleep mode, the CPU clock is off, but there is no effect on other clocks or analog
clock sources. All peripherals continue to operate and can wake up the CPU when an
interrupt or event occurs.
+
SAMPLE PROJECT

23
24
Example:Keypad/Display

When you press a key,


Display it on the 7-segment
+ Downstream - BL0114 - Combo 25
26
27
28
+ the LCD_4x20 component 29

The Start routine is required to initialize the LCD screen, so that the
microcontroller knows it exists, and sets up timing routines etc.
+ 30

TOOLCHAIN

Common questions

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The Watchdog Timer (WDT) plays a crucial role in maintaining system reliability in embedded systems by automatically resetting the microcontroller in the event of software failures or system lock-ups. As the WDT continuously counts up, it forces a reset when it overflows, thereby restoring the system to a known state. This automatic reset is essential for embedded systems that operate without user intervention, ensuring they do not remain in an unresponsive state, which could be catastrophic .

Interrupt vector tables are essential in embedded systems as they provide a fixed memory location to store the addresses of the ISR entry points for different interrupts. Their primary function is to facilitate the quick location and execution of ISRs when interrupts occur, ensuring that the CPU can immediately jump to and execute the appropriate handling routines. This mechanism is critical for timely and effective interrupt handling in the system .

Different interrupt structures among microcontrollers can significantly affect software development by dictating how interrupts are prioritized, handled, and managed. Some microcontrollers support multiple interrupt sources and vary in their configuration of internal versus external interrupts, as well as maskable versus non-maskable types. Developers need to carefully design the interrupt service routines (ISRs) and prioritize interrupts according to application needs to ensure effective handling. This variation requires developers to tailor software specifically for each microcontroller's architecture to optimize performance and reliability .

The INTCON register is crucial in scenarios requiring precise control over interrupt enablement and priority management in PIC microcontrollers. It serves functions such as enabling specific interrupts by setting the relevant enable bits and managing global interrupt enablement through the GIE bit. This register is pivotal in configuring the microcontroller's response to interrupt sources and ensuring the correct sequence of instruction execution in ISR handling .

Sleep Mode contributes significantly to power efficiency by reducing the microcontroller's power consumption to a negligible amount. In this mode, the clock oscillator is turned off, and program execution is suspended, while peripheral settings are maintained. This feature is particularly beneficial for battery-powered devices, as it prolongs battery life by minimizing energy usage during inactive periods. The mode allows the device to remain ready for activation via external reset or interrupts while conserving power .

Using a counter as a timer in microcontroller applications often involves challenges in synchronizing the start and stop of the counter with events, as any delay could lead to inaccurate measurements. Interrupts can mitigate these challenges by ensuring precise synchronization. By triggering interrupts at the exact moment an event occurs, the counter can be started or stopped immediately, thereby enhancing the accuracy of time measurements .

Interrupts enhance CPU functionality by allowing it to respond immediately to significant external events without waiting for the current program to complete. This mechanism alerts the CPU to handle emergencies such as power failures or system overheating swiftly, thus preventing potential issues. Moreover, interrupts allow asynchronous handling of input/output events, enabling the CPU to operate efficiently without continuously polling for events .

The primary challenge in handling shared data in interrupt-driven systems is the risk of logic errors arising from an interrupt updating shared variables between dependent operations. This can lead to inconsistent program behavior. A solution to this problem is to create critical sections in the code where interrupts are temporarily disabled, ensuring that the variable updates occur without interruption. This prevents the logic from being disrupted, thereby maintaining program integrity .

Maskable interrupts allow the CPU to ignore certain interrupts temporarily by setting a mask bit, thereby providing flexibility in managing less critical tasks. Conversely, non-maskable interrupts cannot be ignored, as they are used for handling high-priority events that require immediate attention. This distinction ensures that critical operations are not deferred, while providing some control to the CPU over less urgent processes, balancing system flexibility with control .

Prioritizing interrupts affects performance by determining the order in which interrupts are serviced, helping to ensure that critical tasks are executed promptly, thereby enhancing system reliability. Considerations in setting priorities include the urgency and importance of each interrupt source, the potential impact on system performance if certain interrupts are delayed, and the need for flexibility in adapting to different operational conditions. Proper prioritization ensures that high-priority tasks are not postponed, maintaining consistent system performance .

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