Final exam review

Chapter 4 & 5

Computer Architecture – CSE – HCMIU 1

SIMPLIFIED MIPS IMPLEMENTATION

2
 Full microarchitecture: simplified
implementation
0 32 bit

MUX
Shift left 2
1
32 bit Add
PCSrc
Add
4
Branch
[31:26] Control
unit

RegWrite

MemtoReg
[25:21] 32 bit
Instruction Read register 1 Read oprd 1
PC 32 bit address data 1

ALUSrc
32 bit [20:16] zero MemWrite
Instruction Read register 2
0 ALU Read 32 bit 1
Instruction 32 bit
MUX

ALU Address data

MUX
memory [15:11] Write register Read 0 result
1 32 bit

MUX
data 2 oprd 2 32 bit Write 0
Write data data Data
RegD 1
Register 4 bit memory
st
ALU Operation MemRead

[15:0] Sign ALU

extend ALUOp Control
16 bit 32 bit
32 bit

[5:0] 6 bit
Computer Architecture (c) Cuong Pham-Quoc@HCMUT 3
 Exercises

• Question 1: given the execution time of functional units as

follows (blocks that don’t show up in the table will require 0
ns)

• What is the execution time of: add, addi, lw, and sw

instructions?
• What is the cycle time of the processor?
Computer Architecture (c) Cuong Pham-Quoc@HCMUT 4
 Exercises
• Question 2: Assume that the first instruction is stored at address of 8 while
registers originally store values of two times their numbers (i.e., register $s0
stores value of 32).
L1: addi $t0, $t0, 2
beq $t0, $t1, L1
sw $t0, 100($s0)
lw $t2, 100($s0)
a) What are the values of Instruction memory input and output when executing the
sw instruction?
b) What are the values of Register inputs when executing the lw instruction?
c) What are the values of ALU inputs and outputs when executing beq the first and
the last time?
d) What are the values of Data memory inputs when executing the addi instruction?
e) What is the instruction count (IC) of the above sequence?

Computer Architecture (c) Cuong Pham-Quoc@HCMUT 5

PIPELINE MIPS IMPLEMENTATION

6
 ID/EX EX/MEM MEM/WB

WB
WB
Control M
IF/ID Unit WB
(1) ALUSrc
EX (2) RegDst M
(3) ALUop
[31:26]

Shift left 2

Branch
Add

Add
4 RegWrite

MemtoReg
MemWrite
[25:21]

MUX
0 Instruction Read register 1 oprd 1
MUX

PC address Read data 1

32 bit [20:16] zero
Instruction Read register 2
1 (1) ALU Read 1
Instruction Write register Result Address data

MUX
Memory

MUX
PCSrc 0

MUX
oprd 2 Write 0
Write data Read data 2
data Data
Registers 1 ALU 4 bit Memory
Operation MemRead
F1
F2
[15:0] (3) ALU
Sign
extend Control
16 bit 32 bit
[5:0] (2)
0
EX/[Link]

MUX

MEM/[Link]
[15:11] 1
ID/[Link]
Forwarding
ID/[Link] unit EX/[Link]

Mem/[Link]

Computer Architecture (c) Cuong Pham-Quoc@HCMUT 7

 Exercises
• Question 1: Assume that registers originally store values of their numbers (i.e., $s0 stores value of 16)
and the following sequence will be executed by the MIPS pipeline version
add $s0, $s1, $s2
lw $t0, 100($s0)
and $t1, $t2, $t0
sw $t1, 100($t0)
addi $t2, $t1, 100
lw $t2, 8($t2)
sub $s0, $s2, $t2
a) How many cycles does the MIPS processor need to perform the sequence when hazards are solved by
only the stall insertion method?
b) What is the speed-up compared to the stall insertion method when the forwarding approach is
applied for solving hazards?
c) What are the values of F1 and F2 signals at cycle 6?
d) What are values of control signals used in the EXE stage of Figure 1 at cycle 6?
e) What are values of Data memory inputs at cycle 7?
f) What are values of ALU inputs and outputs in cycle 8?

Computer Architecture (c) Cuong Pham-Quoc@HCMUT 8

MEMORY HIERACHY

9
 Exercise
• Assume that a main memory has 32-bit byte address (MIPS processor). A 256
KB cache consists of 4-word blocks.
a) Which is the size of the main memory?
b) If the cache uses “direct mapped”, how many bits are the tag field?
c) How many memory bits do we need to use to build in the direct mapped
cache?
d) If the cache uses “fully associative”, how many bits are the tag field?
e) How many memory bits do we need to use to build the fully associative cache?
f) If the cache uses “2-way set associative”, how many sets are there in the cache?
g) If the cache uses “2-way set associative”, how many bits are the tag field?
h) How many memory bits do we need to use to build the 4-way set associative
cache?

Computer Architecture (c) Cuong Pham-Quoc@HCMUT 10