VLSI Design

( 3151105 )
Prepared by :
Jayesh Diwan
EC Department
VGEC
Chapter 10: Design for testability

Prepared By : Jayesh Diwan

Introduction
 The task of determining whether fabricated chips are fully functional is highly
complex and can be very time-consuming. However, when faulty chips pass an
improperly designed test, they can cause system failures and enormous difficulty
in system debugging.
 It is known that the debugging cost increases by about tenfold from chip level to
board level, and also from board level to system level. Thus, it is of great
importance to detect faults as early as possible.
 As the number of transistors integrated into a single chip increases, the task of
chip testing to ensure correct functionality becomes increasingly more difficult.

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Fault types and Fault Models
 Examples of physical defects include:
 Defects in silicon substrate
 Photolithographic defects
 Mask contamination and scratches
 Process variations and abnormalities
 Oxide defects

The physical defects can cause electrical faults and logical faults.
The electrical faults include:
 Shorts (bridging faults)
 Opens
 Transistor stuck-on, stuck-open
 Resistive shorts and opens
 Excessive change in threshold voltage
 Excessive steady-state currents

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Fault types and Fault Models
 The electrical faults in turn can be translated into logical faults.
 The logical faults include:
 Logical stuck-at-0 or stuck-at-I
 Slower transition (delay fault)
 AND-bridging, OR-bridging

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Fault types and Fault Models

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Fault types and Fault Models

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Fault types and Fault Models
 The delay fault which causes timing failures at target speed can be due to
several factors, like
 Improper estimation of on-chip interconnect delays and other timing
considerations,
 excessive variations in the fabrication process which cause significant
variations in circuit delays and clock skews,
 opens in metal lines connecting parallel transistors which make the
effective transistor size much smaller,
 aging effects such as hot-carrier induced delay increase.

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Controllability and Observability
 The controllability of a circuit is a measure of the ease (or difficulty) with which
the controller (test engineer) can establish a specific signal value at each node by
setting values at the circuit input terminals.
The Observability is a measure of the ease (or difficulty) with which one can
determine the signal value at any logic node in the circuit by controlling its primary
input and observing the primary output.

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Ad Hoc Testable Design Techniques
 To increase the testability is to make nodes more accessible at some cost by
physically inserting more access circuits to the original design.
 Following are some of the ad hoc testable design techniques.
 Partition-and-Mux Technique
 Initialize Sequential Circuit
 Disable Internal Oscillators and Clocks
 Avoid Asynchronous Logic and Redundant Logic
 Avoid Delay-Dependent Logic

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Ad Hoc Testable Design Techniques
 Partition-and-Mux Technique:
• Large circuits are difficult to test, such circuits can be partitioned and
multiplexors (muxes) can be inserted such that some of the primary inputs
can be fed to partitioned parts through multiplexers with accessible control
signals.
• With this design technique, the number of accessible nodes can be
increased and the number of test patterns can be reduced.
• However, circuit partitioning and addition of multiplexers may increase the
chip area and circuit delay.

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Ad Hoc Testable Design Techniques
 Initialize Sequential Circuit :
• When the sequential circuit is powered up, its initial state can be a random,
unknown state.
• It is not possible to start the test sequence correctly.
• The state of a sequential circuit can be brought to a known state through
initialization.
•The initialization can be done by connecting asynchronous preset or clear-
input signals from primary or controllable inputs to flip-flops or latches.

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Ad Hoc Testable Design Techniques
 Disable Internal Oscillators and Clocks:
• To avoid synchronization problems during testing, internal oscillators and
clocks should be disabled.
• Rather than connecting the circuit directly to the on-chip oscillator, the clock
signal can be ORed with a disabling signal followed by an insertion of a
testing signal.

Prepared By : Jayesh Diwan

Ad Hoc Testable Design Techniques
 Avoid Asynchronous Logic and Redundant Logic:
• Large circuits are difficult to test, such circuits can be partitioned and
multiplexors (muxes) can be inserted such that some of the primary inputs
can be fed to partitioned parts through multiplexers with accessible control
signals.
• With this design technique, the number of accessible nodes can be
increased and the number of test patterns can be reduced.
• However, circuit partitioning and addition of multiplexers may increase the
chip area and circuit delay.

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Redundant Logic:

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Ad Hoc Testable Design Techniques
 Avoid Delay-Dependent Logic :
• Chains of inverters can be used to design in delay times and use AND
operation of their outputs along with input to generate pulses.
• Most automatic test pattern generation (ATPG) programs do not include
logic delays to minimize the complexity of the program. As a result, such
delay-dependent logic is viewed as redundant combinational logic, and the
output of the reconvergent gate is always set to logic 0, which is not correct.
Thus, the use of delay-dependent logic should be avoided in design for
testability.

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Scan-Based Techniques
Step 1: Set the mode to test and, let
latches accept data from scan-in input, X1 Combinational logic Y1
Step 2: Verify the scan path by shifting X2 Y2
X3
in and out the test data.
f
Step 3: Scan in (shift in) the desired
state vector into the shift register.
Step 4: Apply the test pattern to the
prim ary input pins. I : ; FF3
Step 5: Set the mode to normal and Q D
observe the primary outputs of the
circuit after sufficient time for
FF2
propagation.,
Step 6: Assert the circuit clock, for one Q D
machine cycle to capture the outputs of .
the combinational logic into the FF1
registers.
Step 7: Return to test mode; scan out Q D
the contents of the registers, and at the CK
.
same time scan in the next pattern.
Step 8: Repeat steps 3-7 until all test
patterns are applied. Prepared By : Jayesh Diwan
Scan-Based Techniques
Step 1: Set the mode to test and, let
latches accept data from scan-in input,
Step 2: Verify the scan path by shifting
in and out the test data.
Step 3: Scan in (shift in) the desired
state vector into the shift register.
Step 4: Apply the test pattern to the
prim ary input pins. I : ;
Step 5: Set the mode to normal and
observe the primary outputs of the
circuit after sufficient time for
propagation.,
Step 6: Assert the circuit clock, for one
machine cycle to capture the outputs of
the combinational logic into the
registers.
Step 7: Return to test mode; scan out
the contents of the registers, and at the
same time scan in the next pattern.
Step 8: Repeat steps 3-7 until all test
patterns are applied. Prepared By : Jayesh Diwan
Built-In Self Test (BIST) Techniques

A pseudo-random sequence generator using LFSR

A procedure for BIST

Polynomial division using LFSR for signature analysis

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Current Monitoring IDDQ Test
 An often-used technique for testing fabrication defects is the IDDQ test.
Under a bridging fault, the static currents drawn from the power supply in CMOS circuits
can be noticeably.
It can also detect other fabrication defects not easily detected by other test methods,
including:
• Gate oxide short
• Channel punch-through
• p-n diode leakage
• Transmission-gate defect
 The IDDQ test consists of applying the test vector and then monitoring the current drawn
from the power supply rail in DC steady state.
This test requires more testing time, the fault detection capability is greatly improved with
small circuit overhead required to monitor the IDDQ in various parts of DUT.
 While stuck-at tests require both fault sensitization and fault effect propagation, the IDDQ
test requires only fault sensitization.
 The IDDQ fault coverage is relatively easy to obtain and may potentially offer a full-chip
coverage capability for large designs.
 The design guidelines for IDDQ testability are as follows:
• Low static current states, e.g., full CMOS is preferred
• No active pull-ups or pull-downs
• No internal drive conflicts, e.g., drivers share a bus
• No floating nodes in the circuit
• No degraded voltages, e.g., must have VOH = VDD and VOL = 0
Prepared By : Jayesh Diwan