Electronics III
Electrical Technology Program
Egyptian-German Faculty of Technology
Dr. Nabil Sabor
Associate Professor at Electrical Engineering Department
Faculty of Engineering, Assiut University
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Course Contents
• Field Effect Transistor
➢ The JFET
➢ JFET Characteristics and Parameters (Experiment 1)
➢ JFET Biasing
➢ The Ohmic Region
➢ The MOSFET
➢ MOSFET Characteristics and Parameters (Experiment 2)
➢ MOSFET Biasing
• FET AMPLIFIERS
➢ The Common-Source Amplifier (Experiment 3)
➢ The Common-Drain Amplifier
➢ The Common-Gate Amplifier
• The Operational Amplifiers
➢ Introduction to Operational Amplifiers
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Course Contents
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Book
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Evaluation
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Chapter 8
Field Effect
Transistor (FET)
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Chapter Outline
➢ 8–1 The JFET
➢ 8–2 JFET Characteristics and Parameters
➢ 8–3 JFET Biasing
➢ 8–5 The MOSFET
➢ 8–6 MOSFET Characteristics and Parameters
➢ 8–7 MOSFET Biasing
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Introduction
• FET – a three-terminal voltage-controlled device
used in amplification and switching application.
• Field effect transistors controls current by voltage
applied to the gate.
•The FET’s major advantage over the BJT is high
input resistance.
• 2 basic type of FET: JFET and MOSFET
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JFET
▪ The junction field effect transistor, like a BJT, controls
current flow.
▪ The difference is the way this is accomplished. The JFET
uses voltage to control the current flow. As you will
recall the transistor uses current flow through the base-
emitter junction to control current.
▪ JFETs can be used as an amplifier just like the BJT.
VGG voltage levels control
current flow in theVDD,
RD circuit.
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JFET
• The terminals of a JFET are the source, gate, and drain.
• A JFET can be either p channel or n channel.
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JFET
• VDD provide a drain-to-source voltage.
• VGG sets the reverse-bias voltage between gate and source.
JFET is always operated with gate-source pn junction reverse-
biased. Reverse-biasing of the gate-source junction with a –ve
gate voltage produces a depletion region along pn junction.
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JFET Biasing
• Gate-to-source junction of JFET always reverse-biased under
normal condition.
• Gate-to-source junction never allowed to become forward-
biased because the gate material is not designed to handle
any significant amount of current → may destroy the
component.
• The fact gate is always reverse-biased leads to important
feature → JFET has high gate input impedance; typically in
high megaohm range.
• This feature result to JFET extensively being used in
integrated circuits.
• Low current draw helps IC remain cool, thus allowing more
components to be placed in a smaller physical area.
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JFET Characteristics and Parameters
Let’s first take a look at the effects with a VGS of 0V.
This is produced by shorting the gate to source
junction.
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JFET Drain Curve
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• Refer to JFET drain curve from point A to B, ID increases
proportionally with increases of VDD (VDS increases as VDD
increases). This is called the ohmic region (point A to B)
because VDS and ID are related by Ohm’s Law.
• At point B, the curve levels off and ID becomes constant. The
point when ID ceases to increase regardless of VDD increases
is called the pinch-off voltage, VP (point B). This current is
called maximum drain current (IDSS) and always specified for
the condition, VGS=0V. This area is called constant-current
area.
• Breakdown (point C) occur when ID begins to increase
rapidly with any increase in VDS. This of course undesirable,
so JFETs operation is always well below this value.
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JFET Characteristics and Parameters
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JFET Characteristics and Parameters
From this set of curves you can see with increased voltage
applied to the gate, ID decrease and JFET reaches pinch-off at
values of VDS less than VP.
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JFET Characteristics and Parameters
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JFET Characteristics and Parameters
• We know that as VGS is increased ID will decrease. The point
that ID ceases increase is called cutoff.
•The amount of VGS required to do this is called the cutoff
voltage (VGS(off ) ).
• The more negative VGS, the smaller ID becomes. When VGS
has sufficiently large negative value, ID is reduced to zero.
It is interesting to note
that pinch-off voltage
(Vp) and cutoff voltage
(VGS(off)) are both the
same value only
opposite polarity.
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JFET Transfer Characteristic
For n-channel JFET, VGS(off) is negative and for p-channel,
VGS(off) is positive.
Bottom end of the curve is at a point on VGS axis equal to
VGS(off) and the top end of the curve is at a point on ID axis
equal to IDSS (shorted-gate drain current rating of the device).
The operating limits of JFET are:
ID=0 when VGS=VGS(off)
ID=IDSS when VGS = 0
Transfer characteristic curve can be developed from drain
characteristic curves by plotting values of ID for the values of
VGS taken from the family of drain curves at pinch-off.
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JFET Characteristics and Parameters
The transfer characteristic curve illustrates the control VGS
has on ID from cutoff (VGS(off) ) to pinchoff (VP).
The formula below can be used to determine drain current.
All these values are usually available from data sheet.
ID = IDSS(1 - VGS/VGS(off))2
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Normal Biasing
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Transconductance
• Forward transfer conductance, gm of JFETs is
sometimes considered. It is the changes in ID based on
changes in VGS with VDS is constant.
• Input resistance for a JFET is high since the gate -source
junction is reverse biased, however the capacitive effects
can offset this advantage particularly at high frequencies.
The value is larger at the top of the curve (near VGS=0)
but become smaller as you increase VGS (near VGS(off)).
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Transconductance
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Transconductance
Forward transfer conductance referred to as
gm = ∆ID /∆VGS.
At VGS =0, the parameter is known as minimum
transfer conductance, gmo and can be calculated using
this equation:
gmo = 2IDSS/|VGS(off)| and gm = gmo(1 - VGS/VGS(off))
gmo can be read from the datasheet as gfs or yfs and
sometimes written as Forward Transfer Admittance.
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JFET Input Resistance
• Since JFET is reverse-biased for operation, its input
resistance becomes so large. This is an advantage of
using JFET.
• This internal input resistance can be calculated at
different VGS :
RIN=|VGS/IGSS|
• As IGSS increases with temperature, RIN will decrease.
Example 1: Calculate RIN if IGSS=-2nA and VGS=-20V
Solution:
RIN=|VGS/IGSS|=|-20/-2n|=10G
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JFET Biasing Circuit
• Three types of bias methods are
➢ self-bias
➢voltage-divider bias
➢current-source bias.
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JFET Biasing- Self bias
• Self-bias is the most common type of biasing method
for JFETs.
• Notice there is no voltage applied to the gate, VG=0V.
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JFET Biasing- Self bias
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JFET Biasing- Self bias
• However, the voltage from gate to source (VGS) will be negative
for n channel and positive for p channel to keep the junction
reverse biased.
• Keep in mind that analysis of p-channel is the same as n-channel
except for opposite polarity voltages.
• The gate-source voltage can be determined using the formulas
below. ID = IS for all JFET circuits. VG=0 and VS=IDRS.
VGS = VG - VS
(n-ch) VGS = 0-IDRS =-IDRS and (p-ch) VGS = 0-(-IDRS )=IDRS
• The drain voltage with respect to ground is:
VD = VDD – IDRD
• Since VS = IDRS, VDS is: VDS = VD – VS = VDD – ID(RD+RS)
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Example 8.6
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JFET Biasing-graphical
First, establish dc load line by calculating VGS.
VGS = -IDRS for ID=0 and ID=IDSS
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Example 8.10
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JFET Biasing- voltage divider bias
• Voltage-divider bias can also be used
to bias a JFET. R1 and R2 are used to keep
the gate-source junction in reverse bias.
Source voltage,VS = IDRS
Gate voltage, VG =(R2/R1+R2)VDD
Gate-to-source [Link]=VG –VS
Source voltage, VS = VG – VGS
Since ID=IS, then ID=VS/RS
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Example 8.11
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JFET Biasing-graphical
• In using the transfer characteristic curve to determine the
approximate Q-point we must establish the two points for
the load line.
• The first point is ID = 0 and VGS =VG.
VS=IDRS=(0)RS=0V
VGS=VG-VS=VG-0=VG
For VGS=0,
ID=(VG-VGS) / RS = VG / RS
• The second point is ID=VG / RS and VGS=0.
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Dc load line for JFET with voltage-divider bias
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JFET Biasing – Current Source Bias
Current source bias → provides high Q-point
stability by making value of ID independently
of JFET.
From figure, JFET drain current equals BJT
collector current. IDQ = IC
The value of IC is less than the lowest value of
IDSS for JFET.
Assume JFET in the figure has a value of
IDSS=5:12mA, so as long as IC < 5mA, value
of IDQ is independently of JFET itself.
Advantage: provide the most stable Q-point
value of ID.
Disadvantage: circuit complexity makes it
undesirable for most applications.
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Example 8.13
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