Direct RF FPGAs built with Multi-Chip Packaging

Overcome Technology Challenges

Marjorie Catt Dustin Henderson
Altera Corporation, An Intel Company Altera Corporation, An Intel Company
Champaign, USA Seattle, USA
[Link]@[Link] [Link]@[Link]

Abstract—The wideband Altera™ Agilex™ 9 Direct RF-Series architectures for many years. More recently, they have also
portfolio is a leap forward which enables the implementation of developed products with ADCs and DACs integrated into a
direct RF systems in a single package RF FPGA. This development single package and data converters with integrated DSP
included the integration of existing technologies and creating functions which support direct IF architectures. As sample rates,
2024 IEEE High Performance Extreme Computing Conference (HPEC) | 979-8-3503-8713-1/24/$31.00 ©2024 IEEE | DOI: 10.1109/HPEC62836.2024.10938522

solutions for new challenges. resolution, and data rates have increased, most of these products
have shifted from a parallel data interface to the JESD serial
Keywords—ADC, DAC, FPGA, Direct RF, SWaP, Multi-Chip interface protocol. This reduces the number of digital data lanes,
Packaging but comes at the expense of signal path latency. Integrating the
I. INTRODUCTION FPGA core into the same package with the data conversion
solution is a newer development which supports direct IF
Altera™ has developed FPGAs with direct RF sampling architectures with improved SWaP.
capabilities by using multi-chip packaging to achieve
significantly reduced size, weight, and power (SWaP). The The Altera Agilex 9 Direct RF-Series stands out for its
analog-to-digital converter (ADC) and digital-to-analog extraordinary level of integration and high sample rate. It
converter (DAC) can sample at Fs = [40 Gsps, 64 Gsps] and uniquely enables the implementation of direct RF architectures
support RF frequencies up to 36 GHz. The Agilex™ 9 FPGA with low latency and excellent SWaP.
core fabric is designed with Altera’s second generation II. OVERVIEW OF AGILEX 9 DIRECT RF-SERIES FPGAS
proprietary Hyperflex architecture. The integration of these
technologies enables the implementation of direct RF sampling The wideband Altera Agilex 9 Direct RF-Series portfolio
systems up to Ka band in a single package device, refer to Fig. presently includes two devices, refer to Fig. 3. They are designed
1. with Altera Agilex 9 core FPGA technology, analog tile(s), and
transceiver tile(s).

Fig. 1. Direct RF FPGA coverage of RF bands

The sample rate (Fs), RF bandwidth, and resolution of the

data converters enables the implementation of a specific
architecture: superheterodyne, direct IF, or direct RF. Fig. 2
shows key current data converter products of similar resolution
available in the marketplace.

Fig. 3. Altera Agilex 9 Direct RF-Series FPGA Products

Each device includes one or two analog tiles to perform

direct RF sampling and DSP functions, also known as the A-
Tile. The AGRW014 includes Agilex 9 FPGA core fabric with
1.4 million logic elements (LE) and the AGRW027 includes
Agilex 9 FPGA core fabric with 2.7 million LE. The F-Tile
Fig. 2. Marketplace data conversion products transceiver supports up to 58G PAM-4 or 32G NRZ, PCIe 4.0,
and 400 GbE.
Analog companies have developed single- and multi-
channel ADCs and DACs which enable superheterodyne

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A. Direct RF Key Enabling Technologies The on-die distribution and PLL can be used to ease external
The Altera Agilex 9 Direct RF-Series products uniquely distribution and frequency requirements for the data converter
leverage multiple key technologies to implement a direct RF sample clock. However, the frequency flexibility and on-die
system in a single package and optimize SWaP, refer to Table 1. implementation of the PLL necessary to support the full sample
rate range of the device limit the phase noise (PN) performance
Table 1. Key Direct RF Enabling Technologies of the near-in frequency offset of the data converter sample
clock. In case optimized system noise spectral density (NSD) is
Key Technology Direct RF Enablement
required, a higher PN performance sample clock can be directly
Core FPGA technology Flexibility to configure system provided to each port.
with custom IP
The DDC and DUC are used to perform frequency tuning
3rd party IP quad DRF-XCVR with Leverages partner RF expertise on and decimation or interpolation, respectively, in the direct RF
ultra-wide RF bandwidth (A-Tile) optimized process node
sampling system. In an IF sampling system, the same functions
Embedded Multi-Die Interconnect >1k wires for ultra-wide data are performed using RF mixers and a switched filter bank which
and Advanced Interface Bus protocol bandwidth, low latency and power is costlier in terms of size, power, and RF performance. The
Heterogeneous 3D System-in- Tiles and FPGA integrated in coarse DDC includes an NCO with a frequency resolution of
Package (SiP) technology single package to optimize SWaP Fs/128. Each fine DDC channel include an NCO with a
frequency resolution of Fs/236 which rivals the infinite resolution
Including core FPGA technology enables customers with the of an analog VCO. NCOs with the same resolution are used in
flexibility to configure the system with their custom IP. Working the DUC. The DDC supports decimation from 8 to 1024 in
with a partner optimizes the RF performance and powers of 2, and bypass mode. The DUC supports interpolation
implementation of the A-Tile. Using the Embedded Multi-Die from 8 to 1024 in powers of 2.
Interconnect (EMIB) technology and Advanced Interface Bus C. IP Fundamentals
(AIB) protocol supports the required bus for ultra-wideband data
bandwidth and optimizes performance. Fig. 4 shows how the Altera provides a Direct RF soft IP core (DRF IP) with
EMIB is used to integrate multiple chips into a single package. standard interfaces to manage the A-Tile. The DRF IP is
The EMIB is embedded into the package substrate and the tiles comprised of three parts: data plane, control plane, and fast
and FPGA are bonded to it using micro bumps. control I/O. It can be instantiated in a Quartus® Platform
Designer system or using hardware description language (HDL)
code such as Verilog or VHDL, refer to Fig. 6.

Fig. 4. Multi-Chip Packaging with EMIB Technology

B. RF Fundamentals
Each A-Tile is comprised of four direct RF transceiver ports,
refer to Fig. 5. Each port includes an option for clocking
distribution and phase lock loop (PLL) or bypass to provide the
sample clock directly. The receive path is an RF ADC, coarse
digital down-converter (DDC), up to four fine DDCs, and the
AIB. The transmit path is the AIB, up to four fine digital up-
converters (DUCs), coarse DUC, and RF DAC.

Fig. 6. DRF IP Block Diagram

The data plane consists of streaming conduit used to transfer

data samples to and from the A-Tile. In addition to bandwidth
reduction from decimation or interpolation on the A-Tile, the
data is further reduced in frequency using a gearbox FIFO. The
gearbox delivers samples to the FPGA core fabric at Fs/128, or
up to 500 MHz. The data plane can be configured in one of two
modes: basic mode and native mode. Basic mode provides a pre-
defined and simplified interface per decimation and
interpolation ratio. Native mode allows the user to change ratio
at run time with a custom design.
The control plane of the DRF IP consists of four separate
Avalon® Memory Mapped interfaces (AVMM). The AVMM
Fig. 5. A-Tile and single port block diagram

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bus protocol is similar to the AXI 4 Lite standard and can be sample the same RF input, each at a lower rate and out of phase
easily integrated into both Quartus® Platform Designer systems by 360°/N. This allows the effective sample rate to be N-times
and custom RTL. Each of the four AVMM ports corresponds to that of the individual sub-converter ADC. The interleaving
a specific port on the A-Tile. Individual AVMM port control architecture also incurs spurious degradation in the spectrum
supports lower latency by simultaneously writing to all ports, in due to mismatch: DC offset mismatch (VOS), full-scale gain
addition to independent control per port. Each AVMM port is error (GERR), and phase error (φERR). The mismatch at each sub-
used to control actions such as NCO tuning, calibration, and port converter ADC can be calibrated to suppress the spurious
configuration. degradation. This scheme works well across several GHz of RF
The DRF IP implements fast control signals for latency bandwidth.
critical tasks. This interface features independent signals for
each port and acts similar to GPIO. Fast control functions
include: NCO swapping, ADC power state control, and DAC
power state control.
D. Agilex 9 FPGA Fabric
To support processing 32 GHz of bandwidth, Altera paired
the A-Tile with the latest in FPGA technology, refer to Table 2.
The Agilex 9 core boasts a second generation Hyperflex
architecture which has better performance lower power
consumption compared to Stratix®.
Table 2. Agilex 9 Direct RF Product Family
Fig. 8. ADC architecture showing interleave factor N = 4
AGRW014 AGRW027
# of ADC/DAC 4/4 8/8
The A-Tile ADC implements a significantly higher
interleave factor than 4 and supports 36 GHz of RF bandwidth.
Logic Elements (kLE) 1437 2693
At this next level of RF performance, an additional error term
Embedded Memory (Mb) 190 287
becomes more critical: bandwidth mismatch. The RF front-end
Package Size (mm) 45x32 52.5x42.5
of each sub-converter ADC has a slightly different frequency
18x19 Multipliers 9020 17056
response. This limits the effective range of the calibration
coefficients to several GHz of RF bandwidth. The A-Tile ADC
III. AGILEX 9 DIRECT RF-SERIES FPGA TECHNOLOGY: addresses this challenge by providing multiple sets of
CHALLENGES AND SOLUTIONS calibration coefficients to optimize RF performance across the
The Altera Agilex 9 Direct RF-Series products are a leap entire 36 GHz operating range.
forward in combined sample rate and resolution, RF
performance, and SWaP reduction. To implement this B. Frequency Hopping and Agility Mode
technology presented a number of new challenges which An IF architecture and an RF architecture both must
required innovative solutions. accomplish the same functions: frequency tuning and filtering,
refer to Fig. 7. These functions allow the user to more efficiently
A. Sample Rate, Interleaving, and Calibration process a specific portion of the RF bandwidth which is of
The A-Tile ADC can sample up to Fs = 64 Gsps with 10-bits interest at the moment. The IF architecture performs some of
of resolution and excellent NSD performance. This enables these functions in the RF domain using RF mixers and filters.
direct RF applications with up to 32 GHz of instantaneous The RF architecture performs all of the same functions in the
bandwidth (IBW). The A-Tile ADC architecture requires a high digital domain using a digital mixer, decimation filtering and
interleave factor to implement the technology at this sample rate interpolation filtering. When a different portion of the RF
and resolution. bandwidth becomes of interest, it is necessary to tune or “hop”
to that frequency as quickly as possible. For both architectures,
An example ADC interleave architecture is illustrated using
an interleave factor of 4, refer to Fig. 8. Multiple ADC cores

Fig. 7. IF and RF Architecture Block Diagrams

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the control latency to trigger a hop as well as the data path
latency are of critical importance.
The A-Tile ADC and DAC support Agility Mode, which is
a hardware-assisted method to quickly switch NCO frequencies,
ADC calibration coefficients, and other DAC settings which
optimize performance across frequency. A frequency hop in
Agility Mode can be triggered several different ways including:
fast control signal for lowest latency, and external SYSREF
which also supports multi-device synchronization.
C. Managing the Data Flow
The A-Tile ADCs and DACs support an IBW up to 32 GHz
and 8 GHz, respectively. This generates a massive amount of
digital data to ship across the AIB and process at the FPGA core
fabric. It is not possible to simultaneously use all of the ports at
the minimum decimation or interpolation and the maximum
digital word length. To ease the digital data flow in the receive
path, User Mode x1 limits the number of RF ports to one, and Fig. 9. DAC Slope Compensation Filter Profile Fs = 64 Gsps
utilizes the AIB of the other three ports for the digital data, refer
to Table 3. Another option to reduce the data flow per port is to E. Sample Clock Distribution, Generation, and Performance
decimate or interpolate the data. For User Modes x8H The A-Tile data converters support a sample rate up to Fs = 64
(decimate-by-8 half word) and higher, all four ports are again Gsps. Even using dual-edge sampling, this requires a sample
available to the user. clock up to 32 GHz to the data converters. To ease the external
Table 3. Coarse and Fine DDC details per User Mode
clocking requirements, the A-Tile has distribution and an
integer mode PLL on each port. For this clocking mode, it is
User Max Ports Coarse Fine Max Fine only necessary to provide a single reference clock to each A-
Mode per A-Tile Decimation Decimation Tuners per Port Tile on the order of several GHz. Because each port has its own
x1 1 N/A N/A N/A PLL, the noise between ports is uncorrelated. However, the on-
x8F 2 8 N/A N/A die PLL supports the full range of sample rates and its phase
x8H 4 8 N/A N/A noise (PN) performance is limited. The impact of the PLL’s PN
x16 4 16 N/A 1 can be observed in the noise skirt around the fundamental, refer
x32 4 16 2 2
to Fig. 10. In case the application’s performance requirements
cannot tolerate this noise, it is possible to bypass the PLL and
x64 4 16 4 4
directly provide the sample clock at Fs/2. The on-die
x128 4 16 8 4
distribution network has an extremely low amount of additive
x256 4 16 16 4
jitter.
x512 4 16 32 4
x1024 4 16 64 4

D. Transmit Path Gain Flatness

The A-Tile DAC supports direct RF applications up to 36
GHz of RF bandwidth. Many applications have gain flatness
requirements, which are difficult to achieve across such a wide
operating RF range. The DAC incurs sinc roll-off and there are
additional RF losses in the silicon and package.
The A-Tile DAC has an inverse sinc filter and DAC Slope
Compensation (DSC) feature to manage gain flatness in the
transmit path, refer to Fig. 9. DSC is also supported in Agility
Mode, so it is possible to select different beta values while
frequency hopping.

Fig. 10. Typical Noise Impact of on-die PLL

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F. Tracking Saturation Events The higher level of integration is compelling for many
Many ADCs with a lower sample rate send an additional reasons. Integrating the RF sampling circuitry into the package
over-range bit with each data sample. This is a useful flag to with the FPGA core fabric supports the lowest latency and
notify external gain circuitry to reduce the signal level. It can power consumption. This also simplifies the system board level
also be used to tag the processed data where the linearity of the design because the routing and signal integrity tasks are
data samples was degraded due to the over-range event. Due to handled within the single package design. A trade-off to higher
the high sample rate and premium on power consumption, this integration is reduced access to the signal path. Implementation
feature is not practical for the A-Tile ADC. Instead, it detects of a new architecture must take into consideration the
ADC saturation, average power, and DSP saturation events per application requirements to mitigate the drawbacks as much as
multiple samples per port, refer to Fig. 11. Notification of these possible.
events is shared with the DRF IP and ADC saturation can be
optionally sent to a GPIO port. IV. CONCLUSION
The wideband Agilex 9 Direct RF-Series portfolio is the next
generation of direct RF sampling systems. It delivers a new level
of integration and sample rate. This development leverages key
existing technologies: core FPGA fabric, A-Tile partnership
with industry expert, EMIB and AIB for interconnect and
package integration. It also overcame new challenges to sample
at rates up to Fs = 64 Gsps across 36 GHz of RF bandwidth while
handling the data flow by providing new features and flexible
configuration.
REFERENCES

[1] "IEEE Standard for Terminology and Test Methods of Digital-to-Analog

Converter Devices," in IEEE Std 1658-2011 , vol., no., pp.1-126, 10 Feb.
2012, doi: 10.1109/IEEESTD.2012.6152113.
[2] Walt Kester, The Data Conversion Handbook, Burlington, MA,
USA:Elsevier, 2005.
Fig. 11. A-Tile ADC Saturation Detection

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