2023 최신 반도체 집적회로 설계기술 워크샵

Low-Dropout (LDO) Voltage Regulators

– From Basics to Recent Design Trends
(presented in A-SSCC 2022)

Prof. Hyun-Sik Kim

(hyunskim@[Link])

November 22, 2023

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 1 of 94
Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 2 of 94

Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 3 of 94

What is the Voltage Regulator?
LDO, Buck: VIN > VOUT
VIN Boost: VIN < VOUT

Fixed (Regulated) VIN LDO input

Regulator
VOUT
ILOAD VOUT LDO output

time

 Ideal Regulator?: an voltage source (VOUT) used to be VDD of a load system

 Keep VOUT fixed voltage under any situations
◼ VIN varies, but VOUT is fixed → Regulator’s Line Regulation
◼ ILOAD varies, but VOUT is fixed → Regulator’s Load Regulation
 Always “VIN > VOUT” due to the LDO’s resistive voltage generation

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 4 of 94

Key Features of LDO Regulator
size ↓ →
LLsize → ffswsw ↑
Clear
LDO VDD1 Image
Battery Switching Regulator Sensor
DC-DC w/ High-PSR #1
Converter
VDD2 Image Noisy
ΔVRIPPLE LDO
Regulator Sensor
high fsw @ heavy load w/ Low-PSR #2
low fsw @ light load Noise-sensitive load

 Ripple Suppression (Power-Supply Rejection, PSR) → Used as a Post-Regulator

 Impedance Isolation (Low ZOUT like as a buffer )
 Low Output Noise (No switching operation) → Useful for noise-sensitive loads

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 5 of 94

Usages of LDO Regulator
 Discrete LDO chips  SoC-Integrated LDO IPs

LDO
(Microchip)
LDO
(Microchip)

LDO (TI)

Integrated LDOs
Velodyne LIDAR Puck VLP-16 Sensor AMD 7-nm Zen 2
(source: Tech Insights) (ISSCC’20)
◼ Clean voltage-supply (low-noise of LDO) ◼ Per-Core voltage-scaling (compactness)
◼ Step-down DC-DC conversion
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 6 of 94
Conceptual Realization of LDO Regulator (1/2)
VOUT-sense
 Unregulated RIN ☺ Regulated & α-control

+ +
α·RL
VIN VOUT RL VIN VOUT RL

RL 1
VOUT = VIN VOUT = VIN
R IN + RL α+1

 VOUT generated using a resistive divider

◼ Fixed divider ratio → sensitive to load current (RL) changes

 Feedback loop regulates RIN (= α·RL) such that it is always a desired fraction
of load current
◼ VOUT is independent to load current (RL)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 7 of 94

Conceptual Realization of LDO Regulator (2/2)

Pass Element (transistor)

RIN
+
EA RF1
VIN VOUT RL CL
+ RF2
VREF

 RF1 + RF2 
 Feedback loop adjusts RIN such that VOUT =  VREF
◼ VOUT is ideally independent to VIN
 RF2 
◼ Feedback resistors (RF1 + RF2) >> RL

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 8 of 94

Comparison of Power Converter Topologies (1/2)

Linear Regulator Switched Inductor Switched Capacitor

(LDO) DC-DC (e.g., Charge-Pump)
Transfer
Resistive Inductive Capacitive
Media
Efficiency Low  High ☺ Medium
Very Low ☺
Noise High  Medium
(no switching)
Output
Low to Medium Low to High Low
Current
Step-Up X O O

Step-Down O O O

Footprint Small ☺ Large  Medium

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 9 of 94

Comparison of Power Converter Topologies (2/2)

CPU @ 24MHz CPU @ 48MHz

LDO Regulator 165 μA/MHz 158 μA/MHz

Switched Inductor
DC-DC
92 μA/MHz 96 μA/MHz

 LDO regulator: small footprint & low noise, but low efficiency
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 10 of 94
Basic Architecture of LDO Regulator
VIN
PMOS Pass
Element
BGR
VREF +
Dropout Voltage
EA rDS VDO = VIN – VOUT
+ –
VOUT
R1
CL IL
 R1 + R 2  R2
VOUT =  VREF
 R2 

◼ Bandgap (BGR): fixed reference voltage VREF

◼ Error-Amplifier (EA): comparing VREF vs. VOUT, and providing feedback loop-gain (T)
◼ CL: used to “filter” ripple and noise

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 11 of 94

Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 12 of 94

Key Performance Metrics
 Regulation (in DC-domain)  Transient response
◼ Line/load regulation ◼ Voltage droop & Recovery time
◼ Loop-bandwidth (GBW)
 Voltage (VOUT) accuracy
◼ Slew rate
 Dropout voltage (VDO)
 Stability
◼ Power efficiency
◼ Load (IL) dynamic range
 Quiescent current (IQ) ◼ Output capacitor (CL)
◼ Current efficiency
 Power supply rejection (PSR)
 Input/output range
◼ Input (VIN) range  Output noise
◼ Output (VOUT) range ◼ RMS noise voltage within BW

◼ Max. output current (IL,MAX)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 13 of 94

Performance Metrics: Line Regulation (1/2)

(source: TI tech. review)

 Ability to maintain desired VOUT with varying VIN

◼ Line Regulation = ΔVOUT/ΔVIN
◼ Unit: [mV/V] or [%/V]

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 14 of 94

Performance Metrics: Line Regulation (2/2)
VIN
PMOS Pass
+ Element
BGR
VREF gmp
– R2
EA β=
rDS R1 + R 2
+ AEA0
VOUT
R1
( ΔVIN − ΔVOUT  βAEA0 ) gmp RL || rDS || (R1 + R 2 )  = ΔVOUT CL IL
R2

ΔVOUT gmp RL || rDS || ( R 1 + R 2 )  1

 Line Regulation = = 
ΔVIN 1 + βAEA0gmp RL || rDS || ( R 1 + R 2 )  βAEA0
 

 Changes in VIN suppressed by error-amp (EA)’s gain (AEA0)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 15 of 94

Performance Metrics: Load Regulation
VIN
PMOS Pass
Element
V
BGR REF
gmp
R2
EA β=
rDS R1 + R 2
+ AEA0
VOUT
R1
(source: TI tech. review) CL IL
ΔVOUT
ΔIL = + ΔVOUT  β  AEA0  gmp R2
rDS || ( R 1 + R 2 ) 

 Ability to maintain desired VOUT with varying IL

ΔVOUT rDS || ( R 1 + R 2 ) rDS
 Load Regulation = = 
ΔIL 1 + βAEA0gmp rDS || ( R 1 + R 2 )  1 + T0
 Dependent of feedback loop-gain (T0)
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 16 of 94
Performance Metrics: Voltage Accuracy
VIN
PMOS Pass
Element
BGR
VREF
◼ Line/Load regulation: ΔVLR, ΔVLDR EA rDS
◼ Reference voltage drift: ΔVO,REF +
VOUT
◼ Error-Amp offset drift: ΔVO,EA
R1
◼ Feedback resistor tolerance: ΔVO,R CL IL
R2

ΔVLR + ΔVLDR + ΔVO,REF2 + ΔVO,EA 2 + ΔVO,R 2

 LDO’s accuracy =  %
VOUT

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 17 of 94

Performance Metrics: Power Efficiency (η)
VIN
IIN PMOS Pass
Element
BGR
VREF + Dropout Voltage
EA rDS VDO = VIN – VOUT = VDS of PMOS
+
– VOUT
R1 IL
CL IL
IQ Quiescent current R2
(ground current)

VOUT  IL
=
VOUT  IL
=
( VIN − VDO )  IL
 Efficiency (η) = [%]
VIN  IIN VIN  ( IL + IQ ) VIN  ( IL + IQ )

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 18 of 94

Performance Metrics: Min. Dropout (VDO,min)
VIN
PMOS Pass
Element
BGR
VREF +
VDO,min EA rDS VDO = VIN – VOUT
+ VG ≈ 0 –
V OUT

R1
CL IL
R2
(source: TI tech. review)

 Min. dropout voltage (VDO,min): minimum regulating point @ full-load (IL,max)

◼ At VDO,min & IL,max, the EA’s output (VG) reaches the minimum limit (≈ 0V)
◼ Conventional LDOs have VDO,min of 50mV ~ 200mV
◼ High aspect ratio (W/L) of pass element → large parasitic capacitance (CG) 

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 19 of 94

Performance Metrics: Power-Supply Rejection
Lower is Better
0 dB fsw
Typical

PSR (VOUT/VIN) [dB]

LDO PSR rather amplified ΔVOUT(fsw)
More
Desirable reduced

highly rejected

VIN LDO VOUT

fLow fMid fHigh Regulator

ΔVIN(fsw)
ΔVOUT (f)
 Power-supply rejection = PSR(f) =
ΔVIN (f)
◼ Similar to line regulation, but measured ∆VOUT for small-signal ∆VIN variations
◼ PSR = ripple rejection capability
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 Performance Metrics: Transient Reponses
 Line (∆VIN) transient response  Load (∆IL) transient response

Voltage dip/spike

Voltage dip/spike

Line Regulation Load Regulation

(source: TI tech. review)

◼ ∆VOUT is dependent of load-step(∆IL), CL, loop bandwidth (GBW), and slew rate (SR)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 21 of 94

Various Types of LDO (1/4)

 Triode LDO  Saturation LDO

RIN Variable CS

+ +
EA RF1 EA RF1
VIN VOUT RL CL VIN VOUT RL CL
+ RF2 + RF2
VREF VREF

◼ Pass element works in triode region ◼ Pass element works in saturation region
◼ Small VDO (high η) ☺ ◼ High VDO (lower η) 
◼ Low regulation due to low loop-gain ◼ Good regulation performance due to
(T)  high loop-gain (T) ☺
◼ Bad PSR due to small RDS  ◼ Good PSR owing to large RDS ☺
◼ Normally not preferred ◼ Adopted in most LDOs

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 22 of 94

Various Types of LDO (2/4)
 P-type LDO  N-type LDO
VIN VIN
CP
VREF VDD >VIN
PMOS Pass VREF NMOS Pass
EA Element EA
+ Element
+
VOUT VOUT
R1 R1
CL IL CL IL
R2 R2

◼ Pass element = PMOS ◼ Pass element = NMOS

◼ Better regulation performance ◼ Lower regulation performance 
(higher loop-gain) ☺ ◼ Easier stability design ☺
◼ Stability design issue  ◼ Additional charge-pump (VDD) 

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 23 of 94

Various Types of LDO (3/4)

 Cap LDO  Capless LDO

RIN RIN
+ +
EA RF1 EA RF1
VIN VOUT RL CL VIN VOUT RL
+ RF2 + RF2
VREF VREF

◼ External capacitor (CL) is required ◼ No “external” component (CL)

◼ Larger PCB footprint  ◼ Compact or fully-integrated ☺
◼ Low voltage droop @ ∆IL ☺ ◼ High voltage droop @ ∆IL 
◼ Good PSR @ high freq. ☺ ◼ Bad PSR @ high freq. 
◼ Narrow bandwidth  ◼ Wider (faster) bandwidth 
◼ Stability issue over wide IL  ◼ Easier stability compensation ☺

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 24 of 94

Various Types of LDO (4/4)
 Analog LDO  Digital LDO

◼ Analog control & single pass-TR. ◼ Digital control & segmented pass-TR.
◼ Excellent PSR ☺ ◼ Scalable design @ various CMOS tech. ☺
◼ No ripple & clean VOUT ☺ ◼ Digitally synthesizable ☺
◼ Re-design @ different tech. nodes  ◼ Limit cycle oscillation (LCO) ripple 
◼ Hard to work in low VIN  ◼ Friendly to low VIN ☺
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 25 of 94
Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 26 of 94

Feedback Loop-Gain’s Transfer Function: T(s)
VIN ωP2
gmEA rEA
BGR
VREF gmp
ωP1
EA rDS
+
AEA = gmEArEA Cgg VOUT
R OUT = rDS || ( R 1 + R 2 ) || R L R1
R2 VX VY CL IL
β=
R1 + R 2 R2

 Transfer function of feedback loop-gain:

1 1
T ( s) = −
VY
= AEA  gmpR OUT  β
1 , where ω = ωP2 =

P1
R OUT  CL rEA  Cgg
VX s  s 
 1+   1+ 
 ω P1   ωP2 
*Note: Cgg becomes higher for low VDO & high IL
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 27 of 94
Basics of Frequency Response
ωP2 T0 = β  gmEA rEA  gmprOUT

Loop Gain [dB]

VIN
gmEA rEA
BGR
VREF gmp ωP1
EA rDS
+
Cgg VOUT ωUGF
R1 X X | ω [rad/s]
ωP1 ωP2
VX VY CL IL
R2
1 1
ωP1 = ωP2 =
rOUT  CL rEA  Cgg

 Unity-gain frequency (ωUGF, GBW) determines the LDO’s transient response

◼ Wide bandwidth (high ωUGF) = fast transient speed
 Closely-spaced poles compromise stability
◼ “ωUGF ≤ non-dominant pole” is desirable: just 1-pole under ωUGF
◼ Frequency (stability) compensation is necessary

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 28 of 94

Load Current (IL) Dependency of Output Pole
T0 = β  gmEA rEA  gmprOUT

Loop Gain [dB]

VIN
gmEA rEA Heavy load (high IL)
BGR
VREF gmp ωP1 Light load (low IL)
EA rDS
+
Cgg VOUT ωUGF
R1 X X | X | ω [rad/s]
ωP1 ωP2 ωUGF ωP1
VX VY CL IL
R2
1 IL
ωP1 = =
rOUT  CL VA  CL

 Total ROUT (open-loop) = R OUT = rDS || ( R 1 + R 2 ) || R L

 Why cap-LDO (w/ CL) is difficult to be stable?

◼ Load current (IL) variation significantly changes the pole of ωP1
1 1 IL
ωP1 =  =
R OUT  CL rDS  CL VA  CL

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 29 of 94

Stability Compensation I: Zero-Insertion (1/3)
 Zero (ωZ) insertion by adding ESR (equivalent series resistance) in CL

VIN
ωP2 T0 = β  gmEA rEA  gmprOUT

Loop Gain [dB]

gmEA rEA
BGR
VREF gmp ωP1
EA rDS
+
Cgg VOUT
ωUGF

ESR
R1 X X O | ω [rad/s]
IL ωP1 ωP2 ω Z

R2 CL 1
ωZ =
RESR  CL

1 1
ωP1 = ωP2 =
R OUT  CL rEA  Cgg  ωUGF 
−1
PM  tan  
1  ω Z 
ωZ =
RESR  CL

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 30 of 94

Stability Compensation I: Zero-Insertion (2/3)
 Choose the right ESR to secure the phase margin
w/o ESR compensation  w/ ESR compensation (desirable) ☺

Loop Gain [dB]

Loop Gain [dB]
Stable region of ESR

ωUGF ωUGF ωP3

X X | ω [rad/s] X X O | X ω
ωP1 ωP2 ωP1 ωP2 ω Z

w/ too high ESR (unstable)  w/ too low ESR (unstable) 

Loop Gain [dB]

Loop Gain [dB]

ωUGF ωZ
X XO X | ω X X | O ω
ωP1 ωP2ωZ ωP3 ωP1 ωP2 ωUGF

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 31 of 94

Stability Compensation I: Zero-Insertion (3/3)
 Tunnel-of-Death graph: desirable range of stable ESR
◼ ESR on CL may cause a large spike/dip at load transient response 

Kim & Kim, IEEE TPEL 2020 Texas Instrument, LDO

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 32 of 94

Stability Compensation II: Gate Buffering
 Shield Cgg from loading the error-amplifier output using a Buffer
VIN
Buffer R B R O,EA
VREF Buffer RB Buffer CB Cgg
BGR VEA VG
EA rDS
+
RO,EA Cgg VOUT
R1
CL IL
R2
1
◼ w/o gate buffering: ωP2 = (low-frequency one pole)
CggR O,EA

1 1
◼ w/ gate buffering: ωP2,A = ωP2,B = (high-frequency two poles)
CBR O,EA CggRB

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 33 of 94

SSF-based Gate Buffer Design (1/3)
 Gate buffer design with Super Source Follower (SSF)

ωG = gmB/Cgg

ωX = 1/(rXCX)
1 1 1 1
RB =  = 
gmB TSSF gmB gmSrX
 Local feedback loop further reduces RB by loop-gain (TSSF)
 SSF loop-gain (TSSF) has closely-spaced two poles: ωG & ωX
◼ Local stability should be also considered in the design of SSF-based gate buffer 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 34 of 94
SSF-based Gate Buffer Design (2/3)
 AC-peaking at SSF output ◼ Impedance analysis TSSF ( jωUGF )  1
1 1

Output Z (RB) [Ω]

jωCgg gmB
ωG = gmB/Cgg
1 1
gmB TSSF,DC
RB(s) Cgg
X ω
Dominant-pole of TSSF loop

◼ Closed-loop analysis
AC-peaking

Loop Gain [dB]

(ΔPhase ≈ 180°)
TSSF (s)
1 1 ωX = 1/(rXCX)
RB =  TSSF,DC = gmSrX
gmB TSSF (s)
ωUGF
X X | ω
AC-peaking ➔ ωX ωG
Complex pole-pair effect at VG/VEA(s)  VG T (s)
(s) = SSF
VEA 1 + TSSF (s)
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 35 of 94
SSF-based Gate Buffer Design (3/3)
 AC-peaking solution: Capacitive impedance (1/sCgg) does not cross the inductive RB
TSSF ( jωUGF )  1 TSSF ( jωUGF )  1
1 1 1
Output Z (RB) [Ω]

Output Z (RB) [Ω]

jωCgg gmB gmB
1
1 1
gmB TSSF,DC
RB(s) Cgg jωCgg

X ω X ω
Dominant-pole of TSSF loop Dominant-pole of TSSF loop

AC-peaking TSSF (s)

Loop Gain [dB]

Loop Gain [dB]

(ΔPhase ≈ 180°)
TSSF (s)
No AC-peaking
(ΔPhase ≈ 90°)
VG gmS gmB
(s) =
ωG C
VEA ωUGF CX gg
X X | ω X | X ω
ωX ωG VG ω 1
(s) X=
VEA rXC X
Unstable Case  Stable Case ☺
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 36 of 94
Dual-Loop Gate Buffer Design (1/4)
 Kim & Kim, IEEE TPEL 2020
Loop-Gain
VIN Original LM
Power gm21·rds20 X
M22 M19 PMOS
VG X
VBP MP ωt
LM Cgg
IB2 VBI VOUT 0 dB ω
M18 ωp1 ωp2
M21
VBN 0° ω
Cp
M20

Phase
-90°
-180°
Original LM
◼ Conventional SSF-based gate buffer
◼ Single-loop (LM)
◼ Two poles are closely spaced → instability issue & GBW (ωt) limit

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 37 of 94

Dual-Loop Gate Buffer Design (2/4)
 Kim & Kim, IEEE TPEL 2020
Loop-Gain
VIN Original LM
Power gm21·rds20 X X
M22 M19 PMOS
RS VG X
VBP CS MP O ωt
gm21·(rds20||RS) LM ωp3
LM Cgg
IB2 VBI M18
VOUT 0 dB ω
ωp2' ωz1 ωp1 ωp2
M21
VBN 0° ω
Cp
M20

Phase
-90°
-180°
Original LM
◼ Insertion of RS and CS
◼ CS works for dominant-pole compensation (ωp2 ➔ ωp2’)
◼ RS introduces a zero (ωz1)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 38 of 94

Dual-Loop Gate Buffer Design (3/4)
 Kim & Kim, IEEE TPEL 2020
Loop-Gain
VIN
Power gm21·rds20
M22 M19 PMOS
RS VG gm19·(rds20||RS)
VBP CS LS MP ωt' ωp3
gm21·(rds20||RS)
LM Cgg LS LM
IB2 VBI M18
VOUT 0 dB ω
ωp2' ωz1 ωp1
VB M21
VBN 0° ω
Cp
M20

Phase
-90°
-180°
Original LM
◼ An additional loop of LS forms and co-exists with LM-loop
◼ Dual-loop design (LM + LS)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 39 of 94

Dual-Loop Gate Buffer Design (4/4)
 Kim & Kim, IEEE TPEL 2020
Loop-Gain
VIN (LS+LM)
gm21·rds20 X Original LM
M22 Power X
M19 VG PMOS gm19·(rds20||RS)
RS
LS MP ωzcO X X
VBP CS gm21·(rds20||RS) ωt ωt' ωp3
LM Cgg LS LM
IB2 VBI M18
VOUT 0 dB ω
ωp2' ωz1 ωp1 ωp2
VB M21
VBN 0° ω
Cp
M20

Phase
-90°
(LS+LM)
-180°
Original LM
◼ Low-frequency region dominated by LM
◼ LS covers high-frequency region
◼ Proposed dual-loop offers faster response (ωt’) with higher stability (PM ≈ 90º) ☺

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 40 of 94

Stability Compensation III: Miller Effect (1/2)

Loop-Gain
X @ IL > 0
R2
CM R1
+ ωP2 ωP2

gmP
+ ωP1 VOUT 0 dB ω
ωP1
gm1
X
VREF RL
rO1 CA
IB COUT
1/IB ITH α
Atten.

MB M2 M1

 Miller compensation (pole-splitting) by CM is one of viable options in LDO design

1
◼ Dominant pole: ωP1 
rO1  (1 + gmpROUT ) CM
gmp
◼ Non-dominant pole: ωP2 
CL
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 41 of 94
Stability Compensation III: Miller Effect (2/2)

Loop-Gain
X @ IL > 0
X R2
CM R1
+ ωP2

gmP
+
VOUT 0 dB ω
ωP1
gm1
X
VREF RL
rO1 CA IL 0
IB COUT No Miller Effect

Loop-Gain
1/IB ITH X
α
Atten.
X
@ IL 0
MB M2 M1 0 dB ω
ωP2 ωP1
 No Miller-Effect issue at deep light loads
◼ At light-load (IL ≈ 0) → gmp ≈ 0 (no gain in Pass-Element) → No Miller Effect
◼ Miller compensation is difficult to cover IL ≈ 0 
◼ Otherwise, large static current via R1 and R2 must be consumed 

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 42 of 94

Stability Compensation III: Miller w/ LLSL (1/3)
 Kim & Kim, VLSI 2019

Loop-Gain
@ IL 0
R2 X
CM + R1 ωP1

gmP
+
VOUT 0 dB ω
ωP2 ωP1 X
gm1
VREF RL
rO1 CA IL 100°

IB COUT IL,trip ≈ 4mA

Phase Margin (PM)

80°
1/IB ITH α 60°
LLSL on

@IL 0 Atten. with COUT = 1μF

PMmin
40°
≥ 40°

MB M2 M1 20°
LLSL off

2μA 20μA 0.2mA 2mA 20mA 200mA

 Light-load stabilizer loop (LLSL) w/ Miller Load Current IL (log-scale)

◼ If IL < pre-defined ITH, LLSL is activated and

then IB (= ITH – IL) is added to gm1 to reduce rO1
◼ Proposed LLSL can guarantee sufficient phase margin even at IL ≈ 0 ☺

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 43 of 94

Stability Compensation III: Miller w/ LLSL (2/3)
 Kim & Kim, VLSI 2019
Miller Compensation Loop RS VBP
VIN
CA gm5

gm8
VBP CM
Power
Cgg PMOS
rO1 gm2 VBP rO4
gm1 VREF CS gmP
gmC rO2 VOUT IL
M1

ITH
IB IB VBI gm6 CF R RL
1
VBN

gm7
MB MB

COUT
VBP gm3 gm4 rO6 R2
-A0 M2 VBN

Light-Load Stabilizer Loop (LLSL) Compare-and-subtractor

IB-boosting circuit Load-current (IL) sensor
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 44 of 94
Stability Compensation III: Miller w/ LLSL (3/3)
 Kim & Kim, VLSI 2019

R2
20 mV/div

LLSL Off R1
CM +

gmP
+
VO1 VOUT

gm2,3
VOUT LLSL On VREF RL
rO1 CA IL
IB1 COUT

~
200 mA/div

t = 10 ns Heavy-load 1/IB1 ITH IL-Sensor

@ IL 0
IM4,5 Atten.
IL Δ0.3 A M23
Light-load M6,7 M24

20 μs/div

◼ At load transition from 300mA to 0A, a ringing is well suppressed by LLSL ☺

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 45 of 94

Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 46 of 94

Understanding Load-Transient Response (1/6)
 Light-to-heavy load transition

VIN VOUT
IL,light
VREF
EA Pass-Element
+
VOUT
IL,light IL,heavy
RESR
R1
CL IL Load
R2 Current IL,light

◼ At the steady-state, VOUT is stabilized and no current via CL

◼ PMOS’s supply current = Load current = IL,light

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 47 of 94

Understanding Load-Transient Response (2/6)
 Light-to-heavy load transition

VIN VOUT
IL,light VESR
VREF
EA Pass-Element
+
VOUT
IL,heavy
RESR
R1
+ IL,heavy
CL IL Load
R2 Current IL,light
IL,heavy – IL,light
◼ A load transition from light to heavy current occurs
◼ Initially CL reacts to cover the current mismatch between PMOS and load
◼ Large voltage droop (∆VESR) appears at VOUT: ΔVESR  RESR iL,heavy − iL,light ( )
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 48 of 94
Understanding Load-Transient Response (3/6)
 Light-to-heavy load transition
Tdip
VIN VOUT
IL,light
VREF SR Vdip
EA Pass-Element
+ VG
VOUT
IL,heavy
RESR
BW R1
IL,heavy
CL IL Load
R2 Current IL,light

◼ VOUT falls until PMOS current reaches IL,heavy

1 ΔVG 1
◼ Voltage-droop period: Tdip  TSR + = Cgg + , where TSR = slew time
BW@ light −load ISR,EA BW@ light −load

iL,heavy − iL,light
◼ Droop voltage: ΔVdip =  Tdip + ΔVESR
CL *Note: LDO’s loop-BW is dependent of IL
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 49 of 94
Understanding Load-Transient Response (4/6)
 Light-to-heavy load transition

VIN VOUT Load reg. (DC)

IL,heavy
VREF
EA Pass-Element
+ VG Trecover
VOUT
IL,heavy IL,heavy
RESR
BW R1
CL IL Load
R2 Current IL,light

◼ Fine-settling time (Trecover) is dominated by LDO’s loop-BW and phase margin (PM)
◼ VOUT’s DC error after fine-settling is caused by limited load-regulation performance
(insufficient loop-gain in DC-domain)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 50 of 94

Understanding Load-Transient Response (5/6)
 Heavy-to-light load transition
VIN
IL,heavy Vspike
VREF
EA Pass-Element
+ VG
VOUT VOUT
IL,light
IL,heavy Tspike
RESR
R1
CL IL Load
R2 Current
IL,light IL,light
IL,heavy – IL,light
1 ΔVG 1
◼ Overshoot period: Tspike  TSR + = Cgg +
BW@ heavy −load ISR,EA BW@ heavy −load

iL,heavy − iL,light
◼ Overshoot voltage: ΔVspike =  Tspike + ΔVESR Dominated by slew-rate (SR) and BW…
CL

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 51 of 94

Understanding Load-Transient Response (6/6)
 Heavy-to-light load transition
VIN

VREF
EA Pass-Element Load reg. (DC)
+ VG
VOUT VOUT
IL,light Tdischarge
RESR
R1 IL,heavy
CL IL Load
R2 Current IL,light

◼ Typical LDO has no sinking capability (only pull-down path is R1 and R2)
ΔVspike ΔVspike
◼ Return-to-base period: Tdisch arg e  CL = CL
iR2 VREF
R2
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 52 of 94
Figure-of-Merit (FoM)
 Load-transient response
iL,heavy − iL,light
ΔVdip =  ΔTdip + ΔVESR
CL
1 ΔVG 1
Tdip  TSR + = Cgg +
BW@ light −load ISR,EA BW@ light −load

 LDO’s FoM in terms of load-transient response

CL  ΔVdip  IQ
FoM =
ΔIL,max 2
Tdip  IQ
1) Pass element’s Cgg needs to be higher to 
accommodate larger IL,max ΔIL,max 2) FoM shows the efficiencies of SR and BW
against IQ consumption…

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 53 of 94

Zero-IQ Ultra-High Slew-Rate Buffer (1/5)
 Koh & Kim, ISSCC’21 & JSSC’21
A
VIN = VI+ VI- IDCCA
VI VI+

IDCCA
Mn3 Mn2 -VDZ VDZ VIN

VOUT
VDZ VX VOUT
Mp2 Mp3 CL VH
MX IX VDZ
VI+ Type A
VL Time
VIN >VDZ = VTH,n2+VTH,p3
◼ Zero-IQ at steady-state at |∆VIN| < VDZ & Large dynamic current IDCCA ∝ ∆VIN2 ☺
◼ Dead-zone (VDZ) is too large 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 54 of 94
Zero-IQ Ultra-High Slew-Rate Buffer (2/5)
 Koh & Kim, ISSCC’21 & JSSC’21
B
VIN = VI+ VI- IDCCA VTH.n
VI VI+

IDCCA
Mn3 Mn2 -VDZ VDZ VIN

VOUT
VTH,n VOUT Type B
Mp2 Mp3 CL VH
VTH,n
VI+
VL Time
VIN > VDZ VTH,n
◼ VTH of transistors can be cancelled by inserting the series voltage sources ☺
◼ Dead-zone (VDZ) still remains 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 55 of 94
Zero-IQ Ultra-High Slew-Rate Buffer (3/5)
 Koh & Kim, ISSCC’21 & JSSC’21
C
VIN = VI+ VI- IDCCA
VI VI+ VR

IDCCA
Mn3 Mn2 -VDZ DecreaseVDZ VIN

VOUT
VTH,n VR VOUT Type C
Mp2 Mp3 CL VH V
R

VI+
VL Time
VIN > VDZ VTH,n VR
◼ Recursive-current-controlled voltage sources are introduced
◼ Near-zero dead-zone (VDZ ≈ 0) ☺ & Ultra-high slewing current (IDCCA) ☺
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 56 of 94
Zero-IQ Ultra-High Slew-Rate Buffer (4/5)
 Koh & Kim, ISSCC’21 & JSSC’21
C
VIN = VI+ VI- Mp4 Mp7 VDD
IBD Mp23
VI VI+ Mp5 Mp6

IDCCA
Mn3 Mn2 VRCN
Mn3

RCN

VOUT
VOUT
VTH,n VR Mp1 Mn1 Mn2 Mp2
CL
Mp2 Mp3 VRCP Mp3

RCP
CL VI- VI+

Mn4 Mn5 Mn6Mn7 Mn23

VIN > VDZ VTH,n VR IBD GND
◼ Mn5-Mn6 & Mp5-Mp6 forms recursive (positive) feedback loops
◼ Near-zero dead-zone (VDZ ≈ 0) ☺ & Ultra-high slewing current (IDCCA) ☺
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 57 of 94
Zero-IQ Ultra-High Slew-Rate Buffer (5/5)
 Koh & Kim, ISSCC’21 & JSSC’21

CL = 800pF VDD
4.5V IBD
Mp4 Mp7 Mp23
Mp5 Mp6

Mn3
VRCN

RCN

VOUT
0.3V SR+ 0.021V/μs

1V SR- 0.03V/μs Mp1 Mn1 Mn2 Mp2

100μs
VRCP Mp3 CL

RCP
Proposed 1V
200ns
VI- VI+
INPUT
Mn4 Mn5 Mn6Mn7 Mn23
SR+ 10.3V/μs SR- 10.2V/μs IBD GND
◼ SR+ (rise) 10.3V/μs at 800pF, SR- (fall) 10.2V/μs at 800pF
◼ IQ consumption = 30nA & Max. slewing current = 9mA (= 300,000 x IQ) ☺
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 58 of 94
Low-IQ Gm-Boosted OTA Design (1/4)
(1 : K)
IB

VI VI+ VOUT IDC [(3+K)/2]·IB

Mp8 Mp9 Gm K·gmp

( 1 : 1) ( 1 : K )

 Typical mirror-type OTA design (A)

◼ Effective Gm can only be amplified by output-stage mirror-ratio (K)
◼ To increase Gm, larger IDC is required (Gm ∝ IDC → low FoM) 

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 59 of 94

Low-IQ Gm-Boosted OTA Design (2/4)
(1 : 1) ( 1 : K )

IB
VI+ VPX IDC (3+K)·IB
VI VOUT
Mp8 Mn8 Mn9 Mp9 VNX Gm K·(gmn+gmp)
IB

(1 : 1) (1 : K)

 Rail-to-rail mirror-type OTA design (B)

◼ N-type & P-type differential pairs synergies to improve the effective Gm
◼ But, the quiescent current (IDC) is also increased 

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 60 of 94

Low-IQ Gm-Boosted OTA Design (3/4)
 Koh & Kim, ISSCC’21 & JSSC’21
( 1 : Ka : Kb ) ( 1 : K )
Mp16
IB
VPX
VI VI+ VOUT IDC [2+Kb+K·(1+Kb-Ka)/2]·IB

Mp8 Mn8 Mn9 Mp9 VNX Gm K·(1+Ka+Kb)·(gmn+gmp)/2

IB
Mn14 Mn16
(1 : Ka : Kb)(1 : K )

 Proposed low-IQ Gm-boosted OTA design (C)

◼ Signal can be amplified by Ka, but the DC current is reduced by a ratio of Ka ☺
◼ If Ka = Kb = 1 ➔ 1.5x higher Gm compared to (B) for the same IDC

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 61 of 94

Low-IQ Gm-Boosted OTA Design (4/4)
 Koh & Kim, ISSCC’21 & JSSC’21
Conventional Proposed
Gms Gmn Gmp Gm_Eff Gms (K/2)Gms
VI+ VI-
VI- VI+

P+ N- P- P+ N-

VOUT

VOUT
IB (2-K)IB
IB IB 2 2
1:1 1:K 1:1
ML1 ML4 Mn14 Mn16 ML1 ML4
 Proposed low-IQ Gm-boosted OTA design (C)
◼ Signal can be amplified by K, but the DC current is reduced to (2-K)/2

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 62 of 94

Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 63 of 94

Supply-Ripple Delivery Paths
VIN
Main Path Main Path
(PSRMain) ωRC (PSRMain)
ωRC ωP1 Cgg
0 dB ω VREF gmP
ωBW ωP2 BGR
AEA rDS
Total PSRLDO PSRBGR +
ro,EA VOUT
PSR [dB]

COUT
TLoop(s) R1 RL
PSRBGR w/o ωRC
PSRBGR w/i ωRC
R2
 Power-supply rejection: PSR(s) = ΔVOUT/ΔVIN
 Supply-ripple delivery paths from VIN to VOUT
◼ Main path: rDS & gmP of power PMOS
◼ Reference path (VREF): limited PSR of the reference (BGR) voltage circuit

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 64 of 94

Ripple Delivery via rDS: PSR Model (1/6)
VIN
gmEA rEA
◼ Open-loop load impedance:
V
BGR REF
gmp
EA rDS  1 
+ ZLOAD =  + RESR  || (R1 + R2 ) || RL
Cgg VOUT  sCL 

ESR
R1
IL
CL ◼ Closed-loop output impedance:
T0 = AEA  gmpR OUT  β R2
ZLOAD || rDS
ZCL,OUT =
VIN T(s)

rDS ◼ PSR transfer function (via rDS):

VOUT (ZLOAD || ZCL,OUT )
v OUT
PSR(s) = (s) =
ZCL,OUT

rDS + (ZLOAD || ZCL,OUT )

ZLOAD

vIN

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 65 of 94

Ripple Delivery via rDS: PSR Model (2/6)

ω [rad/s]

PSR: VOUT/VIN [dB]

(R1 + R2 ) || RL || rDS
RCL,OUT TDC 1
PSRDC = = 
VIN rDS + RCL,OUT (R + R2 ) || RL || rDS TDC
rDS + 1
TDC
rDS
VOUT 1
PSRDC =
TDC
RCL,OUT

VIN VIN v OUT (ZLOAD || ZCL,OUT )

rEA
gmEA PSR(s) = (s) =
BGR
VREF gmp vIN rDS + (ZLOAD || ZCL,OUT )
EA rDS
rDS
+
Cgg VOUT
VOUT ZLOAD || rDS
ZCL,OUT =
ZCL,OUT
ESR

ZLOAD
R1 T(s)
IL  1 
R2 CL ZLOAD = + RESR  || (R1 + R2 ) || RL
 sCL 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 66 of 94
Ripple Delivery via rDS: PSR Model (3/6)
VIN

VIN ωP ωUGF
rDS
VOUT O X ω [rad/s]

PSR: VOUT/VIN [dB]

(R1+R2)||RL
rDS
VOUT
ZCL,OUT

1
PSR 
T(s)
1
PSRDC =
TDC
Assumed that the dominant pole (ωP) ≈ 1/(rEA·Cgg)

VIN VIN v OUT (ZLOAD || ZCL,OUT )

rEA
gmEA PSR(s) = (s) =
BGR
VREF gmp vIN rDS + (ZLOAD || ZCL,OUT )
EA rDS
rDS
+
Cgg VOUT
VOUT ZLOAD || rDS
ZCL,OUT =
ZCL,OUT
ESR

ZLOAD
R1 T(s)
IL  1 
R2 CL ZLOAD = + RESR  || (R1 + R2 ) || RL
 sCL 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 67 of 94
Ripple Delivery via rDS: PSR Model (4/6)
VIN
ωP ωUGF ωCL ωESR
O X X O ω [rad/s] rDS
VOUT

PSR: VOUT/VIN [dB]

(R1+R2)||RL
CL

1 VIN
PSR  VIN
T(s)
rDS
1 VOUT rDS
PSRDC = VOUT
TDC CL
RESR
RESR

VIN VIN v OUT (ZLOAD || ZCL,OUT )

rEA
gmEA PSR(s) = (s) =
BGR
VREF gmp vIN rDS + (ZLOAD || ZCL,OUT )
EA rDS
rDS
+
Cgg VOUT
VOUT ZLOAD || rDS
ZCL,OUT =
ZCL,OUT
ESR

ZLOAD
R1 T(s)
IL  1 
R2 CL ZLOAD = + RESR  || (R1 + R2 ) || RL
 sCL 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 68 of 94
Ripple Delivery via rDS: PSR Model (5/6)
VIN VIN
VIN ωP ωUGF ωCL ωESR
rDS rDS
VOUT O X X O ω [rad/s]
VOUT

PSR: VOUT/VIN [dB]

(R1+R2)||RL
rDS

(R1+R2)||RL
VOUT CL
ZCL,OUT

VIN 1 VIN
PSR  VIN
T(s)
rDS rDS
1 VOUT rDS
VOUT PSRDC = VOUT
TDC CL
RCL,OUT RESR
RESR

VIN VIN v OUT (ZLOAD || ZCL,OUT )

rEA
gmEA PSR(s) = (s) =
BGR
VREF gmp vIN rDS + (ZLOAD || ZCL,OUT )
EA rDS
rDS
+
Cgg VOUT
VOUT ZLOAD || rDS
ZCL,OUT =
ZCL,OUT
ESR

ZLOAD
R1 T(s)
IL  1 
R2 CL ZLOAD = + RESR  || (R1 + R2 ) || RL
 sCL 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 69 of 94
Ripple Delivery via rDS: PSR Model (6/6)
ωP ωUGF ωCL ωESR
O X X O ω [rad/s]

PSR: VOUT/VIN [dB]

1
PSR 
T(s)
1
PSRDC = ◼ If ωCL (by CL) = dominant-pole
TDC
(ωP = 2nd pole) ➔ More desirable ☺

VIN VIN v OUT (ZLOAD || ZCL,OUT )

rEA
gmEA PSR(s) = (s) =
BGR
VREF gmp vIN rDS + (ZLOAD || ZCL,OUT )
EA rDS
rDS
+
Cgg VOUT
VOUT ZLOAD || rDS
ZCL,OUT =
ZCL,OUT
ESR

ZLOAD
R1 T(s)
IL  1 
R2 CL ZLOAD = + RESR  || (R1 + R2 ) || RL
 sCL 
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 70 of 94
Ripple Delivery via gmP: Ripple Feedforward (1/2)
 Kim & Kim, VLSI’19 & TPEL’20
 Main PSR
w/o Ripple VIN ΔVRipple
Feedforward Main
ΔVRipple PSR
ωP1
0 dB ω BGR
VREF gmP Δvgs,P 0
ωBW
❷ AEA + X rDS
PSR (VOUT/VIN) [dB]

+
Main PSR EA
ωP1 VOUT
w/ Ripple

RESR
☺ Feedforward TLoop R1 RL
❶
R2 COUT
Lower is Better
𝟏 𝟏 𝑹𝑳
𝑷𝑺𝑹𝑳𝒐𝒘 = 𝑷𝑺𝑹𝑯𝒊𝒈𝒉 = 𝒈𝒎𝑷 𝒓𝑫𝑺 ||𝑹𝑳
𝑹𝟐 𝑻𝑳𝒐𝒐𝒑,𝑫𝑪 𝒓𝑫𝑺 + 𝑹𝑳
𝑹𝟏 + 𝑹𝟐 ❶
𝑨𝑬𝑨 ∙ ❷
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 71 of 94
 Ripple Delivery via gmP: Ripple Feedforward (2/2)
 Kim & Kim, VLSI’19 & TPEL’20
VRipple VRipple
VIN
RS VIN
M8 FF-path2 Power M8 Power
(+) PMOS PMOS
VBP MP Δvgs,M8 X
CS 0 MP
VBI Cgg V VBI Cgg V
OUT
M6 M6 OUT

M7 M7
Low-Z by
feedback

 Proposed ripple-feedforward buffer  Conventional buffer

◼ VRipple is absorbed into low-Z via CS ◼ No feedforward by Δvgs,M8 ≈ 0

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 72 of 94

 Ripple Delivery via VREF: Recursive LDO (1/3)
 Kim & Kim, VLSI’19 & TPEL’20

VIN VIN Power w/ ripple VIN Clean

VOUT
VREF Power
LDO
BGR LDO LDO BGR LDO BGR
BGR VREF Out
VOUT Out VOUT VREF Clean Ref
Conventional Architecture VREF Noisy Ref BGR-recursion Recursion

Main PSR Main PSR

ωP1 ωP1
0 dB ω 0 dB ω
ωBW ωBW
Total PSR Total PSR

PSR [dB]
PSR [dB]


☺
Lower is Better Lower is Better
Total PSR of LDO ≈ Worst(Main-PSR, BGR-PSR) Total PSR of LDO ≈ Main-PSR
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 73 of 94
Ripple Delivery via VREF: Recursive LDO (2/3)
 Kim & Kim, VLSI’19 & TPEL’20

Pos. TPFB(s)
VDD,BGR RP + re ,Q 1 1 + sCp ,BGR rds
PSRBGR =
Cp,BGR VIN rds + RP + re ,Q 1 1 + s ( Cp ,BGR + CREF ) rds || ( RP + re ,Q 1 ) 
 
IPTAT

rds
VREF
AEA R2 1 + sCF R1
RP gmP β (s ) =
+ VOUT R1 + R2 1 + sCF ( R1 || R2 )
Q1 CREF
BGR Neg. TLoop(s) R1 CF  PSRBGR (s ) 
Ttot (s )  TLoop (s ) + TPFB (s ) = TLoop (s ) 1 − 
R2  β ( s ) 

 Design Consideration (1) in recursive LDO: stability

◼ TLoop(s) = main LDO regulation loop, TPFB(s) = BGR-recursive loop
◼ For stability, TPFB(s) < TLoop(s)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 74 of 94

Ripple Delivery via VREF: Recursive LDO (3/3)
 Kim & Kim, VLSI’19 & TPEL’20
VIN
BGR VDD,BGR VIN
LDO

Ref
VOUT
EN=1 No CMP
BGR-cascaded ? =0
Yes
CMP
BGR-Replica BGR-Output
ON (VRP) < Soft ON (VREF)
VRP = 0.8V Yes VREF = 0→1.2V

VIN VDD,BGR VOUT(LDO) Anti

dead
No lock
BGR LDO
Ref

VOUT EN=0 No VOUT

? =0 ? Yes
BGR-recursion Yes

 Design Consideration (2) in recursive LDO: startup & deadlock

◼ As a result of VOUT fault, the recursive LDO may fall in a deadlock
◼ When fault is detected, the recursive-loop is unlocked & temporarily VIN-supplied

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 75 of 94

Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 76 of 94

Triode LDO vs. Saturation (CS) LDO
 Triode LDO  Saturation LDO
1% of VOUT 10% of VOUT
+ RIN – Variable CS
+ –
+ +
EA RF1 EA RF1
VIN VOUT RL CL VIN VOUT RL CL
+ RF2 + RF2
VREF VREF

◼ Pass element works in triode region ◼ Pass element works in saturation region
◼ Small VDO (high η) ☺ ◼ High VDO (lower η) 
◼ Low regulation due to low loop-gain ◼ Good regulation performance due to
(T)  high loop-gain (T) ☺
◼ Bad PSR due to small RDS  ◼ Good PSR owing to large RDS ☺
◼ Normally not preferred ◼ Adopted in most LDOs

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 77 of 94

 Low PSR of Triode LDO
VH,M (15.2V) Small
Dropout Condition: RPASS >> RL
vIN (From SCC)
VREF,P MP RO = RPASS / T
- +
Av Buffer VDO T = AV x gm,P x RPASS RPASS
+ RPASS - (0.2V)
vOUT RPASS
=

VOUT Av
VOUT (15V) RO
+
inimized RL
VDO T
CL
EROC VBOOST (16V) IL
=R +RRO = T1
Low
PSR O PASS

 Extremely excellent efficiency ☺: VDO = 0.2V [≈ 1.3% of VOUT (15V)]

 Low PSR due to small RPASS (= RDS of MP) 
◼ MP (power PMOS) working in triode region has a lower RDS
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 78 of 94
Voltage-Current-Hybrid (VIH) LDO (1/6)
 Ko & Kim, ISSCC’21 & JSSC’23
Voltage Regulation (TV) VH,A (19.2V) Large Dropout
VREF,P (VDO + VBAT)
- MV x
(+15V) Av Buffer Large Pass Current (IV)
+ =
IV High Power Loss
Aux. Boost

+
VBAT Low
+ - (4V) Efficiency
V
- BAT VOUT
VH,M (15.2V) +
V DO
VOUT + VDO + VBAT
VOUT -
(0.2V)
=

VOUT (15V)
+ IL (load)
Minimized CL = IV
VDO
EROC VBOOST (16V)
◼ VIN (VH,A = 4V + VOUT) is boosted by charge-pump to ensure a sufficient VDO
◼ Significant power loss  (= large VDO x pass current IV)

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 79 of 94

Voltage-Current-Hybrid (VIH) LDO (2/6)
 Ko & Kim, ISSCC’21 & JSSC’23
Voltage Regulation (TV) VH,A Large Dropout
VREF,P (VDO + VBAT)
- MV x
(+15V) Av Buffer Small Pass Current (IV)
+ =
IV Low Power Loss
Aux. Boost

Current Mirroring
β Small Dropout (VDO)
+ x
V Minimized
- BAT Dropout Large Pass Current (IC)
VH,M + =
VDO Low Power Loss
VOUT -
MC
IL High
CL = IC + IV Efficiency
IC
VOUT
VOUT + VDO
◼ Proposed VIH LDO: power current (IC) = β·IV via power (triode) PMOS ☺
◼ TV-loop regulates the voltage VOUT, while handling smaller IV (≈ ILoad/β)
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 80 of 94
Voltage-Current-Hybrid (VIH) LDO (3/6)
 Ko & Kim, ISSCC’21 & JSSC’23
Small Sign Analysis
VH,A vH,M
VREF,P vG -gm,C
- MV
(+15V) Av Buffer Rds,V ro,C Rds,C
+
Aux. Boost
IV TC
+ 1/β
- RPASS
Current Regulation (TC) vOUT
+ Av
VBAT 1/β
- Rds,V RL
VH,M
Rds,C
VOUT Current Loop (TC)
MC TC = 1/β x gm,C x ro,C
(Main Pass TR.) IL
VG CL IC RPASS-Boosting
ro,C
RPASS =
(1 + TC) x Rds,C
◼ PMOS’s RDS is small because of working in triode region, BUT
◼ RPASS is highly boosted by current-loop gain (TC): RDS → (1+ TC)RDS
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 81 of 94
Voltage-Current-Hybrid (VIH) LDO (4/6)
 Ko & Kim, ISSCC’21 & JSSC’23
Small Sign Analysis
Voltage Regulation (TV) VH,A vH,M vH,M
gm-boosting vG -gm,C
VREF,P MV β x gm,V
-
(+15V) Av Buffer Rds,V β x is ro,C Rds,C
+
IV
is
Aux. Boost
+ 1/β
TTOTAL -
vOUT
+ Av RO
VBAT 1/β
- Rds,V RL
VH,M TV
Rds,C
VOUT Voltage Loop (TV)
MC TV = AV x gm,V x RL
(Main Pass TR.) IL
VG CL Gm-Boosting
ro,C
RO =
RL / (1 + β x TV)

◼ RO is further reduced owing to GM-boosting effect (β): TV → β·TV

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 82 of 94

Voltage-Current-Hybrid (VIH) LDO (5/6)
 Ko & Kim, ISSCC’21 & JSSC’23
Small Sign Analysis
Voltage Regulation (TV) VH,A vH,M vH,M
gm-boosting vG -gm,C
VREF,P MV β x gm,V
-
(+15V) Av Buffer Rds,V β x is ro,C Rds,C
+
TC
is
Aux. Boost
+ 1/β
TTOTAL - RPASS
Current Regulation (TC) vOUT
+ Av RO
VBAT 1/β
- Rds,V RL
VH,M TV
Rds,C
VOUT Voltage Loop (TV) Current Loop (TC)
MC TV = AV x gm,V x RL TC = 1/β x gm,C x ro,C
(Main Pass TR.) IL High
VG CL Gm-Boosting RPASS-Boosting
ro,C PSR
RO = RO RPASS =
RL / (1 + β x TV) R + R (1 + TC) x Rds,C
O PASS

◼ Small RO (by TV-loop) & Boosted RPASS (by TC-loop) ➔ high PSR even low VDO ☺

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 83 of 94

Voltage-Current-Hybrid (VIH) LDO (6/6)
 Ko & Kim, ISSCC’21 & JSSC’23
Load-Current-Reused (LCR)
Voltage Regulation VH,A
VREF,P MV
-
(+15V) Av Buffer Rds,V
+ Using VH,A-VOUT
IBIAS + > VBAT Supply Rail
Aux. Boost

VBAT
-
Load-Current-Reused (LCR)
+ 1/β Voltage Regulation
VBAT
- Load-Current Low-Noise
VH,M Reused IBIAS 5V CMOS
Rds,C +
VOUT VDO
-
MC
(Main Pass TR.) IL Lower Noise
VG CL @ Given Power & Size
ro,C

◼ Bias current (IBIAS) consumed in TV-loop is re-used as a part of ILoad

◼ Thus, high bias current (IBIAS) can contribute on low noise of VOUT ☺
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 84 of 94
Implementation of VIH LDO
β (current gain) = 200 A/A  Ko & Kim, ISSCC’21 & JSSC’23
VIN + VBAT (= 4V) VH,A
LDO input (VIN = 15.2V) VM
5V CMOS
CC1
Mp1 VREF - x1 MVS 40V
MGU IGU IBV MCS AV MV LDMOS
MC Buffer
VG +
ICS IC IVS IV VOUT (= 15V)
Voltage regulation stage
- Mp6 Mp7 IBAL
A2 Mp2 VBAT RZ
IL
IGD +
Mp3 IBB
IV : IGD = 30 : 1 (N : 1) Mp4 Mp5
MGD CL
Mn1 MBAL
IC : IGU = 6000 : 1 (Nxβ : 1) In6 IL,SEN
Mn2 Mn3 Mn4 Mn5 Mn8 Mn9 CC2 RBAL
Mn6 Mn7

MC-gate drive IC-sensing stage Low-voltage domain current-mirroring stage IV-sensing stage Balancing load Output

MC : MCS 300 : 1 Mn2 : Mn3 2:1 Mp3 : Mp4 : Mp5 10 : 1 : 1 MV : MVS 30 : 1

Mn5 : Mn6 1:1 Mn5 : Mn6 1 : 10 Mn5 : Mn7 1:5 Mn9 : Mn8 : MGD 1:1:1
IC : IGU 6000 : 1 IC : In6 600 : 1 IC : IL,SEN 1200 : 1 IV : IGD (= N : 1) 30 : 1

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 85 of 94

Frequency & Stability of VIH LDO
 Ko & Kim, ISSCC’21 & JSSC’23
dB TTotal(s)
Heavy IL
Light IL
TV(s)

TC(s) ro,C
TC

vG
rad/s CC1 iC = β(s)iV
Pole-Zero Location IL

rad/s iV

βωBW,C
ωp1,V
ωBW,C
ωz,V
ωp2,V
Av x1 vOUT
ro,ea RL RZ
Cbuf
Notation Pole/Zero Frequency [rad/s] CL
ωp1,V Pole 1/(RL·CL) TV
ωBW,C Pole gm,C/(N·β·CC1)
ωp2,V Pole 1/(ro,ea·Cbuf) iC T (s) 1
ωz,V Zero 1/(RZ·CL) β (s) = = β C  β
β·ωBW,C Zero gm,C/(N·CC1) iV 1 + TC ( s ) 1 + s ωBW,C

TTotal ( s ) = 1 + β ( s )   TV ( s )
◼ Overall TTotal(s) has 3 poles and 2 zeros
◼ VIH LDO can cover a wide load range
(1 + s ω ) 1 + s ( β  ω )
z,V BW,C
 β  AV  g m,V  RL 
(1 + s ω ) (1 + s ω ) (1 + s ω )
p1,V BW,C p2,V

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 86 of 94

Effects of VIH LDO
fSW @ IL = 1 mA fSW @ IL = 20 mA
 Ko & Kim, ISSCC’21 & JSSC’23 1.E-2
IL = 20 mA
1.E-3 IL = 1 mA
VM,P

Noise [V/sqrt(Hz)]
1.E-4
1.E-5
VM,P (100 mV/div) 1.E-6
VOUT,P
1.E-7
160 mV 1.E-8 PSR = -75 dB
VOUT,P (50 mV/div) @ 30 kHz
100 1k 10k 100k 1M
Frequency [Hz]
VOUT,N (50 mV/div)
◼ -75dB PSR @ 30kHz & 28.7μVRMS noise
160 mV
95 Peak Efficiency

End-to-End Efficiency [%]

VM,N (100 mV/div) 90.5%
10μs 90
VBAT = 3.5 V
85
◼ VIH LDO effectively rejects 80
VBAT = 4 V

the switching ripple 75

VBAT = 4V
(w/o post-regulator)
VBAT = 4.5 V
70
200 400 600
Output Power [mW]
◼ Efficiency loss is only 1.3%
Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 87 of 94
 Summary of VIH (triode) LDO  Ko & Kim, ISSCC’21 & JSSC’23
VH,A
VREF
- MV  Dedicated separate two loops
(15V) Av +
+ ◼ TV (voltage) regulates VOUT by handling low IV
+ IBIAS IV
Aux.
CP VBAT
-
VBAT ◼ TC (current) supplies IC (= β·IV) via ultra-low VDO
VBAT
x1/β -

VM +
 High PSR even at ultra-low VDO
VOUT VDO
IGU
- ◼ RPASS is boosted: RDS → (1+ TC)RDS
MC
(Main Pass TR.) IL ◼ Gm-boosting (β) effect further reduces RO
VG CL IC
ro,C
IGD
 Fabricated results
◼ Power efficiency = 98.7%
◼ PSR = -75dB @ 30kHz

0.34mm2 in 0.18-μm BCD

◼ VOUT noise = 28.7μVRMS integrated in 0.1 – 500kHz
VIN = 15.2V, VOUT = 15V

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 88 of 94

Contents

 Basics of LDO Regulator

 Key Performance Metrics & LDO Configurations

 Frequency Response & Stability

 Fast Transient-Response LDO Designs

 Power Supply Rejection (PSR)

 Energy-Efficient Ultra-Low-Dropout (Triode) LDO

 Conclusion

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 89 of 94

Conclusion
 LDO performs DC-DC step-down conversion via a resistive power transfer media
◼ Error amplifier compares VOUT with VREF and controls the gate volt. of pass transistor
◼ Features: no ripple (clean VOUT), high PSR, small footprint (no bulky L), low efficiency

 Transient response of LDO is determined by loop bandwidth and slew-rate

◼ Dynamic range of load current that LDO can accommodate affects the loop stability
◼ Good FoM in LDO = bandwidth & slew rate vs. IQ consumption

 Supply-ripple (∆VIN) may leak to VOUT via three paths: 1) rDS, 2) gmP, 3) VREF
◼ Wide loop-BW helps to suppress ∆VIN that is transferred through rDS
◼ Ripple-feedforward to gate can restrain ∆VGS of power PMOS, improving PSR
◼ Recursive (self-biased) LDO design is introduced to be free from PSR of VREF

 Ultra-low-dropout (triode) LDO resolves a major drawback of low efficiency

◼ Voltage-current-hybrid (VIH) design is a good option for both high eff. & high PSR

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 90 of 94

 Thank you!

Hyun-Sik Kim (KAIST) 2023 최신 집적회로설계 워크샵: LDO Regulators 91 of 94

References (1/2)
 H.-S. Kim, “Exploring Ways to Minimize Dropout Voltage for Energy-Efficient Low-Dropout Regulators: Viable
approaches that preserve performance”, IEEE Solid-State Circuits Magazine (SSC-M), Spring 2023, pp. 59-68.
 D.-K. Kim et al., “A 300mA BGR-recursive low-dropout regulator achieving 102-to-80dB PSR at frequencies
from 100Hz to 0.1MHz with current efficiency of 99.98%”, IEEE Symp. VLSI Circuits, 2019. Expanded version in
IEEE Trans. Power Electron. (TPEL), Dec. 2020, pp. 13441-13454.
 S.-T. Koh et al., “A 5V Dynamic Class-C Paralleled Single-Stage Amplifier with Near-Zero Dead-Zone Control
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JSSC, Dec. 2021, pp. 3593-3607.
 K.-S. Yoon et al., “Fully-Integrated Digitally-Assisted Low-Dropout Regulator for NAND Flash Memory System,”
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version in IEEE JSSC, May 2023, pp. 1400-1413.
 Texas Instrument, “Application Report: Technical Review of Low Dropout Voltage Regulator Operation and
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 M. Huang et al., “Review of Analog-Assisted-Digital and Digital-Assisted-Analog Low Dropout Regulators”, IEEE
TCAS-II, 2021, pp. 24-29.
 K.-H. Chen, “Power Management Technique for Integrated Circuit Design,” Ed: IEEE Press, 2016.
 G. Rincon-Mora, “Analog IC Design with Low-Dropout Regulators,” Ed: McGraw Hill, 2014.
 Texas Instruments, “LDO noise examined in detail”, 4Q 2012.
 J. Torres et al., “Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison”, IEEE Circuits and
Systems Magazine, May 2014, pp. 6-26.
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References (2/2)
 X. Liu et al., “A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-
Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise
Analyzer,” ISSCC, Feb. 2022.
 V. Gupta et al., "Analysis and design of monolithic, high PSR, linear regulators for SoC applications", IEEE Int.
Syst. Chip Conf., Sept. 2004.
 P. K. Hanumolu, “Low Dropout Regulators”, Tutorial in CICC 2015.
 E. Sanchez-Sinencio, “Low Drop-Out (LDO) Linear Regulators: Design Considerations and Trends for High
Power Supply Rejection (PSR)”, IEEE Santa Clara Valley (SVC), Feb. 2011.
 G. W. den Besten et al., “Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS
technology,” IEEE JSSC, July 1998, pp. 956-962.
 M. El-Nozahi et al., “A 25mA 0.13μm CMOS LDO Regulator with Power-Supply Rejection Better Than −56dB up
to 10MHz Using a Feedforward Ripple-Cancellation Technique”, ISSCC, Feb. 2009. Expanded version in IEEE
JSSC, Mar. 2010, pp. 565-577.
 W.-C. Chen et al., “94% Power-Recycle and Near-Zero Driving-Dead-Zone N-Type Low-Dropout Regulator with
20mV Undershoot at Short-Period Load Transient of Flash Memory in Smart Phone,” ISSCC, Feb. 2018.
 Z. Wang et al., “Review, Survey, and Benchmark of Recent Digital LDO Voltage Regulators,” CICC, April 2022.
 Texas Instruments, “ESR, Stability, and the LDO Regulator”, Feb. 2020.
 B. Xiao et al., “An 80mA Capacitor-Less LDO with 6.5μA Quiescent Current and No Frequency Compensation
Using Adaptive-Deadzone Ring Amplifier”, A-SSCC, Nov. 2019.
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2020.

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