1.
How many total bits are required for a direct - mapped cache with 16
KiB of data and 4 - word blocks, assuming a 32 - bit address? [2]
Cache size = 16 KiB = 16 × 2¹⁰ = 16,384 bytes
Block size = 4 words = 4 × 4 = 16 bytes
Number of blocks = 16,384 ÷ 16 = 1024 blocks
Block offset = log₂(16) = 4 bits
Index bits = log₂(1024) = 10 bits
Tag bits = 32 − (10 + 4) = 18 bits
Each block stores :
Data = 4 × 32 = 128 bits
Plus 1 valid bit and 18 tag bits = 147 bits per block
Thus, total bits = 1024 × 147 = 150,528 bits
2. Find the Average Memory Access Time (AMAT) for a processor with a 1
ns clock cycle time, a miss penalty of 20 clock cycles, a miss rate of 0.05
misses per instruction, and a cache access time (including hit detection)
of 1 clock cycle. Assume that the read and write miss penalties are the
same and ignore other write stalls. [2]
Given :
Clock cycle time = 1 ns
Miss penalty = 20 cycles = 20 ns
Miss rate = 0.05
Cache access (Hit time) = 1 ns
AMAT = Hit Time + (Miss Rate × Miss Penalty)
= 1 ns + (0.05 × 20 ns)
= 1 ns + 1 ns = 2ns
3. How does increasing cache block size impact performance? [2]
Increasing cache block size improves performance by exploiting spatial
locality and reducing miss rate, but it can also increase miss penalty and cause
cache pollution by bringing unnecessary data.
4. How does the inclusion of cache memory improve system performance?
Cache memory improves system performance by reducing average memory
access time, storing frequently accessed data closer to the CPU for faster
retrieval on hits.
5. How do you find the size of the tag field and the total number of bits in
a direct mapped cache? [2]
Tag field size = Address bits − (Index bits + Block offset bits)
Total cache bits =
Number of sets × (Data block size + Tag bits + Valid bit + control bits)
6. What is a tag in a cache memory? What is a “valid bit”? [2]
A tag identifies which main memory block is stored in a cache line. A valid bit
indicates whether the cache line contains valid, usable data matching the
main memory.
7. A CPU accesses cache memory before the main memory. Justify the
reason for this. [2]
The CPU accesses cache first because it is much faster than main memory,
allowing quicker retrieval of frequently used data, thus reducing memory
access time and improving performance.
8. What is the total page table size for 32 - bit virtual address, 4 KiB pages,
and 4 bytes per page table entry? [2]
Number of pages = 2³² ÷ 2¹² = 2²⁰
Total page table size = 2²⁰ × 4 bytes = 4 MiB
9. Describe the role of virtual memory in a computer system. [2]
Virtual memory extends RAM by using disk space to allow programs to use
more memory than physically available, enabling multitasking and memory
protection.
10. Why is cache memory preferred over main memory despite its small
size? [2]
Cache memory is preferred over main memory because its faster access time
allows quicker retrieval of frequently used data, thereby boosting CPU
performance despite its smaller size.
11. What is the difference between SRAM and DRAM? [2]
SRAM uses flip - flops, is faster, costlier, and does not need refreshing.
DRAM uses capacitors, is slower, cheaper, denser, and needs periodic
refreshing.
12. What are the mapping procedures adopted in the organization of a
Cache Memory? [2]
Cache mapping procedures are:
✓ Direct Mapping: Each memory block maps to one specific cache line.
✓ Associative Mapping: Any block can go into any cache line.
✓ Set - Associative Mapping: Block maps to a set, placed in any line
within that set.
13. To design a 512 * 8 RAM chip by using 128 *8 RAM chips what will be
the size of the decoder? [2]
512 ÷ 128 = 4 chips needed
To select 1 out of 4 chips, a 2 – to – 4 decoder is required.
Thus, decoder size = 2 – to – 4.
14.
Consider a direct - mapped cache with a capacity of 32 bytes and a block size
of 8 bytes. Assume that the main memory has 64 blocks. What is the size of
the tag field in bits? [2]
Number of cache blocks = 32 ÷ 8 = 4 blocks
Index bits = log₂(4) = 2 bits
Block offset bits = log₂(8) = 3 bits
Address bits = log₂(64) = 6 bits
Tag field size = 6 − (2 + 3) = 1 bit
15. What is locality of refence? [2]
Locality of reference means the CPU tends to access recently used (temporal
locality) or nearby (spatial locality) memory locations. Cache memory exploits
this principle to improve performance.
16. Consider a direct mapped cache with block size 4 KB. The size of main
memory is 16 GB and there are 10 bits in the tag. Find size of cache
memory and Tag directory size. [2]
Main memory size = 16 GB = 2³⁴ bytes, Block size = 4 KB = 2¹² bytes
34 = 10 (tag) + Index bits + 12 (offset) ⇒ Index bits = 12
Number of cache lines = 2¹² = 4096 lines
Cache size = 4096 × 4 KB = 16 MB
Tag directory size = 4096 × 10 bits = 40960 bits = 5 KB
17. What is the difference between write - through and write - back
methods? [2]
Write - through: Updates both cache and main memory simultaneously on a
write.
Write - back: Updates only cache first; main memory is updated later when
the block is replaced (tracked by a dirty bit).
18. Let us consider a computer with an address space of 8K and a memory
space of 4K. How many pages and blocks can be obtained if we split each
into groups of 1K words? [2]
Address space = 8K words, Page size = 1K ⇒ 8 pages
Memory space = 4K words, Block size = 1K ⇒ 4 blocks
19. What is the difference between FIFO and LRU techniques for page
replacement in case of virtual memory. [2]
FIFO: Replaces the oldest loaded page, without considering usage.
LRU: Replaces the page least recently used, assuming recent pages are likely
needed again. LRU usually performs better but is harder to implement.
20. Give the features of a ROM cell. [2]
Features of a ROM (Read - Only Memory) cell include :
✓ Non - volatile: Retains data without power.
✓ Read - only: Data is fixed during manufacturing.
Simple structure: Uses a transistor or diode to store each bit.