PRELIMINARY TECHNICAL DATA

a 12-Bit, 170 MSPS

3.3V A/D Converter
Preliminary Technical Data AD9430
FEATURES PRODUCT DESCRIPTION
SNR = 65dB @ Fin up to 65MHz at 170Msps The AD9430 is a 12-bit monolithic sampling analog–to–
ENOB of 10.3 @ Fin up to 65MHz at 170 Msps (-1dBFs) digital converter with an on–chip track–and–hold circuit and
SFDR = -80dBc @ Fin up to 65MHz at 170Msps (-1dBFs) is optimized for low cost, low power, small size and ease of
Excellent Linearity: use. The product operates up to 170 Msps conversion rate
- DNL = +/- 1 lsb (typ) and is optimized for outstanding dynamic performance in
- INL = +/- 1.5 lsb (typ) wideband carrier systems.
Two Output Data options
The ADC requires a +3.3V power supply and a differential
- Demultiplexed 3.3V CMOS outputs each at 85 Msps
encode clock for full performance operation. No external
- LVDS at 170Msps
reference or driver components are required for many
700 MHz Full Power Analog Bandwidth
applications. The digital outputs are TTL/CMOS or LVDS
On–chip reference and track/hol d
compatible. Separate output power supply pins support
Power dissipation = 1.25W typical at 170Msps
interfacing with 3.3V CMOS logic.
1.5V Input voltage range
+3.3V Supply Operation An output data format select option of two’s complement or
Output data format option offset binary is supported. In CMOS mode two output buses
Data Sync input and Data Clock output provided support demultiplexed data up to 85 Msps rates. A data sync
Interleaved or parallel data output option (CMOS) input is supported for proper output data port alignment and
Clock Duty Cycle Stabilizer. a data clock output is available for proper output data timing.
Fabricated on an advanced BiCMOS process, the AD9430 is
APPLICATIONS
Wireless and Wired Broadband Communications available in a 100 pin surface mount plastic package (100
- Wideband carrier frequency systems TQFP ePAD) specified over the industrial temperature range
- Cable Reverse Path (–40°C to +85°C).
Communications Test Equipment
Radar and Satellite sub-systems
Power Amplifier Linearization

VREF AGND DrGND DrVDD AV DD

SENSE

Scaleable
AD9430 Reference

LVDS Data(24), OR(2)

AIN+ Outputs
Track & ADC
Hold 12-bit 12
AIN- Pipeline A port Data(12), OR(1)
Core
CMOS
Outputs
B port Data(12), OR(1)
DS+

DS-

ENC+
Clock
Management
ENC-
Select CMOS or LVDS
DCO+

DCO-

S1 S2 S4 S5

AD9430 FUNCTIONAL BLOCK DIAGRAM

REV. PrG 4/01/2002
Information furnished by Analog Devices is believed to be accurate and One Technology Way,[Link] 9106,Norwood,MA 02062-9106,U.S.A.
[Link],no responsibility is assumed by Analog Devices for its use,nor Tel:781/329-4700 [Link]
for any infringements of patents or other rights of third parties that may result from Fax:781/326-8703 © Analog Devices, Inc., 2002
its [Link] license is granted by implication or otherwise under any patent or
patent rights of Analog Devices.
 PRELIMINARY TECHNICAL DATA
AD9430
DC SPECIFICATIONS (AVDD= DrVDD = 3.3V; TMIN = -40°C, TMAX = +85°C, Fin = -0.5dBFS, 1.235V External
reference, LVDS Output Mode)
Test AD9430BSV-170
Parameter Temp Level Min Typ Max Units
RESOLUTION 12 Bits
ACCURACY
No Missing Codes Full I Guaranteed
Offset Error 25°C I tbd mV
Gain Error 25°C I tbd % FS
Differential Nonlinearity (DNL) 25°C I +/- .3 LSB
Integral Nonlinearity (INL) 25°C I +/- .5 LSB
TEMPERATURE DRIFT
Offset Error Full V tbd ppm/°C
Gain Error Full V tbd ppm/°C
POWER SUPPLY REJECTION Full V ± tbd mV/V
REFERENCE OUT (VREF) Full V 1.235 V
ANALOG INPUTS (AIN, AIN )
Input Voltage Range (AIN– AIN )1
Full V ± .768 V
Input Common Mode Voltage
Full V 2.8 V
Input Resistance
Full V 3 kΩ
Input Capacitance
Full V 5 pF
POWER SUPPLY
Supply Voltages
AVDD Full V 3.0 3.3 3.6 V
DrVDD Full V 3.0 3.3 3.6 V
Supply Current
I ANALOG (AVDD= 3.3V) 2 Full V 335 mA
I DIGITAL (DrVDD = 3.3V) 2 Full V 55 mA
POWER CONSUMPTION3 Full V 1.29 W
NOTES
1
Nominal Differential Full Scale = .766 V * 2 = 1.53 Vp-p differential for S5 = 0; Nominal Differential Full Scale = .766 Vp-p d ifferential for S5 = 1 (see Fig. X)
2 IAVDD and IDrVDD are measured with an analog input of 10.3MHz, -0.5dBFs, sine wave, rated Encode rate and in LVDS output mode. See Typical Performance
Characteristics and Applications section for IDrVDD. 3 Power Consumption is measured with a DC input at rated Encode rate in LVDS output mode
DIGITAL SPECIFICATIONS (AVDD= 3.3V, DrVDD = 3.3V; TMIN = -40°°C, TMAX = +85°°C)
Test AD9430BSV-170
Parameter (Conditions) Temp Level Min Typ Max Units
ENCODE AND DATA SYNC
INPUTS (ENC, ENC , DS, DS/ )
Differential Input Voltage 1 Full IV 0.2 V
Encode Common Mode Voltage Full IV 1.5 V

Input Resistance Full IV 5.5 kΩ

Input Capacitance Full IV 4 pF
LOGIC INPUTS ( S1,S2,S4,S5 )
Logic ‘1’ Voltage Full IV 2.0 V
Logic ‘0’ Voltage Full IV .8 V
Input Resistance Full IV 30 kΩ
Input Capacitance Full IV 4 pF
LOGIC OUTPUTS (Demux Mode)
Logic “1” Voltage2 Full IV DrVDD-0.05 V
Logic “0” Voltage2 Full IV 0.05 V
LOGIC OUTPUTS (LVDS Mode)2,3
VOD Differential Output Voltage Full IV 247 454 mV
VOS Output Offset Voltage Full IV 1.125 1.375 V
Output Coding Full IV Two’s Comp or Binary
NOTES 1All AC specifications tested by driving ENCODE and ENCODE differentially | ENCODE - ENCODE | > 200mV
2
Digital Output Logic Levels: DrVDD= 3.3V, CLOAD = 5pF. 3
LVDS Rl=100 ohms, LVDS Output Swing Set Resistor = 3.7K

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 PRELIMINARY TECHNICAL DATA
AD9430
AC SPECIFICATIONS1 (AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ; TMIN = -40°C, TMAX
= +85°C, Internal voltage reference, LVDS Output Mode )
Test AD9430BSV-170
Parameter (Conditions) Temp Level Min Typ Max Units
SNR
Analog Input 10 MHz 25°C I 65 dB
@ -0.5dBFS 65 MHz 25°C I 65 dB
100 MHz 25°C V 65 dB
240 MHz 25°C V 64 dB
SINAD
Analog Input 10 MHz 25°C I 65 dB
@ -0.5dBFS 65 MHz 25°C I 65 dB
100 MHz 25°C V 64.5 dB
240 MHz 25°C V 60 dB
Worst Harmonic (2nd or 3 rd)
Analog Input 10 MHz 25°C I -85 dBc
@ -0.5dBFS 65 MHz 25°C I -80 dBc
100 MHz 25°C V -77 dBc
240 MHz 25°C V -63 dBc
Worst Harmonic (4th or higher)
Analog Input 10 MHz 25°C I -87 dBc
@ -0.5dBFS 65 MHz 25°C I -87 dBc
100 MHz 25°C V -77 dBc
240 MHz 25°C V -63 dBc
Two-tone IMD2
F1, F2 @ -7 dBFS Full V -75 dBc
Analog Input Bandwidth 25°C V 700 MHz
NOTES
1
All AC specifications tested by driving ENCODE and ENCODE differentially.
2 F1 = 31.5 MHz, F2 = 32.5 MHz

SWITCHING SPECIFICATIONS (AVDD= 3.3 V, DrVDD = 3.3V; ENCODE = Maximum Conversion Rate ;
TMIN = -40°C, TMAX = +85°C )
Test AD9430BSV-170
Parameter (Conditions) Temp Level Min Typ Max Units
Maximum Conversion Rate1 Full I 170 MSPS
Minimum Conversion Rate1 Full V 40 MSPS
Encode Pulse Width High (tEH)1 Full V 2 nS
Encode Pulse Width Low (tEL)1 Full V 2 nS
DS Input Setup Time (tSDS) 2 Full IV .5 nS
DS Input Hold Time (tHDS) 2 Full IV 1.5 nS

NOTES
1
All AC specifications tested by driving ENCODE and ENCODE differentially, LVDS Mode.
2 DS inputs used in CMOS Mode only.

REV. PrG 4/01/2002 -3-

 PRELIMINARY TECHNICAL DATA
AD9430
SWITCHING SPECIFICATIONS (cont’d)
Test AD9430BSV-170
Parameter Temp Level Min Typ Max Units
OUTPUT Parameters in Demux Mode
Valid Time (tV) Full IV tbd ns
Propagation Delay (tPD) Full IV 3.8 ns
Rise Time (tR) (20% to 80%) 25°C V 1 ns
Fall Time (tF) (20% to 80%) 25°C V 1 ns
DCO Propagation Delay (tCPD) Full VI 3.8 ns
Data to DCO Skew (tPD – tCPD) Full IV 0 ns
Interleaved Mode (A, B Latency) Full VI 14/14 Cycles
Parallel Mode (A, B Latency) Full VI 14/15 Cycles
OUTPUT Parameters in LVDS Mode
Valid Time (tV) Full IV 2.0 ns
Propagation Delay (tPD) Full I 3.2 4.3 ns
Rise Time (tR) (20% to 80%) 25°C V .5 ns
Fall Time (tF) (20% to 80%) 25°C V .5 ns
DCO Propagation Delay (tCPD) Full VI 1.8 2.7 3.8 ns
Data to DCO Skew (tPD – tCPD) Full IV .5 ns
Pipeline Latency Full VI 14 Cycles
Aperture Delay (tA) 25°C V 1.2 ps
Aperture Uncertainty (Jitter, t J) 25°C V 0.25 ps rms

Measured Preliminary Performance : FFT 65MHz Ain at 170MSPS

-4- 4/01/2002 REV. PrG

 PRELIMINARY TECHNICAL DATA
AD9430
AD9430 Timing Diagram

REV. PrG 4/01/2002 -5-

 PRELIMINARY TECHNICAL DATA
AD9430
ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS
AVDD, DRVDD.. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Test Level
Analog Inputs . . . . . . . . . . .. . .. . . –0.5 V to AVDD + 0.5 V I 100% production tested.
Digital Inputs . . .. . . . . . . . .. . . .. –0.5 V to DRVDD + 0.5 V II 100% production tested at 25C and sample tested at
REFIN Inputs . . . . . . . . . . . . . . . . –0.5 V to AVDD + 0.5 V specified temperatures.
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA III Sample tested only.
Operating Temperature . . . . . . . . . . ... . . . . . –55C to +125C IV Parameter is guaranteed by design and characterization
Storage Temperature . . . . . . . . . . . . . ... . . . . –65C to +150C testing.
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C V Parameter is a typical value only.
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . ..150C VI 100% production tested at 25C; guaranteed by design
θJA2 . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . 25C/W, 32C/W and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
NOTES for military devices.

1 Stresses above those listed under Absolute Maximum Ratings may

cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions outside of those
indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect
device reliability.

2 Typical θJA = 32C/W (heat slug not soldered), Typical θJA =

25C/W (heat slug soldered), for multilayer board in still air.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9430 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality .

ORDERING GUIDE
Model Temperature Range Package Option
AD9430BSV-170 –40°C to +85°C TQFP–100

AD9430/PCB-CMOS +25°C Evaluatio n Board

(CMOS Mode)

Table 1. AD9430 Output Select Coding

S1 S2 S4 S5 Mode
(Data (LVDS/CMOS (Select (Full Scale
Format Output Mode Interleaved or Adjust)
Select) 1 Select ) Parallel Mode) 2
1 X X X 2’s Complement
0 X X X Offset Binary
X 0 1 X Dual Mode CMOS Interleaved
X 0 0 X Dual Mode CMOS Parallel
X 1 X X LVDS Mode
X X X 1 Full Scale -> .766 Vpp differential
1.533 Vpp Single- Ended
X X X 0 Full Scale -> 1.533 Vpp differential
Notes:
1
X = Don’t Care
S1-S5 all have 30K resistive pulldowns on chip
2
In interleaved mode output data on port A is offset from output data changes on port B by ½ output clock cycle.

Interleaved mode Parallel Mode

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 PRELIMINARY TECHNICAL DATA
AD9430
(MSB)

DRGND
DRVDD

D11_C
AGND

AGND
AGND

AGND
AGND

D11_T

D10_T
AVDD
AVDD

AVDD
AVDD

D10_C
AVDD
AGND

AGND

OR_C
OR_T
AGND

D9_C
AVDD
AVDD

D9_T
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
S5 1 75 DRVDD
DNC 2 74 DRGND
S4 3 73 D8_T
AGND 4 72 D8_C
S2 5 71 D7_T
S1 6 70 D7_C
LVDSBIAS
7 69 D6_T
8 68 D6_C
AVDD
9 67 DRGND
AGND
SENSE 10 66 D5_T
11 65 D5_C
VREF AD9430
AGND 12 64 DCO
LVDS PINOUT
AGND 13 TOP VIEW 63 DCO
AVDD 14 (Not to Scale) 62 DRVDD
AVDD 15 61 DRGND
AGND 16 60 D4_T
AGND 17 59 D4_C
AVDD 18 58 D3_T
AVDD 19 57 D3_C
AGND 20 56 D2_T
AIN 21 55 D2_C
AIN 22 54 DRVDD
AGND 23 53 DRGND
AVDD 24 52 D1_T
AGND 25 51 D1_C
DNC 42
DNC 43
DNC 44
DNC 45
DNC 46
DRVDD 47
DRGND 48
D0_C 49
D0_T 50
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
GND

ENC
ENC
AGND

AGND
AGND

AGND

AGND

AGND
AVDD
AVDD
AVDD

AVDD
AVDD

AVDD
AVDD

AD9430 LVDS Mode Pinout

DA11 (MSB)

DRGND
DRVDD
AGND

AGND
AGND
AGND

AGND
AGND

AGND
AGND

AVDD
AVDD
AVDD

OR_A
AVDD
AVDD

AVDD
AVDD

DA10
DA9
DA8
DA7
DA6
DA5
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

S5 1 75 DRVDD
2 74 DRGND
DNC
S4 3 73 DA4
AGND 4 72 DA3
S2 5 71 DA2
S1 6 70 DA1
DNC 7 69 DA0
68 DNC
AVDD 8
67 DRGND
AGND 9
SENSE 10 66 DNC
65 DNC
VREF 11 AD9430
AGND 12 64 DCO
CMOS PINOUT
AGND 13 TOP VIEW 63 DCO
AVDD 14 (Not to Scale) 62 DRVDD
AVDD 15 61 DRGND
AGND 16 60 OR_B
AGND 17 59 DB11 (MSB)
AVDD 18 58 DB10
AVDD 19 57 DB9
AGND 20 56 DB8
AIN 21 55 DB7
AIN 22 54 DRVDD
AGND 23 53 DRGND
AVDD 24 52 DB6
AGND 25 51 DB5
42
43
44
45
DB2 46
DRVDD 47
DRGND 48
DB3 49
DB4 50
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
AGND

AGND
AGND

AGND

AGND

AGND
AVDD
AVDD
AVDD

AVDD

AVDD
AVDD

DB0
DB1
DNC
DNC
ENC
ENC
DS
DS

AD9430 CMOS Dual Mode Pinout

REV. PrG 4/01/2002 -7-

 PRELIMINARY TECHNICAL DATA
AD9430
PIN FUNCTION DESCRIPTIONS (CMOS mode)
CMOS Mode Name Function in CMOS Mode
Pin Number
2,7,42,43,65,66,68 DNC Do not connect
1 S5 Full Scale Adjust pin : ‘1’ sets FS =.766 Vpp differential,
‘0’ sets FS = 1.533 Vpp differential
3 S4 Interlaced or parallel output mode. (only in Dual Port mode
operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.
5 S2 Output Mode select. Low = Dual Port, CMOS; High = LVDS
6 S1 Data format select. Low = Binary, High = Two’s compliment
8,14,15,18,19,24,27,28,29,34, AVDD 3.3V analog supply. (3.0V to 3.6V)
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3 AGND Analog Ground
0,31,35,38,41,86,87,91,92,93,
96,97,100
10 SENSE Control Pin for Reference , Full Scale
11 VREF 1.235 Reference I/O - function dependent on REFSENSE
21 VIN+ Analog input – true.
22 VIN- Analog input – compliment.
32 DS+ Data sync (input) – true. Aligns output channels so that data from
channel A represents a sample that is prior from data in channel B,
taking into account the pipeline delay. (See timing diagram). Tie
LOW if not used.
33 DS- Data sync (input) – compliment. Tie HIGH if not used.
36 ENC+ Clock input – true.
37 ENC- Clock input – compliment.
44 DB0 B Port Output Data Bit (LSB)
45 DB1 B Port Output Data Bit
46 DB2 B Port Output Data Bit
49 DB3 B Port Output Data Bit
50 DB4 B Port Output Data Bit
51 DB5 B Port Output Data Bit
52 DB6 B Port Output Data Bit
55 DB7 B Port Output Data Bit
56 DB8 B Port Output Data Bit
57 DB9 B Port Output Data Bit
58 DB10 B Port Output Data Bit
59 DB11 B Port Output Data Bit (MSB)
60 OR_B B Port Overrange
48,53,61,67,74,82 DrGND Digital ground.
47,54,62,75,83 DrVDD 3.3V digital output supply. (3.0V to 3.6V)
63 DCO- Data Clock output – compliment.
64 DCO+ Data Clock output – true.
69 DA0 A port Output Data Bit (LSB)
70 DA1 A port Output Data Bit
71 DA2 A port Output Data Bit
72 DA3 A port Output Data Bit
73 DA4 A port Output Data Bit
76 DA5 A port Output Data Bit
77 DA6 A port Output Data Bit
78 DA7 A port Output Data Bit
79 DA8 A port Output Data Bit
80 DA9 A port Output Data Bit
81 DA10 A port Output Data Bit
84 DA11 A port Output Data Bit (MSB)
85 OR_A A port Overrange

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 PRELIMINARY TECHNICAL DATA
AD9430
PIN FUNCTION DESCRIPTIONS (LVDS mode )
LVDS Mode Name Function in LVDS Mode
Pin Number
2,42,43,44,45,46 DNC Do not connect
1 S5 Full Scale Adjust pin : ‘1’ sets FS =.766 Vpp differential,
‘0’ sets FS = 1.533 Vpp differential
3 S4 Interlaced or parallel output mode. (only in Dual Port mode
operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channel A at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.
5 S2 Output Mode select. Low = Dual Port, CMOS; High = LVDS
6 S1 Data format select. Low = Binary, High = Two’s compliment
7 LVDSBIAS Sets LVDS Output Current = 3.5mA
(Place 3.7K RSET resistor from LVDSBIAS to ground)
8,14,15,18,19,24,27,28,29,34, AVDD 3.3V analog supply. (3.0V to 3.6V)
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3 AGND Analog Ground
0,31,35,38,41,86,87,91,92,93,
96,97,100
10 SENSE Control Pin for Reference , Full Scale
11 VREF 1.235 Reference I/O - function dependent on REFSENSE
21 VIN+ Analog input – true.
22 VIN- Analog input – compliment.
32 DS+ Data sync (input) – Not used in LVDS [Link] LOW .
33 DS- Data sync (input) – compliment. Not used in LVDS [Link] HIGH.
36 ENC+ Clock input – true. (LVPECL levels)
37 ENC- Clock input – compliment. (LVPECL levels)
47,54,62,75,83 DrVDD 3.3V digital output supply.

48,53,61,67,74,82 DrGND Digital ground.

49 D0_C D0 complement output bit (LSB) (LVDS Levels)
50 D0_T D0 true output bit (LSB) (LVDS Levels)
51 D1_C D1 complement output bit (LVDS Levels)
52 D1_T D1 true output bit (LVDS Levels)
55 D2_C D2 complement output bit (LVDS Levels)
56 D2_T D2 true output bit (LVDS Levels)
57 D3_C D3 complement output bit (LVDS Levels)
58 D3_T D3 true output bit (LVDS Levels)
59 D4_C D4 complement output bit (LVDS Levels)
60 D4_T D4 true output bit (LVDS Levels)
63 DCO- Data Clock output – compliment. (LVDS Levels)
64 DCO+ Data Clock output – true. (LVDS Levels)
65 D5_C D5 complement output bit (LVDS Levels)
66 D5_T D5 true output bit (LVDS Levels)
68 D6_C D6 complement output bit (LVDS Levels)
69 D6_T D6 true output bit (LVDS Levels)
70 D7_C D7 complement output bit (LVDS Levels)
71 D7_T D7 true output bit (LVDS Levels)
72 D8_C D8 complement output bit (LVDS Levels)
73 D8_T D8 true output bit (LVDS Levels)
76 D9_C D9 complement output bit (LVDS Levels)
77 D9_T D9 true output bit (LVDS Levels)
78 D10_C D10 complement output bit (LVDS Levels)
79 D10_T D10 true output bit (LVDS Levels)
80 D11_C D11 complement output bit (LVDS Levels) MSB
81 D11_T D11 true output bit (LVDS Levels) MSB
84 OR_C Overrange complement output bit (LVDS Levels)
85 OR_T Overrange true output bit (LVDS Levels)

REV. PrG 4/01/2002 -9-

 PRELIMINARY TECHNICAL DATA
AD9430
TERMINOLOGY

Analog Bandwidth
The analog input frequency at which the spectral power of Full-Scale Input Power
the fundamental frequency (as determined by the FFT Expressed in dBm. Computed using the following equation:
analysis) is reduced by 3 dB. 2
 VFullscale 
 rms 
Aperture Delay  Z Input 
The delay between the 50% point of the rising edge of the PowerFullscale = 10 log 
ENCODE command and the instant at which the analog  .001 
input is sampled.  
 
Aperture Uncertainty (Jitter) Gain Error
The sample-to-sample variation in aperture delay. Gain error is the difference between the measured and ideal
full scale input voltage range of the ADC.
Crosstalk
Coupling onto one channel being driven by a low level (–40 Harmonic Distortion, Second
dBFS) signal when the adjacent interfering channel is driven The ratio of the rms signal amplitude to the rms value of the
by a full-scale signal. second harmonic component, repo rted in dBc.

Differential Analog Input Resistance, Differential Analog Harmonic Distortion, Third

Input Capacitance and Differential Analog Input The ratio of the rms signal amplitude to the rms value of the
Impedance third harmonic component, reported in dBc.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the Integral Nonlinearity
capacitance and differential input impedances are measured The deviation of the transfer function from a reference line
with a network analyzer. measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to Minimum Conversion Rate
the converter to generate a full-scale response. Peak The encode rate at which the SNR of the lowest analog
differential voltage is computed by observing the voltage on signal frequency drops by no more than 3 dB below the
a single pin and subtracting the voltage from the other pin, guaranteed limit.
which is 180 degrees out of phase. Peak-to-peak differential
is computed by rotating the inputs phase 180 degrees and Maximum Conversion Rate
again taking the peak measurement. The difference is then The encode rate at which parametric testing is performed.
computed between both peak measurements.
Output Propagation Delay
Differential Nonlinearity The delay between a differential crossing of ENCODE and
The deviation of any code width from an ideal 1 LSB step. ENCODE and the time when all output data bits are within
valid logic levels.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the Noise (for Any Range within the ADC)
measured SNR based on the equation:  FSdBm − SNRdBc − SignaldBFS 
 
SNR MEASURED− 1.76 dB V noise = Z * .001 * 10  10 
ENOB =
6.02 Where Z is the input impedance, FS is the full scale of the
device for the frequency in question, SNR is the value for the
ENCODE Pulsewidth / Duty Cycle particular input level, and Signal is the signal level within
Pulsewidth high is the minimum amount of time that the the ADC reported in dB below full scale. This value includes
ENCODE pulse should be left in Logic 1 state to achieve both thermal and quantization noise.
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing Power Supply Rejection Ratio
implications of changing tENCH in text. At a given clock rate, The ratio of a change in input offset voltage to a change in
these specifica-tions define an acceptable ENCODE duty power supply voltage.
cycle.
Signal -to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full
scale) to the rms value of the sum of all other spectral
components, including harmonics but excluding dc.

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 PRELIMINARY TECHNICAL DATA
AD9430
Signal -to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. May be reported
in dBc (i.e., degrades as signal level is lowered), or dBFS Figure X Analog Inputs
(always related back to converter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product;
reported in dBc.

Two-Tone SFDR
The ratio of the rms value of either input tone to the rms
value of the peak spurious component. The peak spurious
component may or may not be an IMD product. May be Figure X S1-S5 Inputs
reported in dBc (i.e., degrades as signal level is lowered), or
in dBFS (always related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.

Transient Response Time

Transient response is defined as the time it takes for the
ADC to reacquire the analog input after a transient from
10% above negative full scale to 10% below positive full
scale.

Out-of-Range Recovery Time

Out of range recovery time is the time it takes for the ADC Figure X VREF, SENSE I/O
to reacquire the analog input after a transient from 10%
above positive full scale to 10% above negative full scale, or
from 10% below negative full scale to 10% below positive
full scale.

EQUIVALENT CIRCUITS

Figure X Data Outputs (CMOS Mode)

Figure X Encode and DS Inputs

Figure X Data Outputs (LVDS Mode)

REV. PrG 4/01/2002 -11-

 PRELIMINARY TECHNICAL DATA
AD9430
APPLICATION NOTES
THEORY OF OPERATION differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs
The AD9430 architecture is optimized for high speed and are self-biased by an on-chip resistor divider to a nominal
ease of use. The analog inputs drive an integrated high 2.8 V. (See Equivalent Circuits section TBD.)
bandwidth track-and-hold circuit that samples the signal Special care was taken in the design of the Analog Input
prior to quantization by the 12-bit core. For ease of use the section of the AD9430 to prevent damage and corruption of
part includes an onboard reference and input logic that data when the input is overdriven. The nominal input range
accepts TTL, CMOS, or LVPECL levels. The digital outputs is 1.5 V diff p-p. The nominal differential input range is 768
logic levels are user selectable as standard 3V CMOS or mV p-p × 2.
LVDS (ANSI-644 compatible) via pin S2.

USING THE AD9430

ENCODE Input
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A
track/hold circuit is essentially a mixer, and any noise,
distortion, or timing jitter on the clock will be combined
with the desired signal at the A/D output. For that reason,
considerable care has been taken in the design of the
ENCODE input of the AD9430, and the user is advised to
give commensurate thought to the clock source.

The AD9430 has an internal clock duty cycle stabilization

circuit that locks to the rising edge of ENCODE (falling
edge of ENCODE if driven differentially), and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in Differential Analog Input Range
the rising edge of the input is still of paramount concern, and
is not reduced by the internal stabilization circuit. This
circuit is always on, and cannot be disabled by the user.
The ENCODE and ENCODE inputs are internally biased to
1.5V (nominal), and support either differential or single –
ended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained
using an MC10EL16 in the circuit to drive the
encode inputs , as illustrated in figure below.

Single Ended Analog Input Range

Driving Encode with EL16

Analog Input
The analog input to the AD9430 is a differential buffer. For
____
best dynamic performance, impedances at AIN and AIN
should match. The analog input has been optimized to
provide superior wideband performance and requires that the
analog inputs be driven differentially. SNR and SINAD
performance will degrade significantly (~6dB) if the analog
input is driven with a single-ended signal. A wideband
transformer such as Minicircuits ADT1 -1WT can be used to
provide the

-12- 4/01/2002 REV. PrG

 PRELIMINARY TECHNICAL DATA
AD9430
Digital Outputs Voltage Reference
The off chip drivers on the chip can be configured by the A stable and accurate 1.25 V voltage reference is built into
user to provide CMOS or LVDS compatible output levels the AD9430 (VREF). The analog input Full Scale Range is
via pin S2. linearly proportional to the voltage at VREF. VREF (and in
turn input full scale ) can be varied by adding an external
The CMOS digital outputs (S2=0) are TTL/CMOS-
resistor network at VREF, SENSE and GROUND. (See
compatible for lower power consumption. The outputs are
figure X ) . No appreciable degradation in performance
biased from a separate supply (VDD), allowing easy
occurs when VREF is adjusted ±5%. Note that an external
interface to external logic. The outputs are CMOS devices
reference can be used by connecting the SENSE pin to VDD
which will swing from ground to VDD (with no dc load). It
(disabling internal reference) and driving VREF with the
is recommended to minimize the capacitive load the ADC
external reference source. A .1uF capacitor to ground is
drives by keeping the output traces short (<1 inch, for a total
recommended at VREF pin in internal and external reference
CLOAD < 5 pF). When operating in cmos mode it is also
applications.
recommended to place low value (220 ohm) series damping
resistors on the data lines to reduce switching transient
effects on performance.

LVDS outputs are available when S2=VDD and a 3.7K

RSET resistor is placed at pin 7 ( LVDSBIAS) to ground .
This resistor sets the output current at each output equal to a
nominal 3.5mA ( 10* IRSET ) . A 100 ohm differential
termination resistor placed at the lvds receiver inputs results
in a nominal 350mV voltage swing at the receiver. Note that
when operating in LVDS mode the output supply must be at
a dc potential greater than or equal to the analog supply level
(AVDD). This can be accomplished simply by biasing the
two supplies from the same power plane or by tying the two
supplies on the pcb through an inductor. When operating in
CMOS mode this is not required and separate supplies are
recommended. Simplified Voltage Reference Equivalent Circuit

Clock Outputs (DCO+, DCO-)

The input ENCODE is divided by two (in CMOS mode) and
available off-chip at DCO+ and DCO-. These clocks can
facilitate latching off-chip, providing a low skew clocking
solution (see timing diagram). The on-chip clock buffers
should not drive more than 5 pF of capacitance to limit
switching transient effects on performance.
Note that the Outputs clocks are CMOS levels when CMOS
mode is selected(S2=0) and are LVDS levels when in LVDS
mode(S2=VDD). (Requiring a 100ohm differential
termination at receiver in LVDS mode). The output clock in
LVDS mode switches at the encode rate.

REV. PrG 4/01/2002 -13-

 PRELIMINARY TECHNICAL DATA
AD9430
AD9430 EVALUATION BOARD > 0.5 V p-p. Power to the EL16 is set at jumper E47. E47–E45
The AD9430 evaluation board offers an easy way to test the powers the buffer from AVDD, E47–E46 powers the buffer from
AD9430. It requires a clock source, an analog input signal, and VCLK/V_XTAL.
a 3.3 V power supply. The clock source is buffered on the board Voltage Reference
to provide the clocks for the ADC, an on-board DAC, latches, The AD9430 has an internal 1.23 V voltage reference. The
and a data ready signal. The digital outputs and output clocks ADC uses the internal reference as the default when jumpers
are available at two 40-pin connectors, P3 and P4. The board E24–E27 and E25–E26 are left open. The full scale can be
has several different modes of operation, and is shipped in the increased by placing optional resistor R3. The required value
following configuration: would vary with process and needs to be tuned for the specific
• Offset Binary application. Full scale can similarly be reduced by placing R4;
• Internal Voltage Reference tuning would be required here as well. An external reference can
be used by shorting the SENSE pin to 3.3 V (place jumper
• CMOS Parallel Timing E26–E25). E27–E24 jumper connects the ADC VREF pin to
• Full-Scale Adjust = Low EXT_VREF pin at the power connector.
Power Connector Data Format Select
Power is supplied to the board via a detachable 12-lead power Data Format Select sets the output data format of the ADC. Set-
strip (three 4-pin blocks). ting DFS (E1–E2) low sets the output format to be offset binary;
setting DFS high (E1–E3) sets the output to two’s complement.
Table II. Power Connector I/P
AVDD 3.3 V Analog Supply for ADC (~ 350 mA) Output timing is set at E11–E13. E12–E11 sets S4 low for
DRVDD 3.3 V Output Supply for ADC (~ 28 mA) parallel output timing mode. E11–E13 sets S4 high for interleaved
VDL 3.3 V Supply for Support Logic and DAC (~350 mA) timing mode.
EXT_VREF* Optional External Reference Input Timing Controls
VCLK/V_XTAL Supply for Clock Buffer/Optional XTAL Flexibility in latch clocking and output timing is accomplished
VAMP Supply for Optional Amp by allowing for clock inversion at the timing controls section of
*LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper
the PCB. Each buffered clock is buffered by an XOR and can be
(AVDD, DrVDD,VDL are the minimum required power connections). inverted by moving the appropriate jumper for that clock.
Analog Inputs Data Outputs
The evaluation board accepts a 1.3 V p-p analog input signal The ADC digital outputs are latched on the board by four LVT574s;
centered at ground at SMB connector J4. This signal is terminated the latch outputs are available at the two 40-pin connectors at pins
to ground through 50 Ω by R16. The input can be alternatively 11–33 on P23 (channel A) and pins 11–33 on P3 (channel B).
terminated at T1 transformer secondary by R13, R14. T1 is a The latch output clocks (data ready) are available at Pin 37 on
wideband RF transformer providing the single-ended to differential P23 (channel A) and Pin 37 on P3 (channel B). The data ready
conversion allowing the ADC to be driven differentially, minimizing clocks can be inverted at the timing controls section if needed.
even order harmonics. An optional second transformer T2 can be
placed following T1 if desired. This would provide some perfor- !: 4.6nS
mance advantage (~1–2 dB) for high analog input frequencies C1 FREQ
84.65608MHz
(>100 MHz). If T2 is placed, two shorting traces at the pads would
need to be cut. The analog signal is low pass filtered by R41,
C12, and R42, C13 at the ADC input.
Gain
1
Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =
1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential.
2
Encode
The encode clock is terminated to ground through 50 Ω at SMB
connector J5. The input is ac-coupled to a high-speed differential
receiver (LVEL16) which provides the required low-jitter, fast CH1 2.00V" CH2 2.00V" M 5.00nS CH2
edge rates needed for optimum performance. J5 input should be
Figure 13. Data Output and Clock @ 80-Pin Connector

-14- 4/01/2002 REV. PrG

 PRELIMINARY TECHNICAL DATA
AD9430
DAC Outputs Optional Amplifier
Each channel is reconstructed by an on-board dual-channel DAC, The footprint for transformer T2 can be modified to accept a
an AD9753. This DAC is intended to assist in debug—it should wideband differential amplifier (AD8350) for low frequency
not be used to measure the performance of the ADC. It is a current applications where gain is required. Note that Pin 2 would need
output DAC with on-board 50 Ω termination resistors. The to be lifted and left floating for operation. Input transformer T1
figure below is representative of the DAC output with a full-scale would need to be modified to a 4:1 for impedance matching and
analog input. The scope setting is low bandwidth. ADC input filtering would enhance performance (see AD8350
data sheet). SNR/SINAD Performance of 61 dB/60 dB is pos-
sible and would start to degrade at about 30 MHz.
C1 FREQ
10.33592MHz
CUT TRACE
C1 PK-PK
448mV

AD9430

CH1 2.00mV" M 25.0nS CH1 248mV

Figure 14. DAC Output CUT TRACE

Encode Xtal
An optional xtal oscillator can be placed on the board to serve
Figure 16. Using the AD8350 on the AD9430 PCB
as a clock source for the PCB. Power to the xtal is through the
VCLK/VXTAL pin at the power connector. If an oscillator is used,
ensure proper termination for best results. The board has been
tested with a Valpey Fisher VF561 and a Vectron JN00158-163.84.
Test results for the VF561 are shown below.

0
ENCODE 163.84MHz
–10 ANALOG 65.02MHz
SNR 63.93dB
–20 SINAD 63.87dB
FUND –0.45dBFS
–30 2ND –85.62dBc
3RD –91.31dBc
4TH –90.54dBc
–40
5TH –90.56dBc
6TH –91.12dBc
dB

–50 THD –82.21dBc

SFDR 83.93dBc
–60 SAMPLES 8k
NOISEFLR –100.44dBFS
–70 WORSTSP –83.93dBc

–80

–90

–100
0 20 40 60 80
MHz

Figure 15. FFT—Using VF561 XTAL as Clock Source

REV. PrG 4/01/2002 -15-

 PRELIMINARY TECHNICAL DATA
AD9430
Table III. Evaluation Board Bill of Materials

No. Qty. Reference Designator Device Package Value Comments

1 45 C1, C3–C11, C15–C17, Capacitor 0603 0.1 µF C43, C47
C19–C29, C31–C48, Not Placed
C58–C62
2 0 C2 Capacitor 0603 10 pF Not Placed
3 0 C12, C13 Capacitor 0603 20 pF Not Placed
4 1 C14 Capacitor 0603 0.01 µF
5 0 C18 Capacitor 0603 1 µF
6 7 C30, C49, C63–C67 Capacitor CAPL 10 µF C30 Not Placed
7 9 E3–E1–E2 3-Pin Header/Jumper
E19–E17–E18 3-Pin Header/Jumper
E13–E11–E12 3-Pin Header/Jumper
E26–E25–E27–E24 4-Pin Header
E46–E47–E45 3-Pin Header/Jumper
E35–E33–E34 3-Pin Header/Jumper
E32–E30–E31 3-Pin Header/Jumper
E29–E23–E28 3-Pin Header/Jumper
E22–E16–E21 3-Pin Header/Jumper
8 5 J1, J2, J3, J4, J5, J6 SMB SMB J1 Not Placed
9 2 P3, P23 40-Pin Header
10 3 P4, P21, P22 4-Pin Power Connector Post 25.531.3425.0 Wieland
Detachable
Connector 25.602.5453.0 Wieland
11 8 R1, R5, R13, R14, R16, Resistor 0603 50 Ω R1, R13, R14
Not Placed
R25, R27, R28, R41, R42
12 1 R2, R3, R4 Resistor 0603 3.9 kΩ R3, R4 Not Placed

13 8 R6–R8, R10, R15, Resistor 0603 100 Ω R15, R21–R24, R38

Not Placed
R21–R24, R33–R36, R38
14 5 R12, R30, R37 Resistor 0603 0Ω
15 4 R17, R18, R19, R20 Resistor 0603 510 Ω
16 1 R26 Resistor 0603 2 kΩ
17 1 R29 Resistor 0603 390 Ω
18 7 R31, R32, R39, R40, R43, Resistor 0603 1 kΩ
R44, R45
19 4 RZ1, RZ2, RZ3, RZ4 Resistor Pack 220 Ω SO16RES 742C163221JTR CTS
20 8 RZ5, RZ6, RZ7, RZ8, RZ9, Resistor Pack 22 Ω SO16RES 742C163220JTR CTS
RZ10, RZ11, RZ12
21 1 T1, T2 Transformer CD542 Minicircuits T2 Not Placed
ADT1–1WT
22 1 U1 AD9430BSV TQFP100 ADC
23 1 U2 MC100LVEL16D SO8NB Clock Buffer
24 1 U3 74LCX86 SO14NB Xor/Buffer
25 4 U4, U5, U6, U7 74LVT574 SO20 Latch
26 1 U9 AD9753AST LQFP48 DAC

-16- 4/01/2002 REV. PrG

 P1 1
2 74LCX86
P2 1 GND

P4
3 VCC E35 COUTA U4
P3 GND 3 RZ1 220 RZ8 22
4
VAMP 2 U3 CLKLATA 1 20
P4 E33 R33 GND OUT_EN VCC VDL P40 P39 GND
R10 1 R1 16 2 19 1 R1 16
1 VDL E20 GND E34 100" D0 Q0 DRX P38 P37 DRA
P1 VCLK/ V_XTAL 100" R2 R2 P36 P35 GND
2 2 15 3 18 2 15
P2 EXT_VREF D1 Q1 DX11 P34 P33 DX11
3 74LCX86 R3 R3

P21
P3 GND DRVDD E7 3 14 4 17 3 14 P32 P31 DX10
4 4 D2 Q2 DX10
P4 VDL VCC E32 COUTA 6 R4 R4 P30 P29 DX9
H4 5 U3 DRA 4 13 5 16 4 13
E30 D3 Q3 DX9 P28 P27 DX8
MTHOLES COUT COUTA R34 R5 R5
P1 1 GND R8 5 12 6 15 DM8 5 12 P26 P25 DX7
2 R9 GND E31 100" D4 Q4 DX8

REV. PrG 4/01/2002

P2 DRVDD R6 R6 P24 P23 DX6
3 H3 100" 6 11 7 14 DM7 6 11 P22 P21 DX5

P22
P3 GND MTHOLES D5 Q5 DX7
4 74LCX86 7 R7 10 8 13 DM6 7 R7 10 P20 P19 DX4
P4 AVDD (VCC) 9

PTMICA04 PTMICA04 PTMICA04

D6 Q6 DX6 P18 P17 DX3
H2 COUTB COUTAB VCC E29 COUTAB 8 R8 R8
MTHOLES 10 U3 CLKLATB 8 9 9 12 DM5 8 9 P16 P15 DX2
R11 D7 Q7 DX5
E23 R35 P14 P13 DX1
R7 10 11
H2 GND E28 100" GND GND CLOCK CLKLATA P12 P11 DX0
MTHOLES 100" P10 P9 DXA
GND LVT574
74LCX86 P8 P7 DXB
12 P6 P5 DRX
VCC E22 COUTAB 11 U5 P4 P3
13 U3 DRB RZ2 220 RZ7 22
E16 R36 1 20 P2 P1 GND
GND OUT_EN VCC VDL
GND E21 R6 100" R1 R1 C4OMS
1 16 2 19 1 16
100" D0 Q0 DX4 P23
2 R2 15 3 18 2 R2 15
D1 Q1 DX3
GROUND PAD UNDER PART 3 R3 14 4 17 3 R3 14
D2 Q2 DX2
PLB GND 4 R4 13 5 16 4 R4 13
D3 Q3 DX1
5 R5 12 6 15 5 R5 12
D4 Q4 DX0
6 R6 11 7 14 6 R6 11

GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
GND
VCC
VCC
VCC
GND
GND
DXA

DRVDD
GND
D5 Q5
7 R7 10 8 13 7 R7 10
D6 Q6 DXB
VCC E19 8 R8 9 9 12 8 R8 9

100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
E17 D7 Q7
GND E18 1 75 GND
10
GND CLOCK
11
CLKLATA
DRVDD
2 74
E14 GND LVT574
3 73
4 72
VCC E13
E11 5 71
GND E12 6 70
GND 7 69
GND GND 8
R39 R41 VCC 68
VCC E10 1k" 25" 9 67
VCC E26 GND GND

-17-
E8 R3 10 66
E29
GND E9 11 AD9430 65
GND E27 12
R39 GND U1 64 COUT
EXT_VREF E24 C1 13 GND
VCC E6 1k" GND 63 COUTB U6
R4 0.1#F 14 62 RZ3 220 RZ6 22
E4 VCC DRVDD 1 20
VDL
15 61 GND OUT_EN VCC P40 P39 GND
GND E5 VCC GND R1 R1
16 60 1 16 2 19 1 16 P38 P37 DRB
VCC E3 R3, R4 GND GND D0 Q0 DRY
17 59 R2 R2 P36 P35 GND
E1 OPTIONAL GND 2 15 3 18 2 15
18 58 D1 Q1 DY11 P34 P33 DY11
GND E2 VCC 3 R3 14 4 17 3 R3 14
19 57 D2 Q2 DY10 P32 P31 DY10
VCC P30 P29 DY9
C12 20 56 4 R4 13 5 16 4 R4 13
GND D3 Q3 DY9 P28 P27 DY8
20pF 21 55
T2 5 R5 12 6 15 5 R5 12 P26 P25 DY7
C43 22 54 D4 Q4 DY8
OPTIONAL DRVDD P24 P23 DY6
0.1#F 23 53 6 R6 11 7 14 6 R6 11
GND GND GND D5 Q5 DY7 P22 P21 DY5
T1 T2 24 52 R7 R7
R14 C3 ADT1-1WT R41 VCC 7 10 8 13 7 10 P20 P19 DY4
ADT1-1WT 25 51 D6 Q6 DY6
29" 0.1#F 25" GND P18 P17 DY3
1 4 1 4 8 R8 9 9 12 8 R8 9 P16 P15 DY2

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

D7 Q7 DY5
5 2 GND 5 2 C11 0.1#F P14 P13 DY1
GND GND 10 11

Figure 17a. Evaluation Board Schematic

R16 C13 GND GND CLOCK CLKLATA P12 P11 DY0
50" 3 6 3 6 P10 P9 DYA
C6 R13 20pF LVT574

VCC
VCC
VCC
VCC
VCC
PRI SEC C2 PRI SEC P8 P7 DYB

GND
GND
GND
GND
GND
GND
GND

0.1#F 25" R42

J4 10pF 25" P6 P5 DRY
DRVDD

GND U7 P4 P3
C6 R5 RZ4 220 RZ5 22
0.1#F C47 50" 1 20 P2 P1 GND
0.1#F GND OUT_EN VCC VDL
GND 1 R1 16 2 19 1 R1 16 C4OMS
E19 R13, R14 OPTIONAL D0 Q0 DY4 P3
ANALOG DATA SYNC J1 CLK– 2 R2 15 3 18 2 R2 15

CLK+
R1 D1 Q1 DY3
R3
PRELIMINARY TECHNICAL DATA

50" 3 14 4 17 3 R3 14
VCC E45 D2 Q2
C36 GND 4 R4 13 5 16 4 R4 13
E47 D3 Q3 DY2
0.1#F 5 R5 12 6 15 5 R5 12
VCLK E46 J2 D4 Q4 DY1
U2 GND R6 R6
8 6 11 7 14 6 11
C5 D5 Q5 DY0
VCC 7 R7 10 8 13 7 R7
0.15#F MC100LVEL 16 R1 NOT PLACED D6 Q6 10 DYA
2 7
J5 D Q 8 R8 9 9 12 8 R8 9
ENCODE D7 Q7 DYB
R27 6
3 DN
QN 10 11
50" GND GND CLOCK CLKLATB
4 VBB
R20 R19 E36
R17 R10 LVT574
GND VEE 510" 510" 00
510" 510" R12
5
GND VCC +
C8 C30
0.1#F C4 10#F
0.1#F
GND
GND GND
AD9430
 PRELIMINARY TECHNICAL DATA
AD9430
VCC
+ C64 C16 C17 C19 C21 C20 C23 C22 C25 C24 C27 C26 C29 C28 C31 C32 C35
10#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F

GND

VDL
+
C67 C44 C42 C41 C15 C37
10#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F

GND

DRVDD VCLK VREF VAMP

+ C65 C61 C62 C60 C14 +
C59 C58 C66 + C63 C49 C48
10#F 0.1#F 0.1#F 0.1#F 0.1#F 0.1#F 10#F 0.01#F 10#F 10#F 0.1#F

GND GND GND GND

GND OPIN B OPIN B

VCLK
R15 GND GND
100" 1 R21
VCC 6

OUT–
GND
GND
E/D VCLK 100"

IN–
R38 2 5
NC OUTPUT B P1
100" 3 4 R22 8 7 6 5
GND GND OUTPUT
100" VCLK
U8 AD9430 OPTIONAL AMP
R38 FOR GND R23
VF561 CRYSTAL 100"
P2 1 2 3 4 U10

IN+
ENBL
VCC
R24

OUT+
100"

OPTIONAL XTAL GND GND VAMP

OPIN OPIN

J6 C34
R25 VOL 0.1U
50"
GND
GND
GND E4Z VOL
J3 E40
R28 E41 GND
VOL 50"
R44
R30 GND GND
0" C33 1k"
GND
GND 0.1U
C38 C18 E39 VOL
0.1U GND R26 E37
.1U R29 2k" E38 GND
392"
GND
R45 RZ12
1k"
48
47
46

45
44
43
42
41

40
39
38
37

VOL 9 R8 8
R43
1k" 10 R7 7
1
GND 36 11 R6 6
R31 R37 2 DYB
1k" DRA 35 12 R5 5
0" 3 DYA
C40 34 13 R4 4
0.1U 4 DY0
R32 GND 33 14 R3 3
1k" VOL DY1
5 32 15 R2 2
DY2
C45 C48 6 31 16 R1 1
0.1U 0.1U DY3
GND
GND 220
AD9430
GND RZ10
RZ9
30 9 R8 8
R1 DY4
DX11 1 16 7 29 10 R7 7
R2 DY5
DX10 2 15 8 28 11 R6 6
R3 DY6
DX9 3 14 9 27 12 R5 5
R4 DY7
DX8 4 13 10 26 13 R4 4
R5 DY8
DX7 5 12 11 25 14 R3 3
R6 DY9
DX6 6 11 12 15 R2 2
R7 DY10
DX5 7 10 16 R1 1
R8 DY11
13
14
15
16
17
18
19
20
21
22
23
24

DX4 8 9
220
220
RZ11
GND

1 R1 16
DX3
2 R2 15
DX2
3 R3 14
DX1
4 R4 13
DX0
5 R5 12
DXA
6 R6 11
DXB
7 R7 10 GND VOL
8 R8 9 C35
0.1U
220

Figure 17b. Evaluation Board Schematic

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 PRELIMINARY TECHNICAL DATA
AD9430

Figure 18. PCB Top Side Silkscreen Figure 21. PCB Split Power Plane

Figure 19. PCB Top Side Copper Figure 22. PCB Bottom Side Copper

Figure 20. PCB Ground Layer Figure 23. PCB Bottom Side Silkscreen
REV. PrG 4/01/2002 -19-
 PRELIMINARY TECHNICAL DATA
AD9430
Troubleshooting The AD9430 Evaluation Board is provided as a design example
If the board does not seem to be working correctly, try the following: for customers of Analog Devices, Inc. ADI makes no warranties,
• Verify power at IC pins. express, statutory, or implied, regarding merchantability or
• Check that all jumpers are in the correct position for the fitness for a particular purpose.
desired mode of operation.
• Verify VREF is at 1.23 V.
• Try running Encode Clock and Analog Inputs at low speeds
(10 MSPS/1 MHz) and monitor 574, DAC, and ADC outputs
for toggling.

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

100-Lead TQFP (with Exposed Heat Sink)

(TQFP-100)

0.047 (1.20) 0.630 (16.00) SQ

MAX
0.030 (0.75) 0.551 (14.00) SQ
0.024 (0.60) 100 76 76 100
0.018 (0.45) 1 75 75 1
BOTTOM VIEW
SEATING
PLANE

TOP VIEW
(PINS DOWN)

CONDUCTIVE
HEAT SINK

25 50 50 25
26 49 49 26

0.006 (0.15) 0.041 (1.05)

0.039 (1.00) 0.260 (6.00) NOM
0.002 (0.05)
0.037 (0.95)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.
0.0197 (0.50) 0.011 (0.27) 7$
BSC 0.009 (0.22) 0$
0.007 (0.17)

NOTE:
THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE
WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

-20- 4/01/2002 REV. PrG