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Coverage of Random Variables in SystemVerilog

The document contains multiple code snippets demonstrating the use of covergroups in SystemVerilog to cover various scenarios such as random variable ranges, card values, student marks, and more. Each example includes a class definition with random variables, coverpoints, and sampling methods to track coverage. The coverage results are displayed after a specified number of iterations.

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N180243 GOLLA SAILAJA
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43 views15 pages

Coverage of Random Variables in SystemVerilog

The document contains multiple code snippets demonstrating the use of covergroups in SystemVerilog to cover various scenarios such as random variable ranges, card values, student marks, and more. Each example includes a class definition with random variables, coverpoints, and sampling methods to track coverage. The coverage results are displayed after a specified number of iterations.

Uploaded by

N180243 GOLLA SAILAJA
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

1) Cover all values of a random variable between 0 and 100

Code snippet

class ram;

rand bit [6:0] a; // 7-bit to cover values 0–100

covergroup cov;

cp1: coverpoint a { bins b[] = {[0:100]}; }

endgroup

func on new();

cov = new(); // instan ate covergroup inside the constructor

endfunc on

endclass

module rakesh;

ram pkt;

ini al begin

pkt = new(); // create the ram object

repeat(201) begin

void'([Link]()); // randomize 'a'

[Link](); // sample the covergroup

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

2) Cover even and odd mul ples of 10 within 0:100

Code snippet

class ram;

rand bit [6:0] a; // 7-bit to cover values 0–100


covergroup cov();

cp1_eve: coverpoint a { bins even_bin[] = {[0:100]} with (item % 2 == 0 && item % 10 == 0);}

cp2_odd: coverpoint a { bins odd_bin[] = {[0:100]} with (item % 2 == 1 && item % 10 == 0);}

endgroup

func on new();

cov = new(); // instan ate covergroup inside the constructor

endfunc on

endclass

module rakesh;

ram pkt;

ini al begin

pkt = new(); // create the ram object

repeat(100) begin

void'([Link]()); // randomize 'a'

[Link](); // sample the covergroup

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

3) Cover all 52 deck cards

Code snippet

class ram;

typedef enum {ACE = 0, TWO = 1, THREE = 2, FOUR = 3, FIVE = 4, SIX = 5, SEVEN = 6,

EIGHT = 7, NINE = 8, TEN = 9, JACK = 10, QUEEN = 11, KING = 12} values;

typedef enum {HEARTS, DIAMONDS, CLUBS, SPADES} suits;

rand values value;


rand suits suit;

covergroup cov ();

cp_value: coverpoint value {

bins numeric[] = {[TWO:TEN]};

bins ace = {ACE};

bins face = {JACK, QUEEN, KING};

cp_suit: coverpoint suit {

bins hearts = {HEARTS};

bins diamonds = {DIAMONDS};

bins clubs = {CLUBS};

bins spades = {SPADES};

cross_vales_suit : cross cp_value, cp_suit;

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt ;

ini al begin

repeat(100) begin

pkt = new();

void'([Link]());

[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());


$finish;

end

endmodule

4) Cover students marks bins 0_50, 51_75, 76_100

Code snippet

class ram;

rand bit [6:0] marks;

covergroup cov();

mark: coverpoint marks {

bins low = {[0:50]};

bins medium_s = {[51:75]};

bins high = {[76:100]};

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt ;

ini al begin

repeat(100) begin

pkt = new();

void'([Link]());

[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule
5) Cover dice 1 to 6

Code snippet

class ram;

rand bit [2:0] dice;

covergroup cov();

mark: coverpoint dice { bins values[] = {[1:6]}; }

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt ;

ini al begin

repeat(100) begin

pkt = new();

void'([Link]());

[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

6) Cover traffic light dura ons green (30-60) yellow (5-10) red (50-90)

Code snippet

class ram;

rand bit[6:0] dura on;

typedef enum {red, yellow, green} light_colors;

rand light_colors lights;

covergroup cov();
cp1: coverpoint dura on {

bins yellow_d = {[5:10]};

bins green_d = {[30:60]};

bins red_d = {[50:90]};

cp2: coverpoint lights;

cp_cross: cross cp1, cp2;

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt ;

ini al begin

repeat(100) begin

pkt = new();

void'([Link]());

[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

8) Cover temperature values in 4 bins

Code snippet

class ram;

rand int temperature;

covergroup temp_cov;
cp_temp: coverpoint temperature {

bins low = {[0:20]};

bins normal = {[21:35]};

bins warning = {[36:50]};

bins cri cal = {[51:100]};

endgroup

func on new();

temp_cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (100) begin

void'([Link]() with {temperature inside {[0:100]};});

pkt.temp_cov.sample();

end

$display("Coverage = %0.2f%%", pkt.temp_cov.get_coverage());

$finish;

end

endmodule

9) Cover different lengths of burst transac ons

Code snippet

class ram;

rand bit [7:0] length;

rand bit [1:0] burst;

covergroup cov ();


cp_fixed: coverpoint length iff(burst == 2'b00) { bins fix = {[0:15]}; }

cp_incr: coverpoint length iff(burst == 2'b01) { bins incr = {[0:255]}; }

cp_wrap: coverpoint length iff(burst == 2'b10) { bins wrap = {1, 3, 7, 15}; }

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (100) begin

void'([Link]());

[Link]();

$display("length=%d, burst=%b", [Link], [Link]);

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

10) Cover all combina ons of signal A (0/1) and signal B (0/1)

Code snippet

class ram;

rand bit a, b;

covergroup cov();

cp1: coverpoint a { bins zero = {0}; bins one = {1}; }

cp2: coverpoint b { bins zero = {0}; bins one = {1}; }

cp1_cp2: cross cp1, cp2;

endgroup

func on new();
cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (100) begin

void'([Link]());

[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

11) Cover id field values from 0 to 15 in a packet.

Code snippet

class ram;

rand bit [3:0] id;

covergroup cov();

cp1: coverpoint id { bins b1[] = {[0:15]}; }

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (100) begin

void'([Link]());
[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

12) Cover binary vector values with an even number of 1s

Code snippet

class ram;

rand bit [3:0] data;

covergroup cov();

cp1: coverpoint data iff ($countones(data) % 2 == 0) { bins b1 [] = {[0:15]}; }

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (100) begin

void'([Link]());

[Link]();

end

$display("Coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

13) Cover all valid IP address ranges (first byte: 10, 172, 192).

Code snippet

class ram;
rand bit [7:0] valid_addr;

constraint con { valid_addr inside {10, 172, 192}; }

covergroup cov();

cp1: coverpoint valid_addr { bins b1[] = {10, 172, 192}; }

endgroup

func on new();

cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (200) begin

void'([Link]());

[Link]();

end

$display("coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

14) Cover valid and invalid packet types.

Code snippet

class ram;

rand bit [2:0] packet_type;

covergroup cov();

cp1: coverpoint packet_type {

bins valid = {[0:4]};

bins invalid = {[5:7]};

endgroup

func on new();
cov = new();

endfunc on

endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (100) begin

void'([Link]());

[Link]();

end

$display("coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

15) Transac on Bins with Illegal and Ignore Bins

Code snippet

class ram;

rand bit [3:0] data;

covergroup cov ();

single_value : coverpoint data { bins b1 = {1}; }

sequence_of_bins : coverpoint data { bins b2 = (2 => 3 => 4 => 5); }

set_of_bits : coverpoint data { bins b3 = (1, 2 => 3, 4); }

repe on : coverpoint data { bins b4 = (7 [* 2]); }

non_consecu ve : coverpoint data { bins b5 = (2 [=3] => 5); }

goto_transi on : coverpoint data { bins b6 = (1 [->2] => 9); }

ignore : coverpoint data { ignore_bins b_ignore = {11, 12, 13}; }

illegal : coverpoint data { illegal_bins b_illegal = {14, 15}; }

endgroup

func on new();

cov = new();

endfunc on
endclass

module rakesh;

ram pkt = new();

ini al begin

repeat (200) begin

void'([Link]());

[Link]();

end

$display("coverage = %0.2f%%", [Link].get_coverage());

$finish;

end

endmodule

16) Coverpoints with Op ons and Transi on Bins (Explicit Instance)

Code snippet

class explicit;

rand bit[2:0] a;

rand bit[2:0] b;

rand bit[2:0] c;

constraint ww { a inside {1, 2, 3, 4}; }

constraint xx { b inside {1, 2, 3, 4}; }

constraint zz { c inside {1, 2, 3, 4}; }

endclass

module rakesh;

bit clk;

explicit p1 = new();

covergroup cg @(posedge clk);

op [Link] = 50;

op [Link] = 10;

op [Link] = "rakesh";
op on.per_instance = 0;

op on.at_least = 2;

s1: coverpoint p1.a { bins b1[] = (1, 2 => 3, 4); } // set off transi on

s2: coverpoint p1.b { illegal_bins b2 = {1, 2}; }

s3: coverpoint p1.c { bins b3 = (4 [* 2]); } // consecu ve repe on

s4: coverpoint p1.a { bins b111 = (2 [<=2] => 4 [=2] => 3); } // non-consecu ve repe on

s5: coverpoint p1.b { bins b7 = (2 [<=1] => 3 [->2] => 2); } // goto repe on, both are same

// s6: coverpoint p1.c { ignore_bins b = {2, 3, 4}; }

/* s1:coverpoint p1.a;

s2:coverpoint p1.b;

s3:coverpoint p1.c;

s2_s3:cross s1,s2; */

endgroup

covergroup cgr @(posedge clk);

op [Link] = 70;

op [Link] = 5;

op [Link] = "rakesh3";

op on.per_instance = 1;

op on.at_least = 1;

s1: coverpoint p1.a { bins b1[] = (1, 2 => 3, 4); }

s3: coverpoint p1.c { bins b3 = (4 [* 2]); } // consecu ve repe on

endgroup

always #5 clk = ~clk;

ini al begin

cg p2 = new();

cgr p3 = new();

repeat(200) begin
[Link]();

[Link]();

[Link]();

$display("a=%d, b=%d, c=%d", p1.a, p1.b, p1.c);

end

Common questions

Powered by AI

Cross coverage applies to combinations of signals A and B by defining coverpoints for each signal, each with bins for possible values (0 and 1), and then a cross coverpoint that combines these. This ensures that all combinations of A and B are tested, providing thorough verification of all possible states the signals can assume together .

The SystemVerilog snippet ensures coverage of traffic light durations by using a covergroup with bins defined for different ranges of duration values: green durations from 30 to 60 seconds, yellow durations from 5 to 10 seconds, and red durations from 50 to 90 seconds. This allows the testbench to determine if all possible light durations are being tested by the design .

Ignore and illegal bins serve specific purposes in SystemVerilog transaction bins: ignore bins are used to exclude certain values from affecting coverage metrics, while illegal bins define values that are not supposed to occur under correct operation. This allows testers to focus on relevant scenarios and quickly identify erroneous states that may require deeper investigation .

The code snippet categorizes card deck values using enumerated types for card values (e.g., ACE, TWO, THREE) and suits (e.g., HEARTS, DIAMONDS). The covergroup specifies coverpoints for numeric cards (TWO to TEN), aces, and face cards (JACK, QUEEN, KING) as well as for each suit. By creating bins for these categories, the code ensures comprehensive coverage across different card types and suits .

Setting constraints on rand variables in SystemVerilog is significant because it limits the range of random values to specific ones meaningful to the verification context. For example, the valid IP address coverage limits the first byte to specific values (10, 172, 192), ensuring that the testbench only generates and evaluates addresses within these valid ranges. This focuses testing on relevant cases, improving efficiency and relevance .

Covergroups in a SystemVerilog testbench are used to measure the coverage of certain values or conditions in the design under test. For example, they can cover all values of a random variable, certain value ranges, or combinations of bits, ensuring that the testbench stimulates all desired conditions to validate the design effectively .

The benefits of having cross coverage for values and suits of a deck of cards in SystemVerilog verification include comprehensive test coverage and efficiency in identifying rare or unique error conditions. Cross coverage ensures that all combinations of card values and suits are accounted for, which helps identify bugs that might only manifest under specific combinations. This thoroughness is key in complex systems where interactions between categories can lead to subtle issues .

Coverage of binary vectors with an even number of 1s is checked by defining a coverpoint with a condition that uses the $countones function in SystemVerilog. This function counts the number of 1s in the vector, and the coverpoint bins values where this count is even, ensuring that all valid cases of even-numbered 1s are covered by the testbench .

The code snippet for covering student marks ensures a balanced distribution by defining bins for different mark ranges (0-50, 51-75, 76-100) using a covergroup. This approach allows the coverage analysis to verify whether each of these ranges is adequately exercised during testing, helping testers identify untested ranges and adjust their stimuli accordingly .

The SystemVerilog example handles even and odd multiples of 10 separately by defining two distinct coverpoints within a covergroup. One coverpoint bins even multiples of 10 by using a condition that checks if the number is even and a multiple of 10, and the other bins odd multiples using a similar condition for odd numbers. This allows targeted testing for these specific categories .

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