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TUTORIALS INTERFACE Index
Interface
SystemVerilog Ports
Verification Interface Methods
Clocking Block
Constructs
The communication between blocks of a digital system is a critical area. In Verilog, Virtual Interface
Interface modules are connected using module ports. For large modules, this is not Svtb N Verilog Dut
OOPS productive as it involves
Randomization Report a Bug or Comment
Manually connecting hundreds of ports may lead to errors. on This section ‐ Your
Functional Coverage
Detailed knowledge of all the port is required. input is what keeps
Assertion Difficult to change if the design changes. [Link] improving
DPI More time consuming. with time!
Most port declaration work is duplicated in many modules.
UVM Tutorial
VMM Tutorial Let us see a verilog example:
OVM Tutorial
Easy Labs : SV
module Dut (input clk, read, enable,
Easy Labs : UVM Input [7:0] addr,
Easy Labs : OVM output [7:0] data);
Easy Labs : VMM ....
assign data = temp1 ? temp2 : temp3 ;
AVM Switch TB
always @(posedge clk)
VMM Ethernet sample ....
endmodule
Verilog module Testbench(input clk,
Verification Output read, enable,
output [7:0] addr,
Verilog Switch TB
input [7:0] data );
Basic Constructs endmodule
OpenVera
Constructs Integrating the above two modules in top module.
Switch TB
RVM Switch TB
RVM Ethernet sample
Specman E
Interview Questions
1 module top();
2 reg clk;
3 wire read, enable;
4 wire [7:0] addr;
5 wire [7:0] data;
6
7 Dut D (clk,read,enable,Addr,data);
8
9 Testbench TB(clk,read,enable,Addr,data);
10
11 endmodule
All the connection clk, read, enable, addr, data are done manually. Line 7 and 9 has
same code structure which is duplicating work. If a new port is added, it needs
changes in DUT ports, TestBench Ports, and in 7, 10 lines of Top module. This is
time‐consuming and maintaining it is complex as the port lists increases.
To resolve the above issues, SystemVerilog added a new powerful features called
interface. Interface encapsulates the interconnection and communication between
blocks.
Interface declaration for the above example:
interface intf #(parameter BW = 8)(input clk);
logic read, enable;
logic [BW ‐1 :0] addr,data;
endinterface :intf
Here the signals read, enable, addr, data are grouped in to "intf". Interfaces can
have direction as input, output and inout also. In the above example, clk signal is
used as input to interface. Interfaces can also have parameters like modules.
Interface declaration is just like a module declaration. Uses keywords interface,
endinterface for defining. Inside a module, use hierarchical names for signals in an
interface.
TIP: Use wire type in case of multiple drivers. Use logic type in case of a single
driver.
Let use see the DUT and Testbench modules using the above declared interface.
module Dut (intf dut_if); // declaring the interface
always @(posedge dut_if.clk)
if(dut_if.read) // sampling the signal
$display(" Read is asserted");
endmodule
module Testbench(intf tb_if);
initial
begin
tb_if.read = 0;
repeat(3) #20 tb_if.read = ~tb_if.read;// driving a signal
$finish;
end
endmodule
Integrating the above two modules in top module.
module top();
bit clk;
initial
forever #5 clk = ~clk;
intf bus_if(clk); // interface instantiation
Dut d(bus_if); // use interface for connecting D and TB
Testbench TB (bus_if);
endmodule
See, how much code we got reduced in this small example itself. In the above
example, I demonstrated the connectivity between DUT and TestBench. Interfaces
can also be used for connectivity between the DUT sub modules also.
Advantages Of Using Inteface:
An interface can be passed as single item.
It allows structured information flow between blocks.
It can contain anything that could be in a module except other module
definitions or instance.
Port definitions are independent from modules.
Increases the reusability.
It Interface can be declared in a separate file and can be compiled separately.
Interfaces can contain tasks and functions; with this methods shared by all
modules connecting to this information can be in one place.
Interface can contain protocol checking using assertions and functional coverage
blocks.
Reduces errors which can cause during module connections.
Easy to add or remove a signal. Easy maintainability.
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