S.K.P.

ENGINEERING COLLEGE
THIRUVANNAMALAI

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

M.E – APPLIED ELECTRONICS

AP 4111 – ELECTRONICS SYSTEM DESIGN LABORATORY

Regulation – 2021

NAME : ……………………………………………
YEAR : ……………………………………………
SEMESTER: ……………………………………………
REG NO:…………………………………………….

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 S.K.P. ENGINEERING COLLEGE
THIRUVANNAMALAI

BONAFIDE CERTIFICATE

NAME……………………………………………………………..YEAR……………
SEM ………. … BRANCH……….…………………………………… REGISTER
NO…………………………………….… certified that this bonafide record of work
done by the above Student of the…….………………………… …….laboratory
during the year 2021-2022.

Staff in-charge Head of the Department

Submitted for the practical Examination held on…………………………..

at [Link] COLLEGE, THIRUVANNAMALAI.

INTERNAL EXAMINER EXTERNAL EXAMINIER

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 CONTENT

[Link]. DATE NAME OF THE EXPERIMENTS SIGNATURE

PAGE NO.

1.

2.

3.

4.

5.

6.

7.

8.

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[Link]: 1 PCB LAYOUT DESIGN USING CAD
DATE:

AIM:

To design a printed circuit board layout for a given circuit.

APPARATUS REQUIRED:

[Link] computer with windows os.

[Link] layout software such as ORCAD.

THEORY:

General rules for designing PCBs:

The PCB designer follows few rules of thumb that can be used when laying out PCBs.
Here they are,

1. PLACING COMPONENTS:

Generally, it is best to place parts only on the topside of the board. Firstly, place all the
components in specific locations. This includes connectors, switches, LED mounting holes,
heat sinks or any other item that amounts to an external location.
Give careful thought when placing components to minimize trace lengths. Doing a good
job here will make laying the traces much easier. Arrange ICs in only one or two orientations
(up and down or right and left). Align each IC so that pin 1 is in the same place for each
orientation, usually on the top or left sides.
Position polarized parts with the positive leads, all having the same orientation. Also use
a square pad to mark the positive leads of these components. Frequently, the beginners run out
of room when routing traces. Leave 0.35 to 0.5 between ICs. For large ICs allow even more
space.
Parts not found in the component library can be made by placing a series of individual
pads and then group them together. Place one pad for each lead of the component. It is very
important to measure the pin spacing and pin diameters as accurately as possible.
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 After placing all the components, print out a copy of the layout. Place each component
on the top of the layout. Check to ensure that you have allowed enough space for every part to
rest without touching each other.

2. PLACING POWER AND GROUND TRACES:

After the components are placed, the next step is to lay the power and ground traces. A
power rail is run along the front edge of the board and a ground rail along the rear edge. From
these rails attach traces that run in between the ICs. The ground rail should be very wide,
0.100” and all the supply lines should be 0.50”. When using this configuration, the remaining
of the bottom layer is then reserved for the vertical signal traces.

3. PLACING SIGNAL TRACES:

When placing traces, it is always a good practice to make them as short and direct as
possible. Use vias to move signals from one layer to the other. A via is a pad-through hole.
Generally, the best strategy is to lay out a board with vertical trace on one side and horizontal
traces on the opposite side. A good trace width for low current digital and analog signals is
0.010”.
Traces that carry significant current should be wider than signal traces. The table below
gives rough guidelines of how wide should a trace be for a given amount of current.

0.010” 0.3
Amps
0.015” 0.4Amps
0.020” 0.7Amps
0.025” 1Amps
0.050” 2Amps
0.100” 4Amps
-0.150” 6Amps

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 When routing traces, it is best to have the snap to grid turned on. Setting the snap
grid spacing to 0.050” works well. Changing to a value of 0.025” can be helpful when trying to
work as densely as possible. Turning off the snap feature may be necessary when connecting to
parts that have unusual pin spacing. It is a commo0n practice to restrict the direction that traces
run to horizontal, vertical or at 45 degrees angles.
When placing narrow traces, use 0.015” or less. Avoid sharp right angle turns.
The problem here is that, in the board manufacturing process the outside corner can be etched a
little narrower. The solution is to use two 45-degree bends with a short leg in between. It is a
good idea to place text on the top layer of the board, such as the product or company name.

4. CHECKING YOUR WORK:

After all the traces are placed, it is best to double-check the routing of every
signal to verify that nothing is missing or incorrectly wired. Do this by running through the
schematic, one wire at a time. Carefully follow the path of each trace. After each trace is
confirmed, mark the signal on the schematic with a yellow highlighter.

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CIRCUIT DIAGRAM:

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 Inspect the layout, both top and bottom to ensure that the gap between every item is
0.007” or greater. Use the pad information tool to determine the diameters of pads that make up
a component.
Check for missing vias. The CAD software will automatically insert a via when changing
layers as a series of traces are placed. The user often forgets that vias are not automatically
inserted otherwise. For example, when beginning a new trace, a via is to first print a top layer,
then print the bottom.
Visually inspect each side for traces that doesn’t connect to anything. When a missing
via is found, insert one. Do this by clicking on the pad in the side tool bar from the down list
box and click on the layout. Check for the traces that cross each other. Inspecting a printout of
each layer easily does this.
Metal components such as heat sinks, crystals, switches, batteries and connectors can
cause shorts, if they are placed over traces on the top layer. Inspect for these shorts by placing
all the metal components on a printout of the top layer. Then look for traces that run below the
metal components.

RESULT:

Thus, the PCB is designed using CAD.

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[Link]: 2 AC/DC VOLTAGE REGULATOR USING SCR
DATE:

AIM:

(i)To design, construct and test an AC voltage regulator using SCR.

(ii)To design, construct and test a DC voltage regulator using SCR.

APPARATUS REQUIRED:

AC VOLTAGE REGULATOR:

[Link] Name of the Range Quantity

Apparatus
1 Transformer 230V/12V 1
2 SCR 2P4M 2
3 Diode BY 127 2
4 Resistor 100k, 2
12k 1
5 Bread Board 1
6 Connecting Wires As required
7 CRO 1
8 DRB 1

DC VOLTAGE REGULATOR:

[Link] Name of the Range Quantity

Apparatus
1 Transformer 230V/24V 1
2 SCR TYN 604 1
3 Diode 1N4001 4
4 Resistor 10 k 2
5 Bread Board 1
6 Connecting wires As required
7 CRO 1
8 DRB 2
9 IC 7812 1
10 Capacitors 1000µf, 100µf 1,1

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THEORY:

The SCR is switched ON and OFF to regulate the output voltage in AC and DC
voltage regulator.

AC VOLTAGE REGULATOR:

If the SCR is connected to AC supply and load, the power flow can be controlled
by varying the RMS value of AC voltage applied to the load and this type of power circuit is
caused as AC voltage regulator.
Applications of AC voltage regulator are in heating on load transformers for
changing light controls, speed controls and polyphase controls, induction motors and AC
magnet controls for power transfer. Two types of power control are normally used.

(1) ON-OFF control

(2) Polyphase Angle control

AC regulators are those converters which converts fixed ac voltage directly to

variable ac voltage of the same frequency. The load voltage is regulated by controlling the
firing angle of SCRs. AC voltage controllers are thyristor -based devices.
The most common circuit is the inverse parallel SCR pair in which two isolated gate
signals are applied. Each of the two SCRs is triggered at alternate half cycles of the supply and
the load voltage is part of input sine wave. The SCR is a unidirectional device like diode, it
allows current flow in only one direction but unlike diode, it has built-in feature to switch ON
and OFF. The switching of SCR is controlled by gate and biasing condition. This switching
property of SCR allows controlling the ON periods thus controlling average power delivered to
the load.
In this circuit SCR1 is forward biased during positive half cycle and SCR2 is forward

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biased during negative half cycle. SCR1 is triggered at the firing angle ωt=α and supply voltage
is impressed on the load resistance (RL). It conducts from the remaining positive half cycle,
turning OFF when the anode voltage becomes zero at ωt=π.
SCR2 is triggered at the firing angle ωt=α+π and conducts till ωt=2π. Hence the load is
alternating in polarity and is part of sine wave. The firing angle of both SCRs is controlled by
gate circuit. The conduction period of SCR is controlled by varying gate signals within
specified values of maximum and minimum gate currents.
For gate triggering, a signal is applied between the gate and cathode of the device. AC
sources are normally used as gate signals. This provides proper isolation between powers.

DC VOLTAGE REGULATOR:

If SCRs are used to convert an AC voltage into DC voltage, then they are known as
DC voltage regulators. Eg. Battery changes for high current capacity batteries in DC voltage
control only phase control is used.
The transformer is used to step down the voltage from 230V to 24V. This is given as
input to bridge rectifier. The bridge rectifier converts incoming ac signal to unidirectional
wave. Therefore, we get full wave rectifier output at the output of bridge rectifier. This is given
as input to SCR. The gate of SCR is triggered with firing angle of α. During positive half cycle,
diode D1 and D2 conducts and during negative half cycle, diode D3 and D4 conducts.
The full wave rectified output is given to capacitive filter. The output of capacitor is dc
that it eliminates ripple contents of bridge rectifier output. The dc input is given to regulator IC.
The unregulated output must be 2V greater than regulated output voltage. The load current may
vary from 0 to rated maximum output current. The output voltage is regulated dc.

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CIRCUIT DIAGRAM:

AC VOLTAGE REGULATOR:

DC VOLTAGE REGULATOR:

PIN DETAILS:

AC VOLTAGE REGULATOR:

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DC VOLTAGE REGULATOR:

MODEL GRAPH:

AC VOLTAGE REGULATOR:

DC VOLTAGE REGULATOR:

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DESIGN:

AC VOLTAGE REGULATOR USING SCR:

Triggering circuit for SCR:

12 V ac is rectified by diode BY 127. SCR 2P4M is used to trigger.

Let the current be 1mA. R=V/I=12V/1mA=12KΩ.

DC VOLTAGE REGULATOR USING SCR:

Triggering circuit for SCR:

24 V ac is rectified by diode 1N4001. SCR TYN604 is used to trigger.

Let the current be 1mA. R=V/I=12V/1mA=12KΩ.

PROCEDURE:

AC VOLTAGE REGULATOR USING SCR:

1. Connections are made as shown in the circuit diagram.

2. The supply is given by means of step-down transformer.
3. Anode terminal of SCR1 is connected to the anode terminal of diode, is connected to
cathode of SCR1 by means of resistor as the load.
4. Hence the voltage regulation is verified at load terminal.

DC VOLTAGE REGULATOR USING SCR:

1. Connect the two terminals at the top of bridge rectifier.

2. The positive terminal of the bridge rectifier is connected to one terminal at the load and
at the other terminal to anode terminal of SCR.
3. The pin 15 connected from the power supply to the load.
4. Then the DC voltage regulation is checked and verified.

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TABULAR COLUMN:

AC VOLTAGE REGULATOR:

DRB 1 value (KΩ) Amplitude(V) TON(ms)

DRB 2 value (KΩ) Amplitude(V) TOFF(ms)

DC VOLTAGE REGULATOR:
DRB value(KΩ) Amplitude (V) TON(ms)

Resistance RL(KΩ) Output (V)

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RESULT:

Thus both AC and DC voltage regulators were designed, constructed and the
output waveforms were drawn.

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[Link]: 3 DESIGN A 4-20MA TRANSMITTER USING BRIDGE
DATE: TYPETRANSDUCER

AIM:

To design the instrumentation amplifier with bridge type transducer.

APPARATUS REQUIRED:

[Link]. Name of the Apparatus Range Quantity

1 Operational amplifier IC741 1
2 Resistor 10K, 1K, 2.2K, 7, 4, 1, 1
4.7K
3 Connecting wires - As
required
4 Dual power supply - 1
5 Bread Board - 1

THEORY:

Instrumentation Amplifier:
Instrumentation amplifier is generally required in any measurement system using
electrical transducers to enhance signal levels often in low voltage less than mV. Also it is
required to provide impedance matching and isolation. When the desired input rides over a
common mode signal special amplifier are needed so that difference signals get amplified to an
acceptable level while the common mode signals get attenuated.
The physical quantities can be converted into electrical quantities by using
transducer. The output of the transducer needs to be amplified to get the meter readings. This
amplification is done by using instrumentation amplifier. The output of instrumentation
amplifier drives of indicator or display system. The important features of an instrumentation
amplifier are high gain accuracy, high CMRR, high gain stability with low temperature co-
efficient, low dc offset, low output admittance.

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 Low input impedance may load the signal source heavily. Therefore, high resistance
buffer is used preceding each input to avoid this loading effect. If V1 is not equal to V2 the
circuit has differential gain by the formula V0=[1+(2R/R’) ](V2-V1).

PROCEDURE:

1. Connections are given as per the circuit diagram.

2. The voltages V1 and V2 from the bridge circuit is given to op-amp 1&2.
3. Varying the resistance R’ the voltages of the bridge circuit V1 and V2 were varied. So
different output voltage is obtained.

DESIGN:

Output voltage VO = (1+(2R/R’)) (V2-V1)

Differential gain Ad=Vo/(V2-V1)
=1+(2R/R’)
Choose R=10kΩ
For Ad(max)=100
100=1+(20kΩ/R’)
99*R’=20KΩ
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 R’(max)=200Ω
For Ad(min)=10
10=1+(20KΩ/R’)
R’(min)=2.2KΩ
IL = I1+I2
I1=(V-(Vo/2))/ R, I2=(VO-(Vo/2))/R
IL=(V-(Vo/2) + (Vo-(Vo/2))/R=(V- Vo+ Vo)/R=V

TABULATION:

S.N Resistor(R’) Voltage(V1 Theoretical Practical

o. ) Voltage(V2 value (Vo) value
) (Vo)

THEORETICAL CALCULATION:
R2=R1=R=10KΩ R’=
V1= V2=
VO=(R2/R1) [1+(2R/R’)] (V2-V1)

RESULT:

Thus the Instrumentation amplifier was designed and constructed using bridge type
transducer and the output is verified successfully.

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[Link]: 4 FPGA IMPLEMENTATION OF UP/DOWN COUNTERS
DATE:

AIM:

To implement up and down counters using Verilog HDL.

APPARATUS REQUIRED:

1. PC with Windows XP.

2. XILINX 9.2i
3. FPGA-SPARTAN-3 KIT
4. PARALLEL TO JTAG CABLE

PROCEDURE:

1. New project and type the project name and check the top -level source type as HDL.
2. Enter the device properties and click Next.
3. Click New Source and Select the Verilog Module and then give the file name.
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it.
6. Double click the synthesize XST and check syntax.
7. Simulate the waveform by behavioral simulation.
8. For implementation Select User constraints and give input and output port pin number.
9. Click Implement design for Translate, map and place & route.
10. Generate .bit file using programming file.
11. Implement in FPGA through parallel-JTAG cable.
12. Check the behavior of design in FPGA by giving inputs

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UP COUNTER:

PROGRAM:

module upcounterr(clk,clr,q);
input clk, clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedgeclk or posedgeclr)
begin
if (clr)
tmp<= 4'b0000;
else
tmp<= tmp + 1'b1;
end
assign q = tmp;
endmodule

RTL SCHEMATIC:

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TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

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DOWN COUNTER:

PROGRAM:

module downcounter(clk,clr,q);
input clk, clr;
output [3:0]q;
reg [3:0]tmp;
always@(posedgeclk or posedgeclr)
Begin
if (clr)
tmp<= 4'b1111;
else
tmp<= tmp - 1'b1;
end assign q = tmp;
endmodule

RTL SCHEMATIC:

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TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

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RESULT:

Thus the up and down counters has been verified and implemented.

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[Link]: 5 FPGA IMPLEMENTATION OF UNIVERSAL SHIFT
DATE: REGISTERS

AIM:

To design and implement Verilog HDL code for Universal Shift Register.

APPARATUS REQUIRED:

1. PC with Windows XP.

2. XILINX 9.2i
3. FPGA-SPARTAN-3 KIT
4. PARALLEL TO JTAG CABLE

THEORY:

Universal Shift Register is a register which can be configured to load and/or retrieve the
data in any mode (either serial or parallel) by shifting it either towards right or towards left. In
other words, a combined design of unidirectional (either right- or left shift of data bits as in
case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load
provision is referred to as universal shift register.

N-Bit Universal Shift Register

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PROCEDURE:
1. Create a module with required number of variables and mention it’s input/output.
2. Write the description of the universal shift register.
3. Create another module referred as test bench to verify the functionality.
4. Follow the steps required to simulate the design and compare the obtained output with the
required one.

UNIVERSAL SHIFT REGISTER:

module p20(op,in,s,MSB_in,LSB_in,clk,clr);
input [3:0]in;
input [1:0]s;
input MSB_in,
LSB_in,clk,clr;
output [3:0]op;
reg [3:0]op;
always @( posedgeclk or clr)
begin
if (clr)
op<=0;
else
case (s)
2'b00: op <= op;
2'b01: op <= {MSB_in, op[3:1]};
2'b10: op <= {op[2:0], LSB_in};
2'b11: op <= in;
endcase
end
endmodule

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TRUTH TABLE:

So S1 FUNCTIONALITY
0 0 No change for any number of clock cycles as the
outputs of the flipflops are back fed to themselves
0 1 Data bits within the register shift right for each clock
tick with the serial input bits being provided at D1 via
MUX1
1 0 Data bits within the register shift left for each clock
tick with the serial input bits being provided at Dn via
MUXn
1 1 Bits of the data word to be stored are fed in parallel
format through pin number 3 of each mux at the rising
edge of the clock

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OUTPUT WAVE:

RESULT:

Thus Universal shift register was implemented and outputs are verified successfully.

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[Link]: 6 FPGA IMPLEMENTATION OF STATE MACHINE
DATE:

AIM:

To implement finite state machine (Moore and Mealy machine) using Verilog HDL.

APPARATUS REQUIRED:

1. PC with Windows XP.

2. XILINX 9.2i
3. FPGA-SPARTAN-3 KIT
4. PARALLEL TO JTAG CABLE

PROCEDURE:

1. New project and type the project name and check the top -level source type as HDL.
2. Enter the device properties and click next.
3. Click New Source and Select the Verilog Module and then give the file name.
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it.
6. Double click the synthesize XST and check syntax.
7. Simulate the waveform by behavioral simulation.
8. For implementation select User constraints and give input and output port pin number.
9. Click Implement design for Translate, map and place & route.
10. Generate .bit file using programming file.
11. Implement in FPGA through parallel-JTAG cable.
12. Check the behavior of design in FPGA by giving inputs

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STATE MACHINES:

MOORE MACHINE:

State diagram:

PROGRAM:

module moore( clk, rst, inp, outp);

input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedgeclk, posedgerst )
begin
if( rst )
state <= 2'b00;
else
begin
case(state)
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
2'b10:
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begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @ (posedgeclk, posedgerst)
begin
if( rst )
outp<= 0;
else if (state == 2'b11)
outp<= 1;
else outp<= 0;
end
endmodule

RTL SCHEMATIC:

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TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

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MEALY MACHINE:

State diagram:

PROGRAM:

module mealy( clk, rst, inp, outp);

input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedgeclk, posedgerst ) begin
if( rst ) begin
state <= 2'b00;
outp<= 0;
end
else begin
case(state)
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp<= 0;
end
else begin
state <= 2'b10;
outp<= 0;
end
end
2'b01: begin
if( inp ) begin
state <= 2'b00;

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outp<= 1;
end
else begin
state <= 2'b10;
outp<= 0;
end
end
2'b10: begin
if( inp ) begin
state <= 2'b01;
outp<= 0;
end
else begin
state <= 2'b00;
outp<= 1;
end
end
default: begin
state <= 2'b00;
outp<= 0;
end
endcase
end
end
endmodule

RTL SCHEMATIC:

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TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

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RESULT:

Thus the finite state machine (moore and mealy machine) were implemented.

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[Link]: 7 FPGA IMPLEMENTATION OF 4-BIT MULTIPLIER
DATE:

AIM:

To implement 4-bit multipliers using Verilog HDL.

APPARATUS REQUIRED:

1. PC with Windows XP.

2. XILINX 9.2i
3. FPGA-SPARTAN-3 KIT
4. PARALLEL TO JTAG CABLE

PROCEDURE:

1. New project and type the project name and check the top level source type as HDL
2. Enter the device properties and click Next
3. Click New Source and Select the Verilog Module and then give the file name
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it
6. Double click the synthesize XST and check syntax
7. Simulate the waveform by behavioral simulation
8. For implementation Select User constraints and give input and output port pin number
9. Click Implement design for Translate, map and place & route
10. Generate .bit file using programming file
11. Implement in FPGA through parallel-JTAG cable
12. Check the behavior of design in FPGA by giving inputs

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4 BIT MULTIPLIER:

module unsignedmult (out, a, b); Output [7:0] out;

Input [3:0] a;
Input [3:0] b;
Assign out=a*b;
end module

TRUTH TABLE:
--------------------------------------------------------
A B RES
---------------------------------------------------------
1000 1001 1000
----------------------------------------------------------

RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

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OUTPUT WAVE:

ARRAY MULTIPLIER:

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PROGRAM:

module HA (sout,cout,a,b);
input a,b;
output sout,cout;
assign sout=(a^b);
assign cout=(a&b);
endmodule
module FA (sout,cout,a,b,cin); input a,b,cin;
output sout,cout;assignsout=(a^b^cin);
assign cout=((a&b)|(b&cin)|(cin&a)); endmodule
module bitmul (m,x,y); output [7:0]m;
input [3:0]x;
input [3:0]y;
assign m[0]=(x[0]&y[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17; HA
HA1 (m[1],x1,(x[1]&y[0]),(x[0]&y[1]));
FA FA1 (x2,x3,(x[1]&y[1]),(x[0]&y[2]),x1);
FA FA2 (x4,x5,(x[1]&y[2]),(x[0]&y[3]),x3); HA HA2 (x6,x7,(x[1]&y[3]),x5);
HA HA3 (m[2],x15,x2,(x[2]&y[0]));
FA FA5 (x14,x16,x4,(x[2]&y[1]),x15);
FA FA4 (x13,x17,x6,(x[2]&y[2]),x16);
FA FA3 (x9,x8,x7,(x[2]&y[3]),x17);
HA HA4 (m[3],x12,x14,(x[3]&y[0]));
FA FA8 (m[4],x11,x13,(x[3]&y[1]),x12);
FA FA7 (m[5],x10,x9,(x[3]&y[2]),x11);
FA FA6 (m[6],m[7],x8,(x[3]&y[3]),x10);
endmodule

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RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

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OUTPUT WAVEFORM:

RESULT:

Thus 4-bit multiplier (simple and array multiplier) was implemented successfully

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[Link]: 8 FPGA IMPLEMENTATION OF MEMORIES USING
DATE: VERILOG HDL

AIM:

To design and implement FPGA based memories (Accumulator) using VHDL.

APPARATUS REQUIRED:

1. Xilinx ISE
2. Model sim simulator
3. FPGA Board-Spartan 3E
4. Personal computer (PC) with parallel to JTAG cable

THEORY:

An accumulator is a register in which intermediate arithmetic and logic results are stored.
Without a register like an accumulator, it would be necessary to write the result of each
calculation (addition, multiplication, shift, etc.) To main memory, perhaps only to be read right
back again for use in the next operation. Access to main memory is slower than access to a
register like the accumulator because the technology used for the large main memory is slower
(but cheaper) than that used for a register.
The canonical example for accumulator use is swimming a list of numbers. The
accumulator is initially set to zero, then each number in turn is read and added to the value in
the accumulator. Only when all numbers have been added is the result held in the accumulator
written to main memory or to another, non-accumulator, CPU register.

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CIRCUIT DIAGRAM:

ALGORITHM:

1. New project and type the project name and check the top level source type as HDL
2. Enter the device properties and click Next
3. Click New Source and Select the Verilog Module and then give the file name
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it
6. Double click the synthesize XST and check syntax
7. Simulate the waveform by behavioral simulation
8. For implementation Select User constraints and give input and output port pin number
9. Click Implement design for Translate, map and place & route
10. Generate .bit file using programming file
11. Implement in FPGA through parallel-JTAG cable
12. Check the behavior of design in FPGA by giving inputs
PROCEDURE:
1. The accumulator circuit is designed and the function is found out.
2. The Verilog module source for the circuit is written
3. It is implemented in Model Sim Simulator.
4. Signals are provided and output waveforms are viewed.

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PROGRAM:

Module accu(in,acc,clk,reset);
input [7:0] in;
input clk, reset;
output [7:0] acc;
reg [7:0] acc;
always@(clk)
begin
if(reset)
acc<=acc + in;
end
endmodule

OUTPUT:

RESULT:

Thus the verilog programs for memories (Accumulator) were written, synthesized,
simulated and implemented using Xilinx tools and FPGA.

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[Link]: 9 FPGA IMPLEMENTATION OF ADDERS
DATE:

AIM:

To implement adders (Simple and Ripple carry adder) using Verilog HDL.

APPARATUS REQUIRED:

1. PC with Windows XP.

2. XILINX 9.2i
3. FPGA-SPARTAN-3 KIT
4. PARALLEL TO JTAG CABLE

PROCEDURE:

1. New project and type the project name and check the top -level source type as HDL.
2. Enter the device properties and click Next.
3. Click New Source and Select the Verilog Module and then give the file name.
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it.
6. Double click the synthesize XST and check syntax.
7. Simulate the waveform by behavioral simulation.
8. For implementation Select User constraints and give input and output port pin number.
9. Click Implement design for Translate, map and place & route.
10. Generate .bit file using programming file.
11. Implement in FPGA through parallel-JTAG cable.
12. Check the behavior of design in FPGA by giving inputs

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SIMPLE ADDER:

Program:

module ad(a,b,sum);
input [7:0]a,b;
output [7:0]sum;
assign sum=a+b;
endmodule

Truth Table:
-----------------------------------------------------------------------
A B RES
------------------------------------------------------------------------
1111111 0000000 1111111

RTL SCHEMATIC:

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TECHNOLOGIC SCHEMATIC

OUTPUT WAVEFORM:

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RIPPLE CARRY ADDER:

PROGRAM:

Main program:
module sw(a, b, c, sum, carry);
input [7:0]a;
input [7:0]b;
input c;
output [7:0] sum;
output carry;
wire [6:0]c;
gk fa0(a[0],b[0],c,sum[0],c1);
gk fa1( a[1], b[1], c1, sum [1], c2);
gk fa2(a [2], b [2], c2, sum [2], c3);
gk fa3(a [3], b [3], c3, sum [3], c4);
gk fa4(a [4], b [4], c4, sum [4], c5);
gk fa5(a [5], b [5], c5, sum [5], c6);
gk fa6(a[6],b[6],c6,sum[6],c7);
gk fa7(a [7], b [7], c7, sum [7], carry);
endmodule

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Sub-Program:

module fulladd (sum, carry, a, b, c);

input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum,a,b,c);
and (w1, a,b);
and (w2, b,c,);
and (w3, c,a);
or(carry,w1,w2,w3);
endmodule

RTL SCHEMATIC:

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TECHNOLOGICAL SCHEMATIC:

OUTPUT WAVEFORM:

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RESULT:

Thus 8- bit parallel adders (simple adder and ripple carry adder) was designed and
implemented successfully.

[Link]: 10 FPGA IMPLEMENTATION OF 4-BIT ALU

DATE:

AIM:

To implement 4 Bit ALU using Verilog HDL.

APPARATUS REQUIRED:

1. PC with Windows XP.

2. XILINX 9.2i
3. FPGA-SPARTAN-3 KIT
4. PARALLEL TO JTAG CABLE

THEORY:

ALU’s comprise the combinational logic that implements logic operations such as AND,
OR, NOT gate and arithmetic operations, such as Adder, Subtractor. Functionally, the
operation of typical ALU is represented as shown in diagram below,

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PROCEDURE:
1. New project and type the project name and check the top level source type as HDL

2. Enter the device properties and click Next

3. Click New Source and Select the Verilog Module and then give the file name
4. Give the Input and Output port names and click finish.
5. Type the Verilog program and save it
6. Double click the synthesize XST and check syntax
7. Simulate the waveform by behavioral simulation
8. For implementation Select User constraints and give input and output port pin number
9. Click Implement design for Translate, map and place & route
10. Generate .bit file using programming file
11. Implement in FPGA through parallel-JTAG cable
12. Check the behavior of design in FPGA by giving inputs

PROGRAM:

4 BIT ALU:

module ALU_4_bit (a, b, operation, Result);

input [3:0] a;
input [3:0] b;
input [1:0] operation;
output [3:0] Result;
reg [3:0] Result;
always@ (a or b or operation)
begin
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 case (operation)
2'b00: Result = a & b; // AND
2'b01: Result = a | b; // OR
2'b10: Result = a + b; // addition
2'b11: Result = a - b; // subtraction
end case
end
end module

TRUTH TABLE:

Selection Input 1 Selection input 2 Operation performed

0 0 AND
0 1 OR
1 0 Addition
1 1 Subtraction

RTL SCHEMATIC:

OUTPUT WAVE:

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RESULT:

Thus 4-bit ALU was implemented and outputs are verified successfully.

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