CMOS VLSI DESIGN LABORATORY

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

Prepared by:

KORRA RAVI KUMAR

S. No Content Available Verified by
Y/N IQAC
Coordinator
1. Cover Page Y

2. Vision, Mission of the Institution Y

3. Vision, Mission of the Department Y

4. PEO’S,PSO’S and PO’S Y

DEPARTMENT OF ELECTRONICS AND COMMUNIOCATION ENGINEERING

5. Laboratory rules and regulations Y

6. List of experiments as per JNTUH Regulation Y `

7. Course Objectives and Course Outcomes Y

8. CO-PO MAPPING Y

9. Lab manuals Y

10. Viva Questions for Each Experiment Y

11. Model Question Papers Y

BASIC SIMULATION LABORATORY FILE CONTENTS:

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VISION OF THE INSTSITUTION

 To emerge as a leading educational institution by producing globally

competent professionals in service of Nation.

DEPARTMENT OF ELECTRONICS AND COMMUNIOCATION ENGINEERING

 MISSION OF THE INSTITUION

 To provide quality education by implementing state-of-the-art teaching-

learning methods for academic excellence.

 To train the students for career development and higher education with
ethical responsibility and human values.

 To inspire innovative ideas for research & development and

entrepreneurship for societal needs

VISION OF THE DEPARTMENT

 To be a Centre for excellence in the field of Electronics and

Communication Engineering to produce professional engineers.

MISSION OF THE DEPARTMENT

 To provide quality teaching-learning methodologies to make

students competitive and innovative for adapting industrial needs
and higher studies.
 To inculcate professional ethics, team spirit, and leadership qualities to
succeed in a dynamic technological world.
 To have concern for environment pertaining to Electronics and
Communication Engineering design and practice.

DEPARTMENT OF ELECTRONICS AND COMMUNIOCATION ENGINEERING

 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

PROGRAM EDUCATIONAL OBJECTIVES (PEOS)

S. No. PEOs Name Program Education Objective Statements

Students shall be competent, creative, and valued professionals in
the chosen field.
PEO-1

Establish a successful professional’s career in industry, academia,

PEO-2
and R&D organizations as an entrepreneur in a specialized field of
Electronics and Communication and allied disciplines.

Become an effective global collaborator, leading or participating to

PEO-3 address technical business, environmental, and societal
challenges.

Graduates will excel as estimable engineers with ethics, effective

4 PEO-4 communication, and leadership skills.

PROGRAM SPECIFIC OUTCOMES (PSOs)

S. No. PSOs Name Program Specific Objective Statements

Identify, analyze and provide innovative solutions to the
PSO – 1
engineering problems in the areas of communication, networking,
signal processing, VLSI, and Embedded Systems with consideration
for societal needs.

Design and develop electronics applications using Raspberry Pi,

PSO – 2
Arduino, and other advanced processors.
Apply the contextual knowledge of Electronics and Communication
PSO – 3 Engineering to design systems containing electrical, electronic
devices, software, and hardware using modern tools and
techniques.

DEPARTMENT OF ELECTRONICS AND COMMUNIOCATION ENGINEERING

 PROGRAM OUTCOMES (POS)
PO Graduate PO Statements
Name Attr
ibut
es
Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering
PO 1 Engineering knowledge specialization to the solution of complex engineering problems. [PEO’s: 1,2 and 4]
[PSO’s: 1,2 and 3]
Identify, formulate, review research literature, and analyze complex engineering problems reaching
PO 2 Problem analysis substantiated conclusions using first principles of mathematics, natural sciences, and
engineering sciences. [PEO’s: 1,2 and 4] [PSO’s: 1,2 and 3]

Design solutions for complex engineering problems and design system components or processes
PO 3 Design/ that meet the specified needs with appropriate consideration for the public health and
developm safety, and the cultural, societal, and environmental considerations. [PEO’s: 1,2 and 4]
ent of [PSO’s: 1,2 and 3]
solutions

Use research-based knowledge and research methods including design of experiments, analysis
PO 4 Conduct investigations of and interpretation of data, and synthesis of the information to provide valid conclusions.
complex problems [PEO’s: 1,2 and 4] [PSO’s: 1,2 and 3]

Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools
PO 5 Modern tool usage including prediction and modeling to complex engineering activities with an understanding
of the limitations. [PEO’s: 1,2 and 4] [PSO’s: 1,2 and 3]

Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal
PO 6 The engineer and society and cultural issues and the consequent responsibilities relevant to the professional
engineering practice. [PEO’s: 3 ]

Understand the impact of the professional engineering solutions in societal and environmental
PO 7 Environment and contexts, and demonstrate the knowledge of, and need for sustainable development.
sustainabilit [PEO’s: 3 and 4], [PSO 3]
y

Apply ethical principles and commit to professional ethics and responsibilities and norms of the
PO 8 Ethics engineering practice. [PEO’s: 3 and 4] [PSO’s: 3]

Function effectively as an individual, and as a member or leader in diverse teams, and in

PO 9 Individual and multidisciplinary settings. [PEO’s: 1,2,3 and 4] [PSO’s: 3]
team
work

Communicate effectively on complex engineering activities with the engineering community and
PO 10 Communication with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear
instructions. [PEO’s: 1,2,3 and 4] [PSO’s: 2 and 3]

KORRA RAVI KUMAR

SCCE,ECE
 Demonstrate knowledge and understanding of the engineering and management principles and
PO 11 Project apply these to one’s own work, as a member and leader in a team, to manage projects and
managemen in multidisciplinary environments. [PEO’s: 1 and 4] [PSO’s: 2 and 3]
t and
finance

Recognize the need for, and have the preparation and ability to engage in independent and life-
PO 12 Life-long learning long learning in the broadest context of technological change. [PEO’s: 1,2,3and 4] [PSO’s:
3]

LABORATORY RULES AND REGULATIONS

DO’ S AND DON’T S IN THE LAB

DO’ S:-

1) Proper dress has to be maintained while entering the lab.

2) Students should carry observation notes and record completed in all aspects.

3) Correct specifications of the equipment have to be mentioned in the circuit diagram.

4) Students should be aware of operating equipment.

5) Students should be at their concerned experiment table; unnecessary moments are restricted.

6) The student should follow the indent procedure to receive and deposit the equipment from the lab
storeroom.

7) After completing the connections, students should verify the circuits with the lab instructor.

8) The reading must be shown to the Lecturer in Charge for verification.

9) Students must ensure that all switches are in the OFF position and all the connections are removed.

10) All patch cords and stools should be placed at their original positions.

DON’ Ts:-

1) Don’t come late to the lab.

2) Don’t enter the lab with golden rings, bracelets, and bangles.

3) Don’t make or remove the connections with power ON.

KORRA RAVI KUMAR

SCCE,ECE
 4) Don’t switch on the supply without verifying by the staff member.

5) Don’t switch off the machine with load.

6) Don’t leave the lab without the permission of the lecturer in charge.

LIST OF EXPERIMENTS AS PER JNTUH REGULATION

1 1. Realize all the logic gates

2 2. Design of 8-to-3 encoder (without and with priority) and 2-to-4 decoder
3 3. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer

4 4. Design of 4 bit binary to gray code converter

5 5. Design of 4 bit comparator

6 6. Design of Full adder using 3 modeling styles
7 7. Design of flip flops: SR, D, JK, T
8 8. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter
9 9. Finite State Machine Design
10 1. Basic logic gates
11 2. CMOS inverter
12 3. CMOS NOR/ NAND gates
13 4. CMOS XOR and MUX gates
14 5. Static / Dynamic logic circuit (register cell)
15 6. Latch
16 7. Pass transistor

17 8. Layout of any combinational circuit (complex CMOS logic gate).

KORRA RAVI KUMAR

SCCE,ECE
 COURSE OBJECTIVES AND COURSE OUTCOMES

COURSE OBJECTIVES:

1 To understand the operation of Induction, Synchronous machines and Transformers.

2 To study the performance analysis of Induction and Synchronous Machines through
various testing methods..
3 To analyze the performance of single and 3-phase transformer with experiments.

COURSE OUTCOMES:

1 Assess the performance of different types of AC machines using different testing

methods
2 Analyze the suitability of AC machines and Transformers for real word applications.
3 Design the machine models based on the application requirements.

CO-PO MAPPING

Course Objectives Program Outcomes

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
To understand the 3 3 3 1 1 3 2 3 2 1 3 1
operation of Induction,
Synchronous
machines and
Transformers
To study the 3 3 3 1 1 3 2 3 1 2 3 1
performance analysis
of Induction and
Synchronous
Machines through
various testing
methods
To analyse the 3 3 3 2 1 2 1 3 1 1 3 1
performance of single
and 3-phase phase
transformer with
experiments

Course Program Outcomes

Outcomes
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
Assess the 3 3 3 2 1 3 2 1 1 1 3 2
performance of
different types of AC
machines using
different testing
methods
KORRA RAVI KUMAR
SCCE,ECE
Analyse the suitability 3 3 3 1 3 2 2 2 1 1 1 3
of AC machines and
Transformers for real
word applications
Design the machine 3 3 3 2 1 3 2 2 1 2 1 3
models based on the
application
requirements
CMOS VLSI DESIGN LABORATORY 1

CMOS VLSI DESIGN LABORATORY

MANUAL

(III-II SEMISTER)

R22-REGULATION

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 2

EXPERIMENT-1

AIM: To Design all gates using Verilog and Simulate the design.

Tools: Modelsim or Xilinx

VERILOG CODE:

module all_gates(a, b, and_out, or_out, notA_out, notB_out,nand_out, nor_out, xor_out,

xnor_out);
input a;
input b;
output and_out;
output or_out;
output notA_out;
output notB_out;
output nand_out;
output nor_out;
output xor_out;
output xnor_out;
not g1(notA_out,a);
not g2(notB_out,b);

and g3(and_out,a,b);
or g4(or_out,a,b);
nand g5(nand_out,a,b);
nor g6(nor_out,a,b);
xor g7(xor_out,a,b);
xnor g8(xnor_out,a,b);

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SCCE,ECE
endmodule

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 3

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 4

EXPERIMENT-2
AIM: To Design the 2x4 Decoder using Verilog and Simulate the design.

Tools: Modelsim or Xilinx

VERILOG CODE:

module decoder2x4(i1, i2, O0, O1, O2, O3);

input i1;
input i2;
output O0;
output O1;
output O2;
output O3;

wire not_i1,not_i2;

assign not_i1=~i1;
assign not_i2=~i2;

assign O0= not_i1 & not_i2;

assign O1= i1 & not_i2;
assign O2= not_i1 & i2;
assign O3= i1 & i2;

endmodule

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 5

EXPERIMENT-3

AIM: To Design the 4x2 encoder (with and without priority) using Verilog and Simulate the
design.

Tools: Modelsim or Xilinx

VERILOG CODE:

Without Priority:

module encoder4x2(in,reset,clock,out);
input [3:0] in;
input clock,reset;
output [1:0] out;
reg [1:0] out;
always @(posedge clock)
if (reset)
out <= 2'b00;
else
case (in)
4'b0001 : out <= 2'b00;
4'b0010 : out <= 2'b01;
4'b0100 : out <= 2'b10;
4'b1000 : out <= 2'b11;
default : out <= 2'b00;
endcase
endmodule

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 6

With Priority:

module priority_encoder4x2(in,reset,clock,out);

input [3:0] in;

input clock,reset;

output [1:0] out;

reg [1:0] out;

always @(posedge clock)

if (reset)

out <= 2'b00;

else

casex (in)

4'b0001 : out <= 2'b00;

4'b001X : out <= 2'b01;

4'b01XX : out <= 2'b10;

4'b1XXX : out <= 2'b11;

default : out <= 2'b00;

endcase

endmodule

RESULT:
Encoder

Priority Encoder

KORRA RAVI KUMAR

SCCE,ECE
KORRA RAVI KUMAR
SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 7

EXPERIMENT-4

AIM: To Design the 8x1 Multiplexer using Verilog and Simulate the design.

Tools: Modelsim or Xilinx

VERILOG CODE:

module Mux8x1(in1,in2,in3,in4,in5,in6,in7,in8,sel3,out);

input in1,in2,in3,in4,in5,in6,in7,in8;
input [2:0] sel3;
output out;

reg out;

always @(sel3,in1,in2,in3,in4,in5,in6,in7,in8)
case (sel3)
3'b000: out = in1;
3'b001: out = in2;
3'b010: out = in3;
3'b011: out = in4;
3'b100: out = in5;
3'b101: out = in6;
3'b110: out = in7;
3'b111: out = in8;
endcase

endmodule
RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 8

EXPERIMENT-5
AIM: To Design the 4-bit binary to gray code using Verilog and Simulate the Design.

Tools: Modelsim or Xilinx

VERILOG CODE:

module bin_to_gray_4bit(bin_in, gray_out);

input [3:0] bin_in;

output [3:0] gray_out;

assign gray_out[3]=bin_in[3];

assign gray_out[2]=bin_in[3]^bin_in[2];

assign gray_out[1]=bin_in[2]^bin_in[1];

assign gray_out[0]=bin_in[1]^bin_in[0];

endmodule

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 9

EXPERIMENT-6

AIM: To Design the comparator using Verilog and Simulate the design.

Tools: Modelsim or Xilinx.

VERILOG CODE:

Comparator

module comparator(A, B, Comp);

input [7:0] A;

input [7:0] B;

output Comp;

assign Comp = A >= B ? 1'b1 :

1'b0; endmodule

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 10

EXPERIMENT-7
AIM: To Design the fulladder using Verilog and Simulate the Design.

Tools: Modelsim or Xilinx

VERILOG CODE:

module fulladder(a, b, c, sum, carry);

input a;

input b;

input c;

output sum;

output carry;

assign sum = a ^ b ^ c;

assign carry = (a & b)|( b & c) | (c &

a); endmodule

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 11

EXPERIMENT-8
AIM: To Design all the SR, D, T, JK flipflops using Verilog and Simulate the Design.

Tools: Modelsim or Xilinx

VERILOG CODE:

SR Flipfloop:

module SRFF(S, R, clock, reset,Q,Qbar);

input S, reset;

input R;

input clock;

output Q,Qbar;

reg Q,Qbar;

always@(posedge clock)

if (reset)

begin

Q<=1'b0;

Qbar<=1'b1;

end else

if (S==1'b0 && R==1'b0)

begin

Q<=Q;

Qbar<=Qbar;

end else

if (S==1'b1 && R==1'b0)

begin

Q<=1'b1;
KORRA RAVI KUMAR
SCCE,ECE
Qbar<=1'b0;

end else

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 12

if (S==1'b0 && R==1'b1)

begin

Q<=1'b0;

Qbar<=1'b1;

end else

if (S==1'b1 && R==1'b1)

begin

Q<=1'bx;

Qbar<=1'bx;

end

endmodule

D Flipfloop:

module DFF(D, Q, reset, clock);

input D;
output Q;
input reset;
input clock;
reg Q;
always@(posedge clock)
if(reset)
Q<=1'b0;
else
Q<=D;
endmodule

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 13

JK Flipfloop:

module JKFF(j, k, clock, reset, Q, Qbar);

input j;
input k;
input clock;
input reset;
output Q;
output Qbar;
reg Q, Qbar;
always@(posedge clock)
if (reset)
begin
Q<=1'b0;
Qbar<=1'b1;
end else
if (j==1'b0 &&
k==1'b0) begin
Q<=Q;
Qbar<=Qbar;
end else
if (j==1'b1 &&
k==1'b0) begin
Q<=1'b1;
Qbar<=1'b0;
end else
if (j==1'b0 &&
KORRA RAVI KUMAR
SCCE,ECE
k==1'b1) begin

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 14

Q<=1'b0;
Qbar<=1'b1;
end else
if (j==1'b1 &&
k==1'b1) begin
Q<=~Q;
Qbar<=~Qbar;
end
endmodule

T Flipfloop:
module TFF(T, Q, clock, reset);

input T;

output Q;

input clock;

input reset;

reg Q;

always@(posedge clock)

if(reset)

Q<=1'b0;

else

if (!T)

Q<=Q;

else

KORRA RAVI KUMAR

SCCE,ECE
Q<=~Q;

endmodule

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 15

RESULT:

SR FlipFlop

D FlipFlop

JK FlipFlop

T FlipFlop

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 16

EXPERIMENT-9
AIM: To Design the 4-bit binary and BCD Counter using Verilog and Simulate the Design.

Tools: Modelsim or Xilinx

VERILOG CODE:

BCD Counter:

module BCD4b_syn(clock,datain, reset, load, count);

input clock;

input reset;

input load;

input [3:0] datain;

output [3:0] count;

reg [3:0] temp;

always @(posedge clock)

begin

if (reset || temp==4'b1001)

temp <= 4'b0000;

else if (load)

temp <= datain;

else

temp <= temp +

1; end

assign count = temp;

endmodule

KORRA RAVI KUMAR

SCCE,ECE
Binary Counter:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 17

module Counter4b_syn(clock,datain, reset, load, count);

input clock;

input reset;

input load;

input [3:0] datain;

output [3:0] count;

reg [3:0] temp;

always @(posedge clock)

begin

if (reset)

temp <= 0;

else if (load)

temp <= datain;

else

temp <= temp +

1; end

assign count = temp;

endmodule

KORRA RAVI KUMAR

SCCE,ECE
RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 18

BCD Counter:

Binary Counter:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 19

EXPERIMENT-10
AIM: To Design the finite state machine using Verilog and Simulate the Design.

Tools: Modelsim or Xilinx

VERILOG CODE:

module fsm1(clk, rst, out);

input clk;

input rst;

output out;

reg [1:0] state, nextstate;

parameter s0 = 2'b00;

parameter s1 = 2'b01;

parameter s2 = 2'b10;

always@(posedge clk, posedge rst)

if(rst)

state <= s0;

else

state <= nextstate;

always@(*)

case(state)

s0:nextstate <= s1;

s1:nextstate <= s2;

s2:nextstate <= s0;

default:nextstate <= s0;

endcase

KORRA RAVI KUMAR

SCCE,ECE
assign out=(state == s2);

endmodule

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 20

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 21

EXPERIMENT-11

AIM: To design and simulate the CMOS inverter and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
PROCEDURE:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 22

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

LAYOUT:

KORRA RAVI KUMAR

SCCE,ECE
RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 23

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 24

EXPERIMENT-12

AIM: To design and simulate the CMOS NAND gate and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 25

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 26

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 27

EXPERIMENT-13

AIM: To design and simulate the CMOS NOR gate and perform

LVS. TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout,

Calibre. CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 28

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 29

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 30

EXPERIMENT-14

AIM: To design and simulate the CMOS AND gate and perform

LVS. TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout,

Calibre. CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 31

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 32

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 33

EXPERIMENT-15

AIM: To design and simulate the CMOS OR gate and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 34

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 35

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 36

EXPERIMENT-16

AIM: To design and simulate the CMOS XOR gate and perform

LVS. TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout,

Calibre. CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 37

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 38

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 39

EXPERIMENT-
17

AIM: To design and simulate the CMOS XNOR gate and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
KORRA RAVI KUMAR
SCCE,ECE
 6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 40

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 41

EXPERIMENT-17

AIM: To design and simulate the CMOS MUX and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 42

LAYOUT:

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 43

EXPERIMENT-
18

AIM: To design and simulate the CMOS full adder.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 44

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 45

EXPERIMENT-19

AIM: To design and simulate the pass transistor circuit and perform LVS.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 46

LAYOUT:

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 47

RESULT:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 48

EXPERIMENT-20

AIM: To design and simulate the CMOS latch.

TOOLS: Mentor Graphics ICstudio, ICschematic, IClayout, Calibre.

CIRCUIT DIAGRAM:

KORRA RAVI KUMAR

SCCE,ECE
 CMOS VLSI DESIGN LABORATORY 49

PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Icschematic.

2. Enter into Simulation mode.
3. Setup the library.
4. Setup the required analysis.
5. Probe the required Voltages
6. Run the simulation.
7. Observe the waveforms in EZ wave.
8. Draw the layout using Iclayout.
9. Perform DRC, LVS, PEX.

RESULT:

KORRA RAVI KUMAR

SCCE,ECE