UCIe PHY Modeling

and Simulation with

XMODEL

Jaeha Kim, Jaemin Park, Juyoung Kang

Last Revision: February 15, 2025
 2

Chiplets
• A new way of building IC systems is to package
multiple dies from different sources, fabs, tech, …
• Intel mobile P packaged with AMD GPU and HBM
• To facilitate integration, each die must have standardized
interfaces – called "chiplet"

Source: [Link]
 3

Universal Chip Interconnect Express

• UCIe is one of the open industry standards defining
the interconnects between chiplets
• Supporting cost-efficient heterogenous integration
• Sustaining IC scaling without being limited by design costs

Source: D. Das Sharma, "UCIe: Building an

Open Chiplet Ecosystem," 2022.
 4

UCIe Overview
• UCIe has multiple layers: PHY, D2D, Protocol, …
• Physical layer (PHY) defines the specs for electrical signaling
(mainband/sideband), clocking, link training, etc.
• Supporting two package types: standard & advanced

Source: D. Das Sharma, "UCIe: Building an Open Chiplet Ecosystem," 2022.

 5

UCIe Cluster (Module)

• A construction unit of interconnect with:
• N single-ended, unidirectional, full-duplex data lanes
• Additional lanes for valid, tracking, differential forwarded
clock, and sideband (clock+data) signals

Source: D. Das Sharma, "UCIe: Building an Open Chiplet Ecosystem," 2022.

 6

UCIe Physical Layer (PHY)

• Electrical layer (analog) performs high-speed data trans.
• Logical layer (digital) performs calibration & training
LINK SPEED CLOCK PHASE VREF RX DESKEW
ADJUSTMENT CALIBRATION ADJUSTMENT CALIBRATION

LOGICAL LAYER
ELECTRICAL LAYER

FIFO Serializer TX Deserializer FIFO

VREF
/N DESKEW

PI TX Phase
PLL DLL + RX
TX Gen
DCC

SPEED PHASE
 7

UCIe Link Speed Training

• Mainband data rates per lane: 4, 8, 12, 16, 24, 32GT/s
• All the lower rates below the highest supported data rates
must be supported (e.g. 4, 8, 12, 16G for 16G device)
• Actual data rate is determined during link training (MBTRAIN)
• Sideband data rates: fixed with 800MHz clock
Decides on the fastest
Uses the slowest data rate data rate possible Operates using the
for initial training (4GT/s) decided data rate

RESET SBINIT MBINIT MBTRAIN LINKINIT ACTIVE

 8

Today's Webinar
• Using UCIe PHY as an example, we will show that
XMODEL is the best way to model and simulate
complex analog+digital systems in SystemVerilog
• Outlines:
• Brief introduction to XMODEL
• UCIe electrical layer modeling and simulation
• Mainband (MB) and sideband (SB) transceivers
• Analog simulations measure DC/AC transfer functions, BER, …
• UCIe logical layer modeling and simulation
• FSMs calibrating Vref, phase, skew, and link speed
• Digital verification with coverage checks
 9

Disclaimer
• We don't represent UCIe and claim ourselves to be
experts in UCIe; our understandings of the UCIe
specifications may not be accurate or fully up-to-date
• Also, our UCIe PHY models are provided "AS-IS",
without any warranties for completeness, correctness,
or merchantability
 10

XMODEL Enables Analog in SV/UVM

• A plug-in extension that enables fast and accurate
analog/mixed-signal simulation in SystemVerilog
• Event-driven: 10~100x faster than Real-Number Verilog
• Analog: supporting both functional and circuit-level models
• SystemVerilog: enabling analog verification in UVM
 11

Event-Driven Simulation of XMODEL

• XMODEL uses a unique algorithm that can trigger
much fewer events and deliver 10~100× faster speed
than Real-Number Model (RNM) or Verilog-AMS

Event Markers
 12

Expressing Analog Events

• XMODEL expresses analog signals in functional forms
instead of using a series of time-value pairs:

SPICE XMODEL

1-e-ωt -0.5+1.4e-ωt

t1 t2
Accuracy relies on fine time step Events occur only when the
coefficients are updated
 13

Propagating Analog Events

• With the signals transformed into Laplace s-domain:

• The response of a system can be computed in an

event-driven manner without time-step integration:
input low-pass filter output response

ωp

1 p 1 1
−
s p + s s  p +s
 14

Circuit-Level Modeling (CLM)

• With XMODEL’s circuit primitives, you can list the
elements of your circuit directly in SystemVerilog
module ctle (
`input_xreal inp, inn, // input signals
`output_xreal outp, outn // output signals
);
RL xreal sp, sn, vdd;

vsource #(.mode("dc"), .dc(Vdd))

V1(.pos(vdd), .neg(`ground), .in(`ground));
isource #(.mode("dc"), .dc(Ib/2))
I1(.pos(sp), .neg(`ground), .in(`ground));
I2(.pos(sn), .neg(`ground), .in(`ground));
gm nmosfet #(.Kp(Gm), .Vth(Vth))
RC M1(.d(outn), .g(inp), .s(sp), .b(`ground)),
M2(.d(outp), .g(inn), .s(sn), .b(`ground));
resistor #(.R(Rload))
RL1(.pos(vdd), .neg(outp)),
RL2(.pos(vdd), .neg(outn));
CC IB/2
capacitor #(.C(Cload))
CL1(.pos(vdd), .neg(outp)),
CL2(.pos(vdd), .neg(outn));
resistor #(.R(Rc)) RC1(.pos(sp), .neg(sn));
capacitor #(.C(Cc)) CC1(.pos(sp), .neg(sn));

endmodule
 15

Build Models with XMODEL Primitives

• You can describe your analog models just by putting
together XMODEL primitives as building blocks
• Unlike RNM, no need to be an expert in SystemVerilog
From
Analogclock to variable Digital stimuli
stimuli From variable to clock waveforms
Replaying
Type connectors with fixed Type Selection, delay,
connectors with variable
Combinational
clk_to_delay logic Sequentialdelay_to_clk
logic
Measurement
dc_gen
Probes for
levels clk_gen and buffer
Data replay_xbit
levels Probes and
Sampling,
Variable
of Measurement of
Sources
signals/proper
clk_to_duty
Functions Elements
Event triggersduty_to_clk
Filters conversion initial
selection,
inv_xbit
step_gen
bit_to_real latch_xbit
pulse_gen
xbit_to_bit elements tribuf_xbit
replay_xreal
values/properti
bit_to_real_var timing
ties conditioning
clk_to_freq
nand_xbit dff_xbit es/ comparison
freq_to_clk
and delay
triinv_xbit
exp_gen
bit_to_xbit
vsource pat_gen
xbit_to_real
resistor bit_to_xreal_var
res_var vprobe
add
probe_bit filter
trig_cross transition
meas_value sample
meas_cross
clk_to_period
nor_xbit
sin_gen period_to_clk
dff_set_sync_xbit
prbs_gen mux_xbit
bit_to_xreal
isource xbit_to_xreal
capacitor real_to_bit_var
cap_var iprobe
multiply
probe_real filter_var
trig_rise slice
meas_slope select
meas_rise
clk_to_phase
and_xbit
pwl_gen phase_to_clk
dff_set_async_xbit delay_xbit
real_to_bit
vcvs xreal_to_bit
inductor real_to_xbit_var
ind_var vinit
scale
probe_xbit filter_fir
trig_fall compare
meas_deriv delay
meas_fall
or_xbit
noise_gen
real_to_xbit dff_rst_sync_xbit
xreal_to_real buf_xbit
xbit_to_real_var
vccs
pwl_func minductor
filter_disc res_sw
dac iinit
delay_var
probe_xreal
xnor_xbit trig_edge meas_avg
dff_rst_async_xbit meas_edge
const_xbit
real_to_xreal
ccvs xreal_to_xbit
transformer xbit_to_xreal_var
cap_sw
poly_func
probe_delay integ
trig_posedge adc
meas_max buffer
meas_posedge
xor_xbit xreal_to_bit_var
cccs
sin_func diode
integ_mod ind_sw
probe_duty trig_negedge meas_min meas_negedge
switch xreal_to_xbit_var
exp_func
probe_freq deriv
trig_time meas_pp meas_time
Over 220 primitives ! limit nmosfet
probe_period meas_rms meas_delay
power pmosfet
 16

GLISTER: Build Top-Down Models

• GLISTER lets you build top-down analog models in
Cadence Virtuoso without writing codes
• Simply place the XMODEL primitives on a schematic
and connect them with wires; no coding is necessary!
 17

Top-Down Modeling with XMODEL

Describe top-down models in schematics Netlist SystemVerilog models
using GLISTER & XMODEL primitives

XMODEL Primitives

Simulate
with XMODEL
 18

Getting Started
• XMODEL Release 2025.02 or later is required
• Decompress the package file:
$ tar zxvf UCIe_model_20250215.[Link]
$ cd UCIe_model

• To view the electrical layer models in Virtuoso:

$ cd electrical
$ source etc/[Link] or etc/[Link]
$ cd cadence
$ virtuoso &
 19

UCIe Electrical Layer Architecture

• Mainband (MB) transceiver components transmitting
data, valid, track, and differential clock signals

Source: Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0, February 2022.
 20

Mainband Transmitter (MB TX)

• TX datapath serializes and drives data thru channels
• TX clockpath drives forwarded clocks with abilities to
adjust their frequency, phase, and skew

Source: Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0, February 2022.
 21

TX Clock Generation
• Generates a set of clocks for data, valid & clock drivers
• Phase-Locked Loop: generates adjustable frequency clock
• Duty-Cycle Corrector: maintains 50% duty-cycle of the clock
• Delay-Locked Loop: generates multiple clock phases

PI To Data
Drivers

8 PI To Valid
clk_ref PLL DCC DLL Drivers

N PI To Clock
Drivers

Phase Interpolators
 22

Phase-Locked Loop (PLL) Modeling

• PLL receives a 2GHz input and produces a 2~16GHz
output clock with the programmable dividing ratio (N)
• With a constant bandwidth n=2×20MHz (=ref/100)
• A lock detector flags when the PLL has settled
UCIe.PLL_top:schematic
 23

More on PLL Modeling

• PLL serves as a good example to demonstrate the
usage of various XMODEL primitives
• For details, watch the demo video "Learning XMODEL
Primitives with Phase-Locked Loop Modeling" on YouTube
Circuit primitives
Gate primitives CP VDT primitives

CKIN
PFD VCO CKOUT

÷N

Verilog Models
 24

Maintaining Constant n and 

• Want to maintain constant n and  regardless of N:

• One way is to scale the VCO gain (Kvco) with N

• For example, Kvco = N × 2GHz/V
 25

Voltage-Controlled Oscillator (VCO)

• Produces a clock whose frequency varies with voltage
• The inline primitive scales both VCO gain (Kvco) and center
frequency (f0) with N
• f = Kvco(V-V0) + f0 where Kvco=2N GHz/V, f0=2N GHz at Vo=0.5

UCIe.PLL_vco:schematic
 26

Programmable Frequency Divider

UCIe.PLL_freqdiv:xmodel
• Its dividing factor N varies
between 1 and 8 to support
the data rates of 4, 8, 12, 16,
24, and 32 GT/s
• The control code ctrl_N[3:0]
sets the value of N
• 4'b0000: N=1, 4'b0001: N=2
• 4'b0010: N=3, 4'b0011: N=4
• 4'b0100: N=6, 4'b0101: N=8
 27

PLL Lock Detector

• Asserts the output when UCIe.PLL_lockdet:xmodel
the frequency and phase of
the feedback clock stay
within 5% for 128 cycles
• A behavioral model using
clk_to_freq and clk_to_phase
primitives to check the
conditions
 28

XMODEL Testbench View

• Defines testbench settings and options for a cell
• Listing dependent cellviews & files, customizing commands, ...
• Easy to organize multiple testbenches for a given cell

All the testbenches

for the 'PLL_top' cell
are listed as its
testbench (TB) views
 29

XMODEL Testbench View (2)

• Example of UCIe.PLL_top:tb_check_lock
• Writing the testbench (tb_check_lock.sv) in the code format
• Listing the [Link] command file as a dependent file
• Customizing the plotting command for XWAVE to use [Link]

Top-level module

Dependent cellview & file

Customize command
 30

Using XMODEL Testbench Views

• Then you can run the simulation and plot results by
clicking buttons on the XMODEL Testbench Editor

Generate netlists
View netlists
Run simulation

Plot waveforms
 31

PLL Locking Transient Simulation

• Checks the locking transients and steady-state phase
and frequency of the PLL
• Testbench UCIe.PLL_top:tb_check_lock

• The input/output clock waveforms at steady states:

• All subsequent simulation results assume N=8 (16GHz output)
 32

PLL Locking Transient Simulation (2)

• Lock signal is asserted when the PLL settles at 16GHz

frequency

phase

Locked!
lock
 33

Testbench tb_meas_phasestep
• Measures the PLL's response to an input phase step
• UCIe.PLL_top:tb_meas_phasestep

input phase

output phase
 34

Testbench tb_meas_freqstep
• Measures the PLL's response to an input frequency step
• UCIe.PLL_top:tb_meas_freqstep

input frequency

output frequency
 35

Testbench tb_meas_jhist
• Measures the output clock noise at steady states and
plots its jitter histogram and phase noise
• UCIe.PLL_top:tb_meas_jhist
Jitter Histogram Phase Noise
 36

Testbench tb_meas_jtran
• Measures the PLL's jitter transfer function (JTRAN)
• UCIe.PLL_top:tb_meas_jtran
Jitter Transfer Function with N=8

DC gain at 8
(=18dB)
n at ~20MHz
 37

Testbench tb_meas_tfac
• Measures the PLL's JTRAN using probe_ac primitive
• Confirming that n and  stay constant with N
• UCIe.PLL_top:tb_meas_tfac

DC gain is
equal to N
N=8
N=4
N=2
n at ~20MHz N=1
 38

Duty-Cycle Corrector (DCC) Modeling

• A DCC is a feedback loop that maintains the duty-cycle
of the output clock at 50%
• A duty-cycle adjuster (DCA) varies the duty-cycle with Vctrl
• A charge-pump filter adjusts Vctrl if the duty-cycle is not 50%

UCIe.DCC_top:schematic
 39

Duty-Cycle Adjuster (DCA)

in

vc
in_slew

out

UCIe.DCC_dutyadj:schematic

• Adjusts the duty-cycle of the input clock by:

• First converting it into a signal with a fixed slew rate (in_slew)
• Then slicing the slew-limited signal at control voltage (vc)
 40

Slew Generator
• Generates a signal with a slew rate equal to Icp/Cint
by charging a capacitor (Cint) with a fixed current (Icp)
+0.5Vsw
• Scaling Icp = 5CintVsw fin
Icp/Cint
so that transition time
-0.5Vsw
Tslew = CintVsw/Icp Tslew is kept at 0.2Tp,in
• vlimit primitive limits
the output between
-0.5~0.5Vsw

vlimit
UCIe.DCC_slewgen:schematic
 41

Testbench tb_DCC_dutyadj
• Checks the DCA operation with a 16GHz input while
gradually varying vc from -0.5 to 0.5V
clk_gen
clk_to_duty

pwl_gen dump

UCIe.tb_DCC_dutyadj:schematic
 42

DCA Simulation Results

• Observes the duty cycle while gradually varying vc
• Testbench UCIe.DCC_dutyadj:tb_check
in
out

in_slew
vc

Duty-cycle varies between

duty-cycle 30~70% as vc changes
 43

DCC Loop Filter

• For DCC loop bandwidth (n) to scale with in, the
charge pump current has to scale with input frequency

• Scaling Icp using

clk_to_freq and
multiply primitives
• With Kdca = 40%/V
and C=1pF,
setting Icp= 40f fin
yields n=in/200

UCIe.DCC_cpfilter:schematic
 44

DCC Lock Detector

• Asserts the output when UCIe.DCC_lockdet:xmodel
the duty-cycle of the output
clock stays within 5% for
128 cycles
• A behavioral model using
clk_to_duty primitive
to check the conditions
 45

Testbench tb_check_lock
• Checks the locking transients and steady-state duty-
cycle of the output clock with clk_to_duty primitive
• At multiple operating frequencies with --sweep option

UCIe.DCC_top:tb_check_lock UCIe.tb_DCC_top:tb_check_lock
 46

DCC Locking Transient Simulation

• Confirms that the loop bandwidth scales with the
operating frequency

vctrl
2GHz Convergence is faster
with higher clock frequency
16GHz

duty-cycle Settling at 50%

 47

Testbench tb_meas_tfdc
• Measures the DC transfer function between the duty-
cycles of the input and output clocks
• Using probe_dc primitive
UCIe.DCC_top:tb_meas_tfdc UCIe.tb_DCC_top:tb_meas_tfdc
probe_dc

duty_to_clk clk_to_duty
 48

DC Transfer Function of DCC

• Confirms that DCC maintains the constant output
duty-cycle of 50% for input duty-cycle of 40~60%

DCC keeps the output duty-cycle at 50%

for input duty-cycle ranging 40~60%
and input frequency ranging 2~16GHz
 49

Testbench tb_meas_tfac
• Measures the AC transfer function between the duty-
cycles of the input and output clocks
• Using probe_ac primitive
UCIe.DCC_top:tb_meas_tfac UCIe.tb_DCC_top:tb_meas_tfac
probe_ac

duty_to_clk clk_to_duty
 50

AC Transfer Function of DCC

• DCC has the TF of a high-pass filter since it rejects low-
frequency variation in the input clock's duty-cycle
• And the cut-off bandwidth scales with the clock frequency

n ~ in /200

2GHz 8GHz
Loop bandwidth indeed
4GHz 16GHz scales with in!
 51

Delay-Locked Loop (DLL)

• A type-I DLL generates a set of 8 multi-phase clocks by
locking a 4-stage VCDL to a half clock period and
tapping true & complementary outputs of the stages
up
180° Locking the delay
dn CP
PD at T/2
Vctrl

CKIN CKOUT

Multiphase Clocks F[0] F[4] F[1] F[5] F[2] F[6] F[3] F[7]
 52

Delay-Locked Loop (DLL) Modeling

• DLL produces 8 multi-phase clocks from 2~16GHz input
• With a bandwidth that scales with input frequency (nin/50)
• A lock detector flags when the DLL has settled
UCIe.DLL_top:schematic
 53

DLL Loop Dynamics

• Type-I DLL locks its VCDL delay (Dout) to one half of the
input clock period (Tp,in)
Phase Detector Loop Filter VCDL

Tp,in/2 KPD KI/s Kvcdl Dout

• The loop bandwidth n = KPDKIKvcdl = 2IcpKvcdl/Tp,inC

• n  in/50 when Icp=100uA, C=0.4pF and Kvcdl=-250ps/V (fixed)
 54

Phase-Only Detector (PD)

• An RS-latch PD that produces equal UP & DN pulses
when the two input clocks have 180° phase difference
• The rising edge of each input clock toggles the UP/DN states
UCIe.DLL_pd:schematic
 55

DLL Loop Filter

• Adjusts the control voltage by the amount
proportional to the UP/DN pulse width differences

• To avoid false lock

problems, the control
voltage starts from the
value for the shortest
delay upon reset

UCIe.DLL_cpfilter:schematic
 56

Voltage-Controlled Delay Line (VCDL)

• A 4-stage delay line
with variable delay D:
• D = Kvcdl(V-V0)+D0
• Max. & min. limits on D
UCIe.DLL_delayunit:schematic

UCIe.DLL_vcdl:schematic
 57

DLL Lock Detector

• Asserts the output when UCIe.DLL_lockdet:xmodel
the VCDL delay stays
within 5% of Tp,in/2 for
128 cycles
• A behavioral model using
clk_to_period and
clk_to_delay primitives
to check the conditions
 58

DLL Locking Transient Simulation

• Checks the DLL's locking transients and steady-states
• Testbench UCIe.DLL_top:tb_check_lock

vctrl

2GHz
delay
4GHz
8GHz
16GHz
lock Locked!
 59

DLL Locking Transient Simulation (2)

• DLL produces 8 multiphase clocks at steady states
• The waveforms of clk_out[0] ~ clk_out[7] at 16GHz
 60

Delay Transfer Function

• Measures the DLL's Tp,in-to-Dout transfer function
• Confirming the loop bandwidth scales with the input frequency
• Testbench UCIe.DLL_top:tb_meas_tfac

n ~ in /50

2GHz 8GHz
4GHz 16GHz
 61

Phase Interpolator (PI) Stage

• Produces a clock with UCIe.PI_top:schematic

digitally-adjustable phase
• By selecting two from 8
multiphase clocks and
• Interpolating between the two
• A digital encoder controls the
selection & interp. weights
based on ctrl[5:0]
• Find more details from the
XMODEL High-Speed I/O
Interface Tutorial
 62

Phase DAC Modeling

• interp_var_xbit primitive UCIe.PI_phdac:schematic

interpolates between
ck_e & ck_o
• Its delay must be greater
than the spacing between
the two input clocks

• To support a frequency
range of 2~16GHz, this
delay is made to scale
with the clock period
Producing delay value  Tp,in
 63

Phase MUX with Enable

• Phase MUX supports clock gating to save power
• The enable (en) input's falling edge is retimed by the falling
edge of the PI's output clock while its rising edge is not (why?)
UCIe.PI_mux:schematic

en

clk

en_sync

To avoid altering To avoid

PI's output clock the pulse width dead-lock
 64

Check for Phase Rotation

• Checks whether PI can support infinite phase range
as the phase control rotates through 0~63
• Testbench UCIe.PI_top:tb_check freq_in = 16GHz

decrementing
ctrl[5:0]

incrementing

phase
The output phase keeps
changing without bounds!
 65

Check for Phase Rotation (2)

• Due to the adaptive control of the PI stage delay, the
model works equally well for the input frequency of
2~16GHz freq_in = 2GHz

decrementing
ctrl[5:0]

incrementing

phase
The output phase keeps
changing without bounds!
 66

TX Clock Control
• TX clockpath produces clocks for the TX drivers
• Adjustable-phase clocks for TX data and valid drivers
• Fixed-phase clocks for TX clock/track drivers
Synchronizing
Clock Buffers
PI To Data
Drivers

variable
8 PI To Valid
clk_ref PLL DCC DLL Drivers

variable en_sync
N To Clock
PI
Drivers

fixed ctrl_txclk
 67

TX Clock Control Model

UCIe.TX_clkgen:schematic deskewer

PI To valid
drivers

Variable

DCC DLL To data

PI
drivers

Variable

PI To clock
drivers
Synchronizing
Fixed (=63) Clock Buffers
 68

Need for Synchronizing Clock Buffers

• When PI code varies from 0 to 63, we'd like the clock
phase to increase monotonically
• This can be achieved by enabling the clock for data & valid
after enabling the clock for clock when a new frame starts
Clk for
Clock Driver

PI=0
PI=35

PI=1
PI=36
Clk for
..., 61, 62, 63 0, 1, 2, ...
Data Driver
PI=33
PI=62

PI=63
PI=34
 69

Clock Gating Buffer

• A clock gating buffer with enable input
• Enable signal (en) is synchronized with the input clock's falling
edge so that gating doesn't alter the clock's pulse width

UCIe.CLK_clkbuf:schematic
 70

Synchronizing Clock Gate Buffers

• To make clock phase vary
clk_txvp
monotonically as PI code
varies from 0 to 63
• The clock gating buffers for
data & valid are enabled by
clk_txdp
the retimed enable signal
(en_sync) of the clock gating
buffer for clock en_sync

clk_txcp

UCIe.TX_clkgen:schematic
 71

Testbench tb_check
• Checks the phases of clk_txcp & clk_txdp while varying
the PI code from 0 to 63

clk_txcp
ctrl_pi = 0
clk_txdp
ctrl_pi = 8
ctrl_pi = 16
ctrl_pi = 24
ctrl_pi = 32
ctrl_pi = 40
ctrl_pi = 48
ctrl_pi = 56
ctrl_pi = 63
 72

Clock Deskewer
• Digitally adjusts the input-to-output delay of a clock
• A 5-bit DCDL modeled with dac and delay_to_clk primitives

UCIe.CLK_deskew:schematic
 73

Testbench tb_meas_tfdc
• Measures the Dctrl vs.
delay DC transfer of
the clock deskewer
• Using probe_dc primitive
• UCIe.CLK_deskew:
tb_meas_tfdc

• Results confirm the delay

range of 0~48ps for Dctrl of
0~63
 74

TX Datapath
• TX datapath serializes and drives data thru channels
• With FIFO, serializers, and driver stages

Source: Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0, February 2022.
 75

TX Serializer Stages
• A tree-type serializer that performs 4:1, 8:1 & 16:1
serialization by cascading basic 2:1 serializer stages
• More details in the XMODEL High-Speed I/O Interface Tutorial

UCIe.SER_ser2to1:schematic UCIe.SER_ser4to1:schematic
 76

TX Serializer Stages (2)

• Each serializer stage requires a clock with 1/2
frequency of the clock used in the next stage

UCIe.SER_ser8to1:schematic UCIe.SER_ser16to1:schematic
 77

Clock Frequency Dividers

UCIe.CLK_freqdiv8:schematic

• Clocks with fin/2, fin/4, fin/8

can be produced with a
series of divide-by-2 stages
• i.e. toggle flip-flops

UCIe.CLK_freqdiv2:schematic
 78

Testbench tb_SER_ser16to1
• Checks the functionality of the 16:1 serializer by
measuring the BER of the serialized data stream
Checking the BER of the
serialized data stream
prbs_gen meas_ber

Feeding 16 parallel
PRBS data streams

UCIe.tb_SER_ser16to1:schematic
 79

Simulation Results
• Zero BER confirms that the serializer works correctly
 80

1-tap TX FIR Equalizer

• 1-tap TX FFE is realized by driving some of the unit
drivers with D[n-1] instead of D[n]
D[n] Chooses between D[n]
and D[n-1] based on
sel_post value
D[n-1]

UCIe.tb_SER_ser2to1_fir:schematic
 81

Operation with sel_post = 0

• Operates as a normal 2:1 serializer, driving the output
with retimed in0 when clk=0 and in1 when clk=1

in0 D0 D2 D4

in1 D1 D3 D5

clk

out · · D0 D1 D2 D3
 82

Operation with sel_post = 1

• Applies 1-UI delay and inversion to the data stream
• Driving with "delayed" in1 when clk=0 and in0 when clk=1
• Adding inverters to flip the polarities

in0 D0 D2 D4

in1 D1 D3 D5

clk

out · · · D0 D1 D2
 83

Testbench tb_SER_ser16to1_fir
• Compares two outputs with sel_post=0 and 1
• out[0] with sel_post = 1 (selecting 1-bit delayed & inverted data)
• out[1] with sel_post = 0 (selecting present data)
• Testbench UCIe.tb_SER_ser16to1_fir:schematic

• Simulation results:
out[0]

out[1]
 84

16:1 Serializing TX with 1-tap FFE

• To realize an adjustable 1-tap TX FFE, 3 out of 16
segmented drivers can select between D[n] and D[n-1]
• ctrl_ffe[1:0] supports de-emphasis of 0, -1.09, -2.33, -3.78 dB

To 16 segmented
TX drivers
D[n] or D[n-1]

D[n] only

UCIe.SER_ser16to1_fir:schematic
 85

Transmitter (TX) Unit Driver

• Voltage-mode push-pull driver with enable signal
• Unit driver cells with two sizes: x1 and x8

Rout = Rs Rout = Rs/8

UCIe:TX_drvunit.schematic UCIe:TX_ drvunit_x8.schematic

 86

Transmitter (TX) Driver

• Made of eight x8 and eight
x1 unit drivers D[n] or D[n-1]

• Output impedance (Rout) is TX_ drvunit_x8

adjustable between
28.3~31.9 by controlling
the number x1 units D[n] only
enabled (ctrl_rout[2:0])
TX_ drvunit
• FFE tap value is controlled
by the number of x8 units
driving D[n-1] (ctrl_ffe[1:0])
UCIe:TX_drv.schematic
 87

TX Datapath Model
• Combining the 16:1 serializer with FFE control and the
TX driver stages

UCIe.TX_datapath:schematic
 88

Testbench tb_check_clkpat
• Checks the functionality of TX FFE while transmitting
11110000 data pattern
• Sweeping ctrl_ffe[1:0] value from 0 to 3
• Testbench UCIe.TX_datapath:tb_check_clkpat
 89

Testbench tb_check_prbs
• Checks the functionality of TX FFE while transmitting
PRBS pattern
• Sweeping ctrl_ffe[1:0] value from 0 to 3
• Testbench UCIe.TX_datapath:tb_check_prbs
 90

Testbench tb_check_ber
• Checks if TX datapath can transmit PRBS data correctly
• Testbench UCIe.TX_datapath:tb_check_ber
 91

Clock & Valid Framing

• Valid signal accompanying the data signals indicates
when the data is valid

• Clocks must be gated when Valid is low for 16 UIs

 92

Clock & Valid Pattern Generation

• To support clock & valid
clock[15:0]
SER To Clock Driver
framing, they are sent
like "data"
clk_txcp
• TX_syncgen block
produces 16-bit syncgen
valid[15:0]
SER To Valid Driver
clock & valid patterns clk_pat

when data is ready

clk_txvp
r_en empty
• And the patterns
get serialized by
data[15:0]
the same serializer FIFO SER To Data Driver
clk_data
blocks
clk_txdp
 93

Adjusting Skew Between Clock & Data

• The clock vs. data/valid skew is calibrated via training
• Skew < 1UI can be calibrated by adjusting the PI code
• Skew > 1UI can be calibrated either by delaying the data/valid
bits (positive shift) or by delaying the clock pattern bits
(negative shift)
Positive Shift (e.g. +2) Negative Shift (e.g. -2)
Delaying Data/Vaild Bits
data D0 D1 D2 D3 data D0 D1 D2 D3 D4 D5

valid valid
Delaying Clock Bits
clock clock
 94

First-In First-Out (FIFO) Buffer

• Transfers data between two clock domains
(core and UCIe interface) [Link]:xmodel
• Can read and write using
dedicated enable signals
and clocks
• Flags "full" or "empty"
depending on FIFO state
d_in d_out
ctrl_shift flag_full
FIFO flag_empty
w_en r_en
w_clk r_clk

reset
 95

FIFO Read Operation with Bit Shifts

• FIFO can also perform [Link]:xmodel
bitwise shifts in the read-
out bits (positive shifts)
15 0

r_ptr

r_ptr+1

shift
15 3

r_ptr 000
2 0 15 3

r_ptr+1
 96

Clock & Valid Pattern Synchronizer

• TX_syncgen block produces clock & valid pattern:
• 10101010… for the clock and 11110000… for the valid
• Also supporting bitwise bitwise shifts in the patterns
shift_valid = +5 [15:0]

valid 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
5 shifts

clock 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

shift_valid = -5 [15:0]

valid 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0

clock 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
-5 shifts
 97

Top-Level Transmitter Model

• Combining clock/data generation & driver blocks
UCIe.MB_tx_x1:schematic
 98

Testbench Setup for MB_tx_x1

• Generates stimuli and connects outputs with channels
UCIe.tb_MB_tx_x1:schematic
 99

Channel Model
• A transmission line channel with frequency-dependent
characteristics extracted from an S-parameter file
• Using sparam_to_tf or sparam_to_tline utilities
• Find details from XMODEL High-Speed I/O Interface Tutorial
[Link]:schematic
 100

Testbench tb_check_output
• Checks TX functionality transmitting PRBS pattern
• Testbench UCIe.MB_tx_x1:tb_check_output
 101

Testbench tb_check_output (2)

• Checks valid framing and clock postamble
8 UI 8 UI 16 UI

Clock

Nomal operation Clock postamble Gated

Valid

Data

Byte N-1 Byte N

 102

Testbench tb_meas_eye
• Measures the eye diagram of channel output signal
• TX FFE improves
the eye opening
• Testbench
UCIe.MB_tx_x1:
tb_meas_eye
 103

Receiver (RX)
• RX clockpath recovers clock
and generates quarter-rate
clocks from it
• RX datapath recovers data
and deserializes them

• Note:
• Track signal is used as clock
when the forwarded clocks
are unavailable

Source: Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0, February 2022.
 104

RX Data Path
• Made of quarter-rate sampling front-end with clock
deskewers and 4:16 deserializer

To
FIFO

UCIe.RX_datapath:schematic
 105

Quarter-Rate Receiver Frontend

• 1:4 demultiplexing receiver with quarter-rate clocks

Retiming
FF's & latches

Generates digitally
adjustable Vref

UCIe.RX_frontend:schematic Clocked comparators

 106

Rx Reference Generator
• A 4-bit DAC generating Vref ranging 0~0.625Vsw
• 30Ω of TX driver impedance and 50Ω of termination set the
nominal TX voltage swing level at 0.625Vsw
• Vref is calibrated during link training

UCIe.RX_refgen:schematic
 107

4:16 Deserializer
• A tree-type deserializer
cascading basic 1:2 stages
• Each stage is a half-rate
receiver with a retimer

UCIe.DES_des1to2:schematic UCIe.DES_des4to16:schematic
 108

RX Clock Path
• Generates a set of full-swing, quarter-rate clocks from
the clk or track signals forwarded by TX

A mux choosing clk

or track as input

UCIe.RX_clkpath:schematic
 109

Limiting Amplifiers
• Full-swing clocks are UCIe.RX_diffamp:schematic

recovered from:
• Differential forwarded
clock inputs, or
• Single-ended track
input
UCIe.RX_limitamp:schematic

• A single-ended
limiting amp needs
a reference level
 110

Quarter-Rate Clock Generator

• A divide-by-2 frequency divider generating 0, 90, 180,
270° phase clocks

UCIe.RX_phasegen:schematic
 111

Top-Level Receiver Model

UCIe.MB_rx_x1:schematic

• Combining RX data path, clock

path, and FIFO
 112

Testbench Setup for MB_rx_x1

• Generates stimuli and connects inputs with channels
UCIe.tb_MB_rx_x1:schematic
 113

Testbench tb_meas_ber
• Checks RX functionality deserializing PRBS pattern
• Testbench UCIe.MB_rx_x1:tb_meas_ber
 114

Testbench Setup for TX & RX Pair

• Connected via a set of data, clk, valid, track channels

UCIe.tb_MB_top_x1:schematic
 115

Testbench tb_meas_ber
• Checks the correct data transmission between TX & RX
• Testbench UCIe.tb_MB_top_x1:tb_meas_ber
 116

Testbench tb_meas_eye
• Measures the eye diagram of the transmitted signal
• Testbench UCIe.tb_MB_top_x1:tb_meas_eye

w/o FFE
enabled

w/ FFE
enabled
 117

Testbench tb_meas_bathtub_tm
• Measures BER while varying PI control code over 0~63
• Testbench UCIe.tb_MB_top_x1:tb_meas_bathtub_tm

Control Value Margin Control Value Margin

of 0 ~ 19 of 32 ~ 51
~0.625UI ~0.625UI
 118

Testbench tb_meas_bathtub_vm
• Measures BER while varying Vref control code 0~15
• Testbench UCIe.tb_MB_top_x1:tb_meas_bathtub_vm

Control Value Margin

~250mV of 5 ~ 9
 119

UCIe Link Module

• Made of mainband (MB) and sideband (SB) transceivers

Source: Universal Chiplet Interconnect Express (UCIe) Specification Revision 1.0, February 2022.
 120

Sideband Transmitter (SB TX)

• Simple TX transmitting clock and data at 800MHz

UCIe:SB_tx:schematic
 121

Sideband Receiver (SB RX)

• Simple RX sampling the received data with the
forwarded clock

UCIe.SB_rx:schematic
 122

UCIe Electrical Layer Model

• Combining the MB and SB
transceivers

UCIe.UCIE_ELECTRICAL_top
UCIe.SB_top:schematic
UCIe.MB_top:schematic :schematic
 123

Pair of Two UCIe Modules

Main Band

Module1 Module2

Side Band

UCIe.UCIE_ELECTRICAL_pair:schematic
 124

UCIe Logical Layer

• UCIe logical layer performs the following functions:
• Link initialization and training
• Transmitting and receiving sideband messages
• Scrambling and training pattern generation
• Interconnect redundancy mapping
• Lane reversal
• Width degradation

• We partially implemented the link training FSM to

demonstrate the benefits of SystemVerilog modeling
with XMODEL
 125

Getting Started
• The models and testbenches for the UCIe logical layer
are located in the sub-directory "logical":
$ tar zxvf UCIe_model_20230629.[Link]
$ cd UCIe_model
$ cd logical
$ source etc/[Link] or etc/[Link]

• To run simulation, type "make runsim" within each

testbench directory:
$ cd tb/tb_MBTRAIN
$ make runsim

• Note: the options for measuring coverages assume Xcelium

 126

UCIe Physical Layer (PHY) Model

UCIE_PHY_top.sv:
• UCIe PHY model is a
combination of logical
and electrical layers

ctrl
en
rst
UCIE_PHY_top

ctrl vld
data clk
Logical Electrical
layer clock layer data
 127

UCIe Logical Layer Model

UCIE_LOGICAL_top.sv:
• Includes a subset of link
training FSM (LTFSM)
and LFSR pattern
generator/validator
ctrl
en
rst

UCIE_LOGICAL_top

rst rst
LFSR LTFSM LFSR dout
din en en
Pattern Pattern vldout
Generator done done Comparator
 128

LTFSM RTL Model Structure

• Modeled as a hierarchical Link Training FSM

RESET

finite-state machine (FSM)

• i.e. a modular/nested structure SBINIT
Enable
SBINIT
FSM
Done
of multiple sub-FSMs MBINIT FSM
Enable

• All FSMs are written in MBINIT

Done PARAM
Enable
PARAM
FSM
Done
consistent styles for easy reading
Enable
Cal
Cal
FSM
Done
RESET VALVREF DATATRAIN
SBINIT DATAVREF CENTER1 ACTIVE

Enable Enable
MBINIT SPEEDIDLE DATATRAIN Repair Repair
Link
Training
LTFSM MBTRAIN TXSELFCAL VREF CLK
Done
FSM
Done basic

LINKINIT RXCLKCAL RXDESKEW

ACTIVE VALTRAIN DATATRAIN
PHYRETRAIN CENTER CENTER2
L1 VALTRAIN LINKSPEED
L2 VREF REPAIR Done

TRAINERROR
 129

TX-Initiated Point Training

• A sequence of data transmission test initiated by the
TX of the main module:
1. Exchange SB messages to start the point training
2. Reset LFSR pattern generator and comparator
3. Send patterns via MB
4. Request the partner's log of comparison results
Pattern
Main Module1 Module2 Partner

MB
FSM TX RX FSM
SB

Result
 130

RX-Initiated Point Training

• A sequence of data transmission test initiated by the
TX of the main module:
1. Exchange SB messages to start the point training
2. Reset LFSR pattern generator and comparator
3. Partner starts sending patterns via MB
4. Collect the log of comparison results
Pattern
Main Module1 Module2 Partner

MB
FSM RX TX FSM
SB

Request
 131

Top-Level LTFSM Model

• Made of a sequence of states (INIT, RESET, SBINIT, …)
• Each state activates a sub-FSM by asserting enable
signal (en) and waits until it returns done signal (done)
 132

Mainband (MB) Training

• Performs a set of calibrations using a set of TX- or RX-
initiated point trainings
• VALVREF, DATAVREF: finds the optimal Vref control code
• SPEEDIDLE: initializes or adjusts the data rate
• VALTRAIN_CENTER: finds the optimal PI code for valid TX
• VALTRAIN_VREF: calibrates valid Vref control code again
• DATATRAIN_CENTER1: finds the optimal PI code for TX
• DATATRAIN_VREF: calibrates Vref control code again
• RXDESKEW: adjusts the data-to-clock skew of RX
• DATATRAIN_CENTER2: calibrates PI code again
• LINKSPEED: checks the operation at current data rate
 133

MB Training State Diagram

Repair
Speed downshift

SPEED
INIT VALVREF DATAVREF TXSELFCAL
IDLE

DATATRAIN VALTRAIN VALTRAIN

RXCLKCAL
CENTER1 VREF CENTER

DATATRAIN DATATRAIN
RXDESKEW LINKSPEED
VREF CENTER2
 134

Finding the Optimal Vref

• Goal is to find the center of the passing window of the
control code within min~max
BER
Test

PASS
Fail Fail

Control
min bdry0 center bdry1 max Code

Find the center of

the passing range
 135

Optimal Vref Search Algorithm

• *_VREF FSMs find the optimal Vref code in two steps:
1. Find the lower bound (bdry0) by performing point tests
starting at min until a passing point is found
2. Find the upper bound (bdry1) by performing point tests
starting at max until a passing point is found
3. The optimal Vref control code is (bdry0 + bdry1) / 2
BER ① ②
Test

PASS
Fail Fail

Control
min bdry0 center bdry1 max Code
 136

DATAVREF Waveforms
• Finds the optimal ctrl_vref via two search steps

Optimal ctrl_vref

Exchanges Exchanges
SB messages SB messages

Runs the RX point tests

 137

DATAVREF Waveforms (2)

• Each trial performing a RX-initiated point test
Runs the RX point test

Exchanges Exchanges
SB messages SB messages

Vref voltage
 138

Checking FSM Coverages

meas_txpoint.sv:
• We can use SystemVerilog's
coverage features to check:
• Whether all states are visited
• Whether all state transitions are
For all FSMs
exercised
• For reusability, the checkers
For main FSM
are defined in separate
modules (using "bind") For partner FSM

design coverage checking

instance name module name
tb_txpoint.sv:
 139

DATAVREF Coverages
• All the bins for states and transitions are covered
 140

Finding the Optimal Center Timing

• Timing offset between the clock and data/valid is
adjustable with FIFO shift (-32~+31) and PI code (0~63)
• Goal is to find the center of the opening yielding BER=0

shift = -2 shift = 0 shift = +2

PI PI PI
0 63 0 63 0 63

2 UI
Find the center of this opening
 141

Coarse-Fine Search Algorithm

• *_CENTER FSMs find the optimal center in two steps:
1. Coarse search (FSM_coarse.sv): performs point tests at PI=8
increments to find the passing range → min_c~max_c
2. Fine search (FSM_search.sv): performs point tests at PI=1
increments within min_c-7 ~ max_c+7 to find the passing
range → min_f~max_f
3. Center is (min_f+max_f)/2
8 -7 +7

PASS

min_c max_c
min_c-7 max_c+7
 142

DATATRAIN_CENTER Waveforms
• Finds the optimal center via coarse & fine searches

Coarse Search Fine Search

 143

DATATRAIN_CENTER Waveforms (2)

• Each trial performing TX-initiated point test
• The optimal center is found once the search is done

Runs the TX point test

PI & shift
values for
optimal center
 144

DATATRAIN_CENTER Coverages
• All the bins for states and transitions are covered
 145

RXDESKEW FSM
• Calibrates the per-lane skews to further improve the
timing margins
• Can use the same search algorithm with Vref training
• All the lanes can be calibrated individually at the same time
Dout[0]
data[0] lane0

clk[3:0]

ctrl_rxdeskew[5:0]

Dout[1]
data[1] lane1

clk[3:0]

ctrl_rxdeskew[11:6]
 146

RXDESKEW Waveforms
• The skews of all the lanes are calibrated simultaneously

Delay for
lane0

Delay for
lane4

Delay for
lane8

Delay for
lane12
 147

RXDESKEW Coverages
• All the bins for states and transitions are covered
 148

Testbench tb_MBTRAIN
• Checks the operation of MBTRAIN FSM
• Simulation ends when the LTFSM enters the ACTIVE state
after MBTRAIN is finished
• Measures the state & transition coverages of the FSMs
by binding the coverage measuring modules
tb_MBTRAIN.sv:

Binding the coverage

modules
 149

Cross-Coverage Checks
meas_MBTRAIN.sv:
• To make sure all the states
and transitions are covered
at each data rate
• By defining cross-coverage
between states & data rates
meas_DATATRAIN_CENTER.sv:
 150

Initial Coverage Results

• Link training completed successfully, but…

• The coverages of all FSMs didn't reach 100% (1h 27m)

• Because the training was finished without speed downshifts
 151

Improved Coverage Results

• To improve coverage, we increased the channel loss
with an extra filter primitive
tb_MBTRAIN_noise.sv:

• And the coverage reached 100%! (6h 30m runtime)

 152

Coverage Graph

Reached 100%
 153

Testbench tb_eyevref
• Plots the eye diagrams before and after Vref training

Before training:
ctrl_vref = 0

vref: ~0mV
After training:
ctrl_vref = 7

vref: 350mV
 154

Testbench tb_eyepi
• Plots the eye diagrams before and after PI training

Before training:
ctrl_pi = 0

After training:
ctrl_pi = 41

Rising edge of the RX clock

 155

Testbench tb_lockvref
• Measures the trained Vref value while varying the
deliberate voltage offset applied to the received data

Increasing voltage offset

 156

Testbench tb_lockpi
• Measures the trained PI code and UI shift value while
varying the clock-to-data delay offset
 157

Testbench tb_bathtub_tm
• Checking the timing margin after the calibration

Timing Margin of
~0.6UIpp
 158

Testbench tb_bathtub_vm
• Checking the voltage margin after the calibration

Voltage Margin
of ~225mVpp
 159

Summary
• Presented SystemVerilog models of UCIe PHY
• Electrical layer: analog circuits are modeled with XMODEL
• Logical layer: digital FSMs are modeled in Verilog RTL

• XMODEL enables fast and accurate simulation of

complex analog+digital systems in SystemVerilog
• Offers a unified platform to combine analog and digital
simulation techniques for thorough validation
• Analog: AC/DC transfer functions, statistical BER analysis, …
• Digital: coverage & assertion checks, random directed test, …
 160

To Learn More
• To learn more about XMODEL,
visit Scientific Analog's website:
[Link]

• And check out these resources:

• Videos: [Link]/saflix
• Webinars: [Link]/webinars
• Newsletters: [Link]/avm
• Online demos: [Link]/glister_demo &
modelzen_demo
 161

Appendices
• Measuring Coverage with Cadence Xcelium
• Measuring Coverage with Synopsys VCS
 162

Xcelium: Generating Coverage Data

• To generate coverage data, add the -coverage option
with the desired coverage types
• For example, b:e:f:u means block, expression, FSM and
functional coverages
xmodel <other options> --elab-option -coverage b:e:f:u --

• By default, a directory named cov_work will be created

• Use the following commands to generate report:
imc -batch
imc> load -run ./cov_work/scope/test
imc> report -detail -metrics functional -all -inst *... \
-out [Link]
imc> exit
 163

Xcelium Coverage Report Example

...
Instance name: tb_TXpoint.[Link].FSM2.cov_main Coverage of main FSM
Type name: meas_txpoint
File name: /users/jaemin/projects/ucie/logical/meas_covs/meas_txpoint.sv
Number of covered cover bins: 27 of 27
Number of uncovered cover bins: 0 of 27 No uncovered bins
Number of excluded cover bins: 0

Name Average, Covered Grade Line Source Code

---------------------------------------------------------------------------------------------------
cg_inst 100.00%, 100.00% (27/27) 13 covergroup cg @(posedge clk);
|--cp_common 100.00% (22/22) 17 coverpoint STATE'(state) {
| |--states[INIT] 100.00% (1980/1) 18 bins states[] = ...
...
| |--transitions[INIT=>SENDMSG] 100.00% (1/1) 19 bins transitions[] = ...
...
Instance name: tb_TXpoint.[Link].FSM2.cov_partner Coverage of partner FSM
Type name: meas_txpoint
File name: /users/jaemin/projects/ucie/logical/meas_covs/meas_txpoint.sv
Number of covered cover bins: 23 of 23
Number of uncovered cover bins: 0 of 23 No uncovered bins
Number of excluded cover bins: 0
Name Average, Covered Grade Line Source Code
---------------------------------------------------------------------------------------------------
cg_inst_partner 100.00%, 100.00% (23/23) 13 covergroup cg_partner @(posedge clk);
|--cp_common 100.00% (22/22) 17 coverpoint STATE'(state) {
...
 164

Xcelium Coverage Report Example (2)

• You can also browse the coverage reports in GUI mode
imc -gui -load ./cov_work/scope/test

② Click

① Click
 165

VCS: Generating Coverage Data

• To generate coverage data, add the -cm option with
the desired coverage types
• For example, line+cond+fsm means line, condition, and FSM
coverages
xmodel <other options> --elab-option -cm line+cond+fsm -- \
--sim-option -cm line+cond+fsm --

• By default, coverage data is written to a directory

named [Link]
• Use the following commands to generate text report:
urg -dir [Link] -format text
more urgReport/[Link]
 166

VCS Coverage Report Example

===============================================================================
Group Instance : cg_inst
===============================================================================
SCORE WEIGHT GOAL AT LEAST AUTO BIN MAX PRINT MISSING
100.00 1 100 1 64 64

Group:

SCORE INSTANCES WEIGHT GOAL AT LEAST PER INSTANCE AUTO BIN MAX PRINT MISSING COMMENT NAME
66.67 100.00 1 100 1 1 64 64 tb_txpo
[Link].FSM2.cov_main::cg Coverage of main FSM
-------------------------------------------------------------------------------

Summary for Group Instance cg_inst

CATEGORY EXPECTED UNCOVERED COVERED PERCENT

Variables 28 1 27 100.00 No uncovered bins
Variables for Group Instance cg_inst

VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT AT LEAST AUTO BIN MAX COMMENT
cp_common 22 0 22 100.00 100 1 1 0
cp_main 5 0 5 100.00 100 1 1 0
cp_partner 1 1 0 0.00 100 0 1 0
 167

VCS Coverage Report Example (2)

• You can also browse the coverage reports in GUI mode
urg -dir [Link]
firefox urgReport/[Link]

Click