CMOS ANALOG IC DESIGN

(R22D6803)

DIGITAL NOTES
[Link]
(I YEAR – I SEM)
(2023-24)

Department of Electronics and Communication Engineering

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)
Recognized under 2(f) and 12 (B) of UGC ACT 1956
(Affiliated to JNTUH, Hyderabad, Approved by AICTE - Accredited by NBA & NAAC – ‘A’ Grade - ISO 9001:2015 Certified)
Maisammaguda, Dhulapally (Post Via. Kompally), Secunderabad – 500100, Telangana State, India
 ELECTIVE-I
CMOS ANALOG IC DESIGN
Course Objectives:
 To provide in-depth understanding of different types of MOS devices and modeling
techniques
 To understand and design the operation of current mirror circuits
 To demonstrate the analysis and design of amplifiers using CMOS
 To design a various stages of Operational amplifiers using CMOS devices.
 Design and construct the open loop and discrete time comparators using op-amp.

UNIT –I

MOS Devices and Modeling:

The MOS Transistor, Passive Components- Capacitor & Resistor, Integrated circuit Layout,
CMOSDevice Modeling - Simple MOS Large-Signal Model, Other Model Parameters, Small-Signal
Model forthe MOS Transistor, Computer Simulation Models, Sub-threshold MOS Model.

UNIT –II

Analog CMOS Sub-Circuits:

MOS Switch, MOS Diode, MOS Active Resistor, Current Sinks and Sources, Current Mirrors-
Currentmirror with Beta Helper, Degeneration, Cascode current Mirror and Wilson Current Mirror,
Current andVoltage References, Band gap Reference.

UNIT –III

CMOS Amplifiers

Inverters, Differential Amplifiers, Cascode Amplifiers, Current Amplifiers, Output Amplifiers, High
Gain Amplifiers Architectures.

UNIT –IV

CMOS Operational Amplifiers

Design of CMOS Op Amps, Compensation of Op Amps, Design of Two-Stage Op Amps, Power-Supply

Rejection Ratio of Two-Stage Op Amps, Cascode Op Amps, Measurement Techniques of OPAmp.

UNIT –V
Comparators
Characterization of Comparator, Two-Stage, Open-Loop Comparators, Other Open-Loop
Comparators, Improving the Performance of Open-Loop Comparators, Discrete-Time Comparators.
TEXT BOOKS:

1. CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University
Press, International Second Edition/Indian Edition, 2010.
2. Analysis and Design of Analog Integrated Circuits- Paul R. Gray, Paul J. Hurst, S. Lewis and
R. G. Meyer, Wiley India, Fifth Edition, 2010.

REFERENCE BOOKS:

1. Analog Integrated Circuit Design- David A. Johns, Ken Martin, Wiley Student Edn, 2013.
2. Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition.
3. CMOS: Circuit Design, Layout and Simulation- Baker, Li

Course Outcomes:
 Model various components in CMOS process to estimate their performance in circuits.
 Analyze and design of MOS and different current mirror circuits including Wilson, cascode
current mirror.
 Design of CMOS Amplifiers including Differential, Cascode and high gain amplifier
architectures.
 Design of CMOS Operational amplifiers and to measure the characteristics of cascode
operational-amplifier.
 Apply and analyze the performance of open loop and discrete time capacitor circuits
 UNIT -I
MOS Devices and Modeling

MOS Transistor:

A MOS transistor is primarily a switch for digital devices. Ideally, it works as follows:
If the voltage at the gate electrode is "on" , the transistor is "on", too, and current flow between
the source and drain electrodes is possible (almost) without losses.
If the voltage at the gate electrode is "off", the transistor is "off", too, and no current flows
between the source and drain electrode.

The most basic element in the design of a large scale integrated circuit is the transistor. For the
processes this type of transistor available is the Metal-Oxide-Semiconductor Field Effect
Transistor (MOSFET). These transistors are formed as a ``sandwich'' consisting of a
semiconductor layer, usually a slice, or wafer, from a single crystal of silicon; a layer of silicon
dioxide (the oxide) and a layer of metal. These layers are patterned in a manner which permits
transistors to be formed in the semiconductor material (the ``substrate''); a diagram showing a
typical (idealized) MOSFET is shown in Figure . Silicon dioxide is a very good insulator, so a
very thin layer, typically only a few hundred molecules thick, is required. Actually, the
transistors which we will use do not use metal for their gate regions, but instead use
polycrystalline silicon (poly). Polysilicon gate FET's have replaced virtually all of the older
devices using metal gates in large scale integrated circuits. (Both metal and polysilicon FET's are
sometimes referred to as IGFET's --- insulated gate field effect transistors, since the silicon
dioxide under the gate is an insulator. We will still continue to use the term MOSFET to refer to
polysilicon gate FET's.)
Transfer Characteristics of MOS Devices:

A cross section of a typical enhancement-mode n-channel MOS (NMOS) transistor is shown in

Fig.

Heavily doped n-type source and drain regions are fabricated in a p-type substrate (often called
the body).A thin layer of silicon dioxide is grown over the substrate material and a conductive
gate material (metal or polycrystalline silicon) covers the oxide between source and drain. Note
that the gate is horizontal in Fig., and we will use this orientation in all descriptions of the
physical operation of MOS devices. In operation, the gate-source voltage modifies the
conductance of the region under the gate, allowing the gate voltage to control the current flowing
between the source and drain. This control can be used to provide gain in analog circuits and
switching characteristics in digital circuits.
Passive Components- Capacitor & Resistor:
Integrated circuit Layout:
Y path technique
CMOS Device Modeling:

Simple MOS Large-Signal Model:

Other Model Parameters:
Computer Simulation Models:
Sub-threshold MOS Model:
Sub-threshold MOS Model:
 UNIT -II:
Analog CMOS Sub-Circuits

MOS SWITCH:
MOS DIODE/ACTIVE RESISTOR:
Current Sinks and Sources:
Current Mirrors-Current mirror with Beta Helper
Cascode current Mirror and Wilson Current Mirror
Current and Voltage References:
Band gap Reference:
 UNIT -III:
CMOS Amplifiers

Inverters & Differential Amplifiers:

Differential Amplifiers:
Cascode Amplifiers :
Current Amplifiers:
Output Amplifiers:
High Gain Amplifiers Architectures:
 UNIT -IV:
CMOS Operational Amplifiers

Design of CMOS Op Amps:

Compensation of Op Amps:
Design of Two Stage Op Amps:
Power-Supply Rejection Ratio of Two-Stage Op Amps:
Cascode Op Amps:.
Measurement Techniques of OP Amp.:
 UNIT -V
Comparators
Characterization of Comparator:
Design of Two stage Comparator:
Improving the Performance of Open-Loop Comparators:
Comparator with hysteresis:
Discrete-Time Comparators:
 Tutorial Problems

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MALLA REDDY COLLEGE OF ENGINEERING AND TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
DEPARTMENT OF ECE
CMOS Analog Integrated Circuit Design

Hand outs-Unit1-5
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
[Link] (VLSI &ES) (2019-21 Batch)
ROLL LIST

[Link] HALL TICKET NUMBER NAME OF THE STUDENT

1 19N31D6801 ADEPU HARI PRIYA
2 19N31D6802 ALGAPALLY SANTOSH SAGAR
3 19N31D6803 BADDAM SINDHU REDDY
4 19N31D6804 BANGARIGALLA SHEKARBABU
5 19N31D6805 CHIPPA PRITHVIRAJ
6 19N31D6806 DANAVATH NAGAMMA
7 19N31D6807 DEETI ADIKYA
8 19N31D6808 DOKKU VARA LAKSHMI
9 19N31D6809 GADHARI KEERTHANA
10 19N31D6810 GEDDADA SANDEEP VARMA
11 19N31D6811 KATTA VIDUSHEE KUMARI VISHWA KARMA
12 19N31D6812 KODE SASIKALA
13 19N31D6813 KUNDETI MAMATHA
14 19N31D6814 NAGANABOINA SUMAN
15 19N31D6815 POLAPALLI MANASA
16 19N31D6816 POLAPALLI SRIKANTH
17 19N31D6817 SAIKUMAR KURAKULA
18 19N31D6818 SANDEEP BALLEM
19 19N31D6819 SIDDA MANOJ KUMAR REDDY
20 19N31D6820 SUNKARI JASNAVI
21 19N31D6821 TALLURI SAI PRIYANKA
22 19N31D6822 TALLURI VENKATA RESHMA
23 19N31D6823 VENKATREDDY GARI PRATHAP REDDY
24 19N31D6824 VUTUKURI ANUSHA
 [Link] (VLSI &ES) (2019-21 Batch)
Internal Exam Evaluation
HALL TICKET
[Link] NO MID-I MID-II AVERAGE

1 19N31D6801 26 12 19

2 19N31D6802 27 26 26.5

3 19N31D6803 12 26 19

4 19N31D6804 12 21 16.5

5 19N31D6805 21 26 23.5

6 19N31D6806 26 26 26

7 19N31D6807 26 22 24

8 19N31D6808 26 25 25.5

9 19N31D6809 26 26 26

10 19N31D6810 26 24 25

11 19N31D6811 25 25 25

12 19N31D6812 29 26 27.5

13 19N31D6813 27 24 25.5

14 19N31D6814 24 21 22.5

15 19N31D6815 20 22 21

16 19N31D6816 26 26 26

17 19N31D6817 24 18 21

18 19N31D6818 24 20 22

19 19N31D6819 20 19 19.5

20 19N31D6820 28 27 27.5

21 19N31D6821 19 22 20.5

22 19N31D6822 12 23 17.5

23 19N31D6823 21 12 16.5

24 19N31D6824 21 20 20.5
 End/Mid Questions

UNIT-I
MOS DEVICES AND MODELING

[Link] about the Passive Components of the MOS transistor.

[Link] about the CMOS device Modeling.
[Link] the Large-signal model for the MOS Transistor.
[Link] the small-signal model for the MOS transistor. Briefly explain each component
[Link] about the computer simulation models.

UNIT-II ANALOG CMOS SUB CIRCUITS

1. Write short notes on current sinks and sources.
2. What is Current Mirror? Explain the general properties of current mirrors with
block diagram.
3. Explain the cascode current mirror and Wilson current mirror using bipolar and MOS
devices.
4. Explain the following:
i) Simplest form of Current Mirror in Bipolar and MOS
ii) Simplest form of Current Mirror with beta helper in Bipolar and MOS
iii) Simplest form of Current Mirror with degeneration in Bipolar and MOS

UNIT III CMOS AMPLIFIERS

1. Draw and explain the small signal frequency response of the active resistor load
inverter.
2. Briefly explain the differential amplifiers. With necessary equation give
the large signal analysis of CMOS differential amplifiers.
3. Explain the large signal characteristics of cascode amplifier.
4. What is a current amplifier? Explain the single ended input current amplifier.
5. Write short notes on Output amplifiers.
6. Explain about high gain amplifier architectures.

UNIT IV CMOS OPERATIONAL AMPLIFIERS

1. Explain about the design of CMOS op-amps.

2. Explain about the two stage operational amplifier analysis.
3. Derive the expression for power-supply rejection ratio of Two-stage op-amps.
4. What is compensation of op amp? Explain the operation of Miller compensation.
5. Explain about the Cascode Op-amps.
6. Explain the Measurement technologies of Op-amp.
UNIT V COMPARATORS

1. What are the characterizations of comparators? Calculate the gain and propagation
delay of two stage comparator.
2. Draw and explain the two stage open loop comparator.
3. Explain the types of discrete time comparator circuit.(or)
4. Explain the following terms with neat sketch.
a) Switched capacitor comparators
b) Regenerative comparators
5. How to improve the performance of open loop comparators? Explain it.
 R15
Code No: R15D6805

MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY

(Autonomous Institution – UGC, Govt. of India)

[Link] I-Year - I Semester Supplementary Examinations, Dec-18/Jan-19

CMOS Analog Integrated Circuit Design

(VLSI&ES)

Roll No

Time: 3 hours Max. Marks: 75

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE Question from
each SECTION and each Question carries 15 marks.

*****

SECTION-I

1 (a) Explain about MOS large- signal analysis of CMOS Device Modeling [10M]
(b) Explain sub-threshold MOS model Parameters.
[5M]

OR

2 (a) Discuss about the passive components of the MOS transistor. [7M]
(b) Write about computer simulation models for MOS transistor
[8M]

SECTION-II

3 a) Explain the working of current mirror with beta helper [10M]

b) Explain the operation of MOS Diode
[5M]

OR

4 Discuss the Cascode current Mirror and Wilson Current Mirror [15M]

SECTION-III

5 (a)Explain about working of differential amplifier [10M]

(b)Explain the operation of CMOS inverter [5M]

OR
6 Discuss the principle of High Gain Amplifiers Architectures [15M]

SECTION-IV

7 Discuss the concept of op amp compensation and give the necessary expressions. [15M]

OR

8 (a)Explain the Design of Two-Stage Op Amps [10M]

(b)What are the various measurements of op amp? [5M]

SECTION-V

9 (a) Explain the Discrete-Time Comparators. [7M]

(b) What is a comparator and list the important characteristics of a comparator [8M]

OR

10 What are the various forms of improving the slew-rate of a 2-stage op amp and obtain [15M]
the expression for slew rate of CMOS op amp

**********
 R17
Code No: R17D6805
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
[Link] I-Year - I Semester Regular/Supplementary Examinations, Dec-18/Jan 19
CMOS Analog Integrated Circuit Design
(VLSI&ES)
Roll No

Time: 3 hours Max. Marks: 70

Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE
Question from each SECTION and each Question carries 14 marks.
*****
SECTION-I
[Link]. 1.a. Draw the physical structure of n channel and p channel MOS transistor using well
technology
and highlight the importance points? [7M]
b. Explain the importance of BSIM3 model addresses threshold voltage reduction? [7M]

OR
[Link] 2.a. Explain the small signal model for the MOS transistor? [7M]
b. Explain about CMOS device model? [7M]

SECTION-II
[Link].3.a. Explain the the feedback through effects by using a dummy transistor? [7M]
[Link] the current sink circuits and explain the VI characteristics? [7M]
OR
[Link].4.a. What do you mean by band gap reference and list the principle involved? [7M]
[Link] the circuit diagram of standard cascode current sink and how its reduces the errors in
V or I? [7M]
SECTION-III
[Link].5.a. Draw the circuit diagram of output amplifier using push pull inverting amplifier and
comment on
it? [7M]
b. Explain the noise model of a p channel differential amplifier ? [7M]
OR
[Link].6.a. Explain the design relationships for the differential amplifier? [7M]
b. Draw the circuit diagram of differential mode and common mode circuits using CMOS and
explain? [7M]
SECTION-IV
[Link].7. What is compensation of Op-amp? Explain the operation of Miller compensation. [14M]

OR
[Link].8.a. Explain the design procedure for the 2 stage CMOS opamp? [7M]
[Link] folded cascode op amp? [7M]
SECTION-V
[Link].9.a. Explain regenerative comparators? [7M]
b. Draw the switched capacitor comparator and highlight four important points? [7M]
OR
[Link].10.a. How to improve the performance of an open loop high gain comparator by auto zeroing?
[7M]
b. Explain clamped push pull output comparator? [7M]

****