Units
Processor
and mem interface Typesof lines Jun
man size of memory that can be used is determined by its
addressee scheme
toxandle ass mem interface
[Link] foyson
if a comp 32 address a
24 locations
mar
I III mentation
Address Data and Central lines
connection b w proselor memory involves 3 types of lines
Address lines
data lines
Controllines
addresslines are used
by the power to specify the mentation
data lines are used to facilitate thetransf ofdata b w the process Ethenemy
controllines are used to provide essential timinginformation ensuring synchronization
b w Moussa and memory
control lines carry READ and wage commands
a processor needs to read data controllines conveya RED command
ifto memory
Asif a ne WIE command to memory
Fundamental Concepts PL IR Fetch Phase Ex phase
Program Counter
keeps track of the next instanttobeexecuted
After fetching an instant PCis updatedto point next instant in sequence
Instruction Register
Streetthe fetchedinstantintothe IR from the memory
[Link] mesmerose area in the
and is placed in the IR_in the processor
executed contentsof IR is examined to determine which operation is to
beperformed
The specified operation is then performed by the processor As ALUoperations
and storesthe result in destination location
once execution phase is completed PC contains the address of the
next instruction and a new fete phase begins
This is known as Fetch ExecuteLyn
Single Bus organization of datapath in CPU
1 data at a time
single Bus fetches only control signals
EFFI
consff
shift If
fneral
purpose
Iris
E
registers
my in
Dev E
Dadpathcomponents
ALL toperform arithmatic belogic operations
stores data temporarity duringexecution
Steffy
Internal Bus connects ALU and registers
Decoder generatescontrol signalstoregister selection data transfer
T [Link] eo IEdi
ff yf
registers
[Link]
fomgf
Y Z TEMP are for tempstorage duringexecution notfor programmers
Lex selects b w Youtputon constant 4 tofeed the ALU's Ainput
4 is used to increment value ofPC by4N
Exudes steps
[Link] fttEotaer Aw to computation
controlled by the deedswhich selects the registers involved in the transfer
IYfffthnsmgtiem [Link] presanside
MARholdsthe mem address
MDRloadsthe datafrom m intointernalbus
controlsignalsfrom decoderdirectthe transfer
Arithmatic logic operations
perform arithmatic logic operations using ALU
ALU recieves data from selectedregisters internalbusperforms operation
and stores result back to a register
Atdecoder generates control we
ftfhekhf [Link] a
MAR holds add mem
MDR receives data [Link]
[Link]
the mem
control e A
Control Sequence
series
ALVoperation
ofcontrol signals generatedby a control unitin a processor
Of write a control sequence for the instant ADD R1 R2 R3
R out Yin contents
of RI movedtoY
R2out SelectY Add2in R2is addedwithYanswer ismovedto 2 Y
Zont 23in contents
of 2 is movedto R3 RTY 92
2 R3
fetchins
D write the control sequenceoftheinstinsinvolvingmen read operation assumeinstance isalready
fetchedfrom mem and stored in IR M
Effdoffetingwithcontents
1 RI out Marin Read place [Link] initiatereadoperation
2 MDRin E WMFCC waitforMFCsignalfrommem indicatingthat iscopiedtoMDR
oreadisdonedata
3 MDR
Ethmoid fromMDRtoR2
more data
waitmenton complete
write the control sequence for mem write operation
of the
interne MOV R2 R1 assuming the instant is already
fetched and stored in IR
1 Riont MARin
2 Rout MDRin Waite
3 MDROut E WMFC
Ofwrite LITE control sequence forexecution of instantADDEDm
first 3 lines
are same for all
Pout MarinReadSelect4 Add 2in Pcontents MARReadALUto add 4 to allcontents
waitto instantiomoring
[Link] Y
sfatsaggohmohm [Link]
RoutMarinRead Rs
[Link]
[Link]
Zout Rlin End 2 R1 end my g
Of write we
ADD R2 R1 V
direct
Plot MarinRead Select4Add2in
Zoat Plin Yin WMFC
fatty
MDRout Irin ADD R3 R4
Ri out Yin
Rout Selecty Add2in
Zout Min End 2nd last
stor
head
Brandy insulin
we use a branchtargetaddress to replace the contentsofPC
this is done by adding an offsets
OfControl sequencefor unconditional branch instant
Plont MARin Read Select4 Add 2in
Zout Plin Yin WMFC same sequence
MDRout Ikin getbranchinstant toIR
Offset field of Iront Add2in
Zout Plin End
A Controlseq for conditionalbranch instant Branch 20
44am an
SL 2
Zout Plin Yin WMFC
Iront Add2in
field
Offset of if N O then End
Zout Plin Endy
Multiple Bus organization
trammattimism
we can complelete many
operations in a lesserno
y s collection
fall the registers
we have 3 buses to
execute simultaneously
which makes the process
faster
[Link]
a separate increments
is provided we donot
needto add 4 using ALV
manatees
ALUsimplypassesoneof
the twooperands to the
BÉ busc
t
datalines haddresslines
[Link]
Cs z
D write control seg to ADD R4 RS R6for3busogh
Plant R B Marin Read Ro out Yin
WMFC Informant R out select'sAdd2in
MDRontB RIB Irin Zout Rain End
F7
k fsAdd R6inEndp
Hardwired Control
To executeinstusperoper generation of control signalsis needed
in proper
sequence
speed
mpledesigh
lower cost
lossoutheafficiency
Advantage
can operate in high speed
each step 1 Ile cycle
A counter keeps trackof
these steps
decoder provides separate signal
for each step
explain conditionalcodes
2 mn
Efffi
Y Éintal no ofwords same
i
NV
word size diff WX
vertical night Lament II
matrix both diff Nw
design 128 16 RAM using 128 4 ram
128 3 horizontal
P 1 1
8
q 4
no of chips req 9
1 41
Y decodersize 1 no decoder
88 to
horizontal
m
42 ti this
i skinned
1024 8 using 256 8
101 4 p pXq 4 chips
1 9
l
dead
i 1
ti
y 4
11
ammonia
Eff
R ff
h
Design 256 16 using 128 l
Data ets
T
I
Call
RII M 220
A design 16k t
8 using 128 1 AM
16K 8 RAM
16 210 8 RAM
[Link]
jeYfpxq
8
p Odm
1040dm
204 4
a 14 y 4 12,1 7Th
510
FAE
III
ftation
IS
7
Wachenapping
Direct
HUYasks L makesmain men appear
v [Link]
Mapping placing of memory blocks in the docketency
DIE
each memblock can be mapped into one singlecacheline
Chacheis divided into no Of cache lines
each line can store one block
ofmemory
hash
simplest mapping technique time
quick acness
tallassee Fwd
each mem block can be placed in any cadreline
no restriction on where to place theblock
req more hardware
Compleseto implement
Dfwod
a compromise b w direct fully as
cache is dir into sets
each set has
multiple lines
each mem block maps to a specific set
within the set it can be placedin any line
less hardware
Balanced approach
Readonlymemoy [Link] vol Bios slowed
PROM EPROM EEPROM flash memory
programtable erasable electrically
data canbe stouddata erases similar to EEPROM
loaded from can be 99 greatdensity
user erased light powerconsumption
irreversible new data physically is low
expensive cambe removed
loaded from circuit
RAM volatile main mom [Link]
DRAM SPRAM
Dynamic Static
mostcommon fast
expensive
low cost no refreshingneeded
highdensity commonly used
slowaccess time in cache memory
needs
refreshing