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EEE517 2nd Material

The document discusses advanced circuit techniques, focusing on phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs). It describes the components and functionality of PLLs, including phase detectors, low-pass filters, and their applications in signal detection and processing. Additionally, it covers design relationships and calculations for implementing PLL circuits in various applications.

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0% found this document useful (0 votes)
9 views11 pages

EEE517 2nd Material

The document discusses advanced circuit techniques, focusing on phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs). It describes the components and functionality of PLLs, including phase detectors, low-pass filters, and their applications in signal detection and processing. Additionally, it covers design relationships and calculations for implementing PLL circuits in various applications.

Uploaded by

juliusalajani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF or read online on Scribd
EEE 527: ADVANCED CiecuiT TECHNIQUES : 7 Ne ART TWO), write in this} Candidate's. Exam No Question write in this ¥ » ree ea Write on both sides o he paper 2:0 | PHASE-LOCKED LOOP: ‘ A ay UL) _t close = : ba m_w which a generated stanal, ablis @ stinchrenization or tuck’ with ae Dec stqnal |The basic ragram of a RLL is shown m TEC; iE ean een that 1 donsist of a phase detector, Allow — pass clter, an amplifier and a va stl oscil dtor V:C-0). number ef integrated Cireut versisns Lit are offered by different manufacturers ot |low cot d_ this made the PUL technique popular for Vario tgnal = detection and _ processing paltatiehs. Most} intearai P-Lls require only a few ~ extemal_compenen complete. tem ;_usuall4 these are componerts Which alldus the. er te sel he free - sunning frequency of LC and passband of she filter. Y i J INPUT, Phase Low=pas Amplifier urpar. detector file F oe Noltage Coatrolled Oscillator Figa+1 Block diagram ef a phase-locked bh } Vv Question. ...scssereeeeretteres Write on both sides of the paper eveltes an "ela ale is properis a rence the two ators: “he oulp i as the error voltage, Ve: if Se He inp ae atl ak_differen Ges es ge will corifam mpenerils ties Aaicsatag Q@ frequency whi equal ts! the difference bebueen The input frequehaes This ts knew as! the difference = = fiequensy The action of the phase defect is t ee He mpul signals tegeher. In a ptt. q e@ Mput signals fo Yhe phase defector is tbe Signal td be processe: and she other simal ; provide. by She V.C-0. The ouput voltage of he Vc. is usually Q square waveform varying he Ee posthive votfage and approximalely Zers | 2--2[The Voltage - controlled _ Oscillator A_yoltage - controlled secllor V:C:0) 18 an_oscillalfe whose frequen can nan bu @ valtace app ied i to its control “termnal. the =a Ae eV: C. 0 qre : Do not write in this margin Candidate's Exam No Question Write on both sides of the paper ©)" Good frequency stability e VCO. is usually some form _ oe not waite in this margin basic aoc of the lew- =pass {ler bb ifference - equenc Component of she error wo ef che phase detect he filler also tnproves the” rdepo % -U1. tS changes be fieg a of 4 rereerence. the effects of an kk Center _fiegueny a which ae caplure vange th ts the von ats can anti Candidate's Exam No. ++ Question. Write on both sides of the paper ATThoudh, The | os and Cape (Se teat € at Caceres bide Hhan he Fas 4B _wWhich i oful ram ‘are ea 192-30) and (b) or can be. can iat the TC yicle des 0. ge_de ie 4 ote a ti ke | cana d ait Ce iden pins ‘J and 10 . “The rs g ff he VCO is sek g ag x cr a et ger I Do not Do not ite in this] Candidate's Exam No.2... Question “ee margin ae eh baka ple C100/ He fb _SWatl- and qenerdes bath a demodulated, teference 6 woltage. the reference vd} s mn iloble so iNet if required, the PLL ddmetul con be applied ts a. vette “compa rater. “Gen Saw topit b rer aces Pe syero—eutputqjy 5 Preset voopt Ts Foc Reference outpat [Je Wo etemat upratr Denodefafed (7 Veo extemal vesishr | Fq.2-3 565 PLL @® Pin connediins (&) Block diagram [the “Fuso mpul pra pros at 3 must be 9 dc bios v Somewhere mm ae ToMae| fs -4V . The power supply Cequirements the SS5_are fiom TEV B HRV. 2:5 |Design Re stitaships —— @ [the V6o pecuyrang corks ¥ enc S esfedali by Ri and ¢ = et & qven by: + ARO Re Sea e 36kN resist oppents on the du ™ dim _of the loop fi heb Tin me constant _assocat with this resis] de as Ra) and “the external capacitance ome have) Y= R= BCC CS) 2.9) Ihe_lsck-rang & atven by 7 ft tty where \ec_is the telal j at Ve bias: Gernitale. 7 vellage “Tbehueen he) ©, can be any value but R, must have a valy . . 20k, ath a value near t 4000.2 Pas q resent @ within the range 20nd. being preferred as. (@ The capture range f, & Given by = ‘pao +L [am fe ame Candidate's Exam No css Question ‘Write on both sides of the paper +12V_ voltages. Defermme ; @ free —running cenler frequency. Sock range Fig 2-4 ypical connedion diagram fer oe Qs FM detection Nofé : “The purpose OF “he ©-O01 NF Capaclsr conned betaeen Pip Tand & ie timid 2 osallabin, Do not ‘rite in this Margin cones dQuastionssssssedeneeenee® Candidate's Exam No... ‘Write on both sides of the paper I wit © & be designed fer an _Opplica the follonng ‘requirements v Do nor write in this margin Candidate's Exam No Question rive pn both sides of the paper aie O} ae alues of Rand C he TOMAE Solution fay 2 fein sf 2203 RG =03 = 03 2x10 , 8 RG fi R5KIOe Lek Ru Bie Then C; = axle = 4x0 °F = 400pF | 3x 10% =< | ) Lock ran ~ k I pe + 8G hee (Ve = /2V) cw f =+ &x 25x O° = +t [66:67 kHe a 122 (c) “the ae Lepression ‘ig Given b « equatn 2-4) _quarhcies i att eth are knew eaeiet T_. Dropping “he t sign t momentarily and _ solving fox , = i i - 16-67 x10 = 6 43/5 x10 S are = _2arx (20 x}0")* Be xlO But Ros eh ue 65 PLL ciruit is te be designed fer an apphicffier th the a Tequirements ency = 100 kHz @) Capture range = + Site &)_W “be powered with £Gv supplies Determine cal_pppoprinte values of Ri, and C_ Whe lock range and ‘(ey “The required value of G ANS: f @ RG = 3x0" | R= 3S G=00IE ) ff = $66.7 kts © G = O-IN79 PF O12 pF ANS eee Tikte OE AEST We OTe ee Do not Candidate's Exam No Question waite in this margin i ‘Write on both sides of the paper A S65 Pit ctrant is & be despgned fbr on appllicelsa * @) Opproprial e_Nalwes of R and C &)_Lbek “range the rey . fay R= 1Ok2 , C = 0-001 pF byt (Oke ‘

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