H1008 Journal of The Electrochemical Society, 157 共11兲 H1008-H1013 共2010兲

0013-4651/2010/157共11兲/H1008/6/$28.00 © The Electrochemical Society

Deposited Thin SiO2 for Gate Oxide on n-Type and p-Type

GaN
M. Placidi,a,z A. Constant,a A. Fontserè,a E. Pausas,a I. Cortes,a Y. Cordier,b
N. Mestres,c R. Pérez,d M. Zabala,a J. Millán,a P. Godignon,a and A. Pérez-Tomása
a
Institut Nacional de Microelectrònica-Centre Nacional de Microelectrònica-Consell Superior
d’Investigacions Cientifiques and cInstitut de Ciència de Materials de Barcelona-Consell Superior
d’Investigacions Cientifiques, Campus UAB, 08193 Barcelona, Spain
b
Centre de Recherche sur l’Hétéro-Epitaxie et ses Applications-Centre Nacional de la Recherche
Scientifique, 06560 Valbonne, France
d
Plataforma de Nanotecnología, Parc Cientific de Barcelona-Universitat de Barcelona, 08028 Barcelona,
Spain

Here, we report on a comparison of two different methods to achieve thin SiO2 deposited layers for gate oxide on n- and p-type
GaN by using plasma-enhanced chemical vapor deposition with silane 共SiH4兲 and tetraethyl orthosilicate 共Si关OC2H5兴4兲 precur-
sors. An annealing was performed at 800°C for 2 min in N2 ambient as an attempt to improve electrical characteristics. Before and
after annealing, capacitors were electrical/physically analyzed by capacitance–voltage 共C-V兲, conductance–voltage, current–
voltage, optical microscope, scanning electron microscope, atomic force microscope, and secondary-ion mass spectrometry.
Globally, the p-type samples presented higher interface state density and rougher surfaces, and in some C-V measurements, it is
possible to observe inversion-like characteristics. The surface roughness also increases after annealing. The interfacial trap density
for the different SiO2 /GaN interfaces has been determined. Silane samples exhibit lower Dit than TEOS samples. For n-type,
annealed SiO2 from silane has been found as the sample with the lowest Dit. The annealing on the SiO2 from silane samples is not
so efficient for the p-type with the Dit actually increasing. A discussion on the different diffusion mechanisms in correlation with
the electrical results is performed in the last section of this paper.
© 2010 The Electrochemical Society. 关DOI: 10.1149/1.3486091兴 All rights reserved.

Manuscript submitted June 14, 2010; revised manuscript received August 9, 2010. Published September 16, 2010.

Silicon 共Si兲-based metal-oxide-semiconductor 共MOS兲 devices acteristics of the SiO2 silane-based and TEOS-based deposited on
possess high quality insulating layers of silicon dioxide 共SiO2兲 both n- and p-type 2H–GaN are compared. In prior works we also
grown directly on Si using wet or thermal processes. This high qual- reported the effect of using a cap layer for source and drain contact
ity oxide and interface play a crucial role in achieving high perfor- formation8 required for MOSFET fabrication.9
mance devices, thus efficiently preventing leakage current. Many
semiconductor materials with superior electrical properties relative Experimental
to Si, such as gallium nitride 共GaN兲, do not currently form good The MOS structures were fabricated on p- and n-type 共0001兲
semiconductor/insulator interfaces being detrimental for their use on 2H–GaN epilayers grown on c-plane sapphire substrates, supplied
high frequency or high power applications. by TDI. The p-epilayer was 6 ␮m thick, Mg doped 共NA = 1.9
The ideal insulator for GaN-based devices should exhibit a good ⫻ 1017 cm−3兲 while the n-epilayer was 5 ␮m thick, unintentionally
chemical and thermal stability because GaN is expected to extend doped 共ND = 2 ⫻ 1016 cm−3兲. A high resistivity Zn compensated
the silicon high temperature operation range. For this reason, it buffer layer was grown between the sapphire substrate and the GaN
should have no mobile oxide traps, low interfacial trap density, and layers. Samples were submitted sequentially to solvent degrease 共ac-
a dielectric constant higher than GaN to avoid premature breakdown etone and isopropyl alcohol兲 and then to a SiO etch. Finally, a
at low electric fields. A large band offset of conduction and valence chemical RCA-based cleaning process was performed. A 100 nm
bands to provide good confinement of carriers is also a requirement. thick amorphous SiO2 layer was then deposited by PECVD using
Due, to its very well established technology, large band offsets either TEOS or silane as the source material, both on n- and p-type
and low leakage current, SiO2 still remains the general insulator of substrates. Temperature deposition was 380 and 400°C for the silane
choice for successful GaN metal-oxide-semiconductor field effect and TEOS-based processes, respectively. Table I summarizes the
transistors 共MOSFETs兲.1-4 Other crystalline insulators such as main parameters used in both processes. Lateral n- and p-type MOS
MgO,5 Sc2O3,6 or Gd2O3 7 have recently been investigated because capacitors were fabricated to investigate the C-V characteristics and
they present ordered interfacial structure resulting in lower interfa- to determine the density of interface traps within the bandgap close
cial trap density but they also could induce high strain levels thus to the conduction and valence band, respectively. The area of the
favoring the defects diffusion at the interface. Although it evidently gate electrode was 0.45 mm2.
has potential applicability, for example in a power switch device, Capacitance–voltage 共C-V兲 and conductance–voltage 共G-V兲 mea-
there is much less information available of the characteristics of the surements were performed in the dark using a Keithley K82 system.
MOS interface on GaN when it is compared with Si or SiC, which Quasistatic 共C-V兲 characteristics were probed using the linear ramp
has been massively investigated. voltage sweeping technique in which the charge current was mea-
Here, we report on a comparison of two different methods to sured instead of the capacitance. The quasi-static capacitance was
achieve SiO2 MOS on n- and p-type GaN by using plasma-enhanced then calculated from the low frequency current 共C = I/共dV/dt兲兲 in
chemical vapor deposition 共PECVD兲 with silane 共SiH4兲 and tetra- which a sweep rate of dV/dt = 0.7 V/s was used. High frequency
ethyl orthosilicate 共TEOS, Si关OC2H5兴4兲 precursors. In traditional C-V characteristics were also measured at 10, 100, and 1000 kHz
silane-based processes, SiO2 tends to stick readily and an undesired using different signal amplitudes and time stresses. After as-
oxidation can be expected at the beginning of the reaction. In TEOS- deposited 共AD兲 electrical characterization, an annealing 共AN兲 was
based processes, the silicon atom is already oxidized, and thus, the performed at 800°C for 2 min in N2 ambient as an attempt to im-
conversion of TEOS to silicon dioxide is essentially a rearrangement prove electrical characteristics. Surface morphology was examined
rather than an oxidation reaction. The electrical and physical char- using an optical microscope, a scanning electron microscope 共SEM兲,
and an atomic force microscope 共AFM兲. Secondary-ion mass spec-
trometry 共SIMS兲 was also used to analyze the depth distribution of
z
E-mail: [Link]@[Link] chemical elements after the SiO2 AN.

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 Journal of The Electrochemical Society, 157 共11兲 H1008-H1013 共2010兲 H1009

Table I. Summary of the PECVD silane- and TEOS-based SiO2 deposition parameters.

Thickness Temperature Pressure Flow rates

Process 共nm兲 共ºC兲 共Torr兲 Time 共sccm兲 Others

Silane-based 100 380 1 2 min 20 SiH4 Radio-frequency power: 250 W

1000 N2O
800 N2
TEOS-based 100 400 9 17 s 1000 O2 Radio-frequency power: 395 W
500 TEOS

Physical and Electrical Characteristics gases that have hydrogen related bonds, and thus, H migration into
GaN can occur. It was theoretically predicted that H can be as a deep
Electrical characteristics.— Quasistatic C-V.— Figure 1 shows donor in p-type GaN and enhances the diffusion of defects.12 For
a typical quasistatic C-V curve for AD MOS capacitors with silane this reason, AN is usually performed in nitrogen ambient to remove
and TEOS-based SiO2 on n- and p-type GaN. The negative flatband this undesired H both in GaN and dielectric layers. However, the
shift observed suggests that fixed positive oxide charges are present concentration of H impurities still remains elevated in p-type ni-
in the SiO2 bulk or at the GaN/SiO2 interface, being slightly higher trides after conventional AN.12
for the silane-based SiO2. It was routinely observed that a lower Silane-based SiO2 on p-type samples shows a rather uncommon
accumulation capacitance value 共Cox兲 was obtained on the silane- characteristic for a wide bandgap MOS capacitor. GaN or SiC MOS
based SiO2 on n- and p-type capacitors. Profilometer measurements structures generally not show surface inversion at room temperature
confirmed the homogeneity of our process with a deposited thick- because the generation rate of the minority carriers is extremely low
ness of 100 nm for both TEOS and silane. We suggest that this Cox 共ni is around 10−10 cm−3兲, thus resulting in the deep depletion fea-
difference would come from a higher dielectric constant value ture in the C-V characteristic. Nevertheless, an inversion character-
共around 4.9兲 for AD TEOS-based SiO2 as previously reported for Si istic seems to take place, as it can be inferred in the quasi-static
capacitors.10 curve 共Fig. 1c兲. This inversion characteristic seems ever more evi-
After AN for 2 min in a N2 ambient at 800°C, both n-type TEOS dent after the N2 AN. Huang et al.13 and Nakano et al.14 already
AN and silane AN still show a negative flatband voltage shift. For reported a surface inversion in a p-type GaN capacitor, without the
the silane AN, this shift is small but for TEOS AN flatband capaci- presence of minority carriers source. Nakano et al.14 attributed this
tance is clearly shifted toward negative values. The Cox value for behavior to dislocations, acting as recombination centers and thus
TEOS AN is now analogous to the silane AN 共Fig. 2兲. Again, it helping to the formation of a surface inversion layer at the interface.
would be an indication of a change in the dielectric constant, which They also attributed the decrease in the inversion capacitance with
would also be associated with a densification of the TEOS SiO2 frequency to incomplete ionization of Mg dopants, which can follow
film. da Silva et al.11 reported the presence of –OH contamination in the voltage modulation when the C-V frequency is decreased.
the oxide layer, and they suggested that the increased dielectric con-
stant was due to dielectric polarization of OH molecules in the film. High frequency C-V curves and interface state density.— The high
frequency 共higher than 10 kHz兲 C-V curves of the AD and annealed
SiO2 deposited from TEOS at low temperature results in silanol
samples are shown in Fig. 3 and 4 for the n- and p-type capacitors,
共Si–OH兲 incorporation due to the large size of the TEOS molecule.
respectively. Although it is not reported here, the accumulation ca-
On the contrary, silane chemistry only requires the elimination of
pacitance presents a much more important decrease at frequencies
small hydrogen molecule. It is reasonable to suggest then that after
higher than 10 kHz, especially at 100 kHz, compared to the quasi-
AN the contamination coming from the C–H and O–H is reduced,
static C-V value. This situation reminds a typical series resistance
thus decreasing the dielectric constant value.
effect commonly observed in MOS structure.
Moreover, the Mg-doped GaN grown by metallorganic chemical
An estimation of the interfacial trap density has been determined
vapor deposition inherently contains a huge amount of hydrogen 共H兲
from the C-V deviation from ideal characteristics 共Fig. 3 and 4兲 by
atoms, which passivate Mg acceptors. During the PECVD deposi-
tion, H incorporation is also possible because SiO2 films use source

Figure 2. 共Color online兲 Quasi-static C-V characteristics for the annealed 共2

Figure 1. 共Color online兲 Quasi-static C-V characteristics for the AD 共a兲 min at 800°C in N2兲 共a兲 silane-based SiO2 on n-type GaN, 共b兲 TEOS-based
silane-based SiO2 on n-type GaN, 共b兲 TEOS-based SiO2 on n-type GaN, 共c兲 SiO2 on n-type GaN, 共c兲 silane-based SiO2 on p-type GaN, and 共d兲 TEOS-
silane-based SiO2 on p-type GaN, and 共d兲 TEOS-based SiO2 on p-type GaN. based SiO2 on p-type GaN.

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 H1010 Journal of The Electrochemical Society, 157 共11兲 H1008-H1013 共2010兲

Figure 3. 共Color online兲 High frequency C-V characteristics of metal-

Figure 5. 共Color online兲 Interface state density for the n-type GaN/SiO2
insulator-semiconductor capacitors for the n-type GaN/SiO2 capacitors with
capacitors for the AD and annealed silane- and TEOS-based SiO2.
共a兲 AD silane-based SiO2, 共b兲 annealed silane-based SiO2, 共c兲 AD TEOS-
based SiO2, and 共d兲 annealed TEOS-based SiO2.

state density, which is slightly higher close to the valence band. The
the Terman method15 and the conductance losses. The interface state TEOS-based SiO2 interface state density is markedly asymmetric.
density 共Dit兲 spectra within the bandgap close to the valence band Dit is lower near the conduction band in the TEOS AD but lower
and conduction band, for the silane- and TEOS-based SiO2 capaci- near the valence band in the silane AD. Such an asymmetric inter-
tors implemented on n- and p-type GaN substrates, respectively, is face state density, with higher values near the valence band agrees
presented in Fig. 5 and 6. with Huang et al.13
For n-type GaN 共close to the conduction band兲, an interface state We suggest that this difference between the conduction and va-
density of 1.1 ⫻ 1011 and 6 ⫻ 1011 cm−2 eV−1 has been extracted lence band may be due to the difference in the starting material
at Ec − ET = 0.2 eV for silane AD and TEOS AD, respectively. quality between the n- and p-type. The p-type usually presents larger
After AN, the interface trap density of n-type silane AN is reduced number of dislocations and higher surface roughness due to the re-
to 6.1 ⫻ 1010 cm−2 eV−1, clearly indicating an improvement of the quired AN thermal budget required to activate the Mg dopants dur-
interface characteristics after the thermal treatment. On the contrary, ing or after the growth. Moreover, it has been reported16 that any
the TEOS AN Dit is increased to 9.2 ⫻ 1011 cm−2 eV−1, revealing plasma deposition method inevitably induces a thin amorphous
a deterioration of the interface. This trend is corroborated with the GaOx layer, which almost certainly contributes to an increase some-
G-V measurements. Lower conductance losses were observed for how of the density of interface states.
silane AN SiO2, while theses losses are increased for TEOS AN. For The interfacial traps in the upper half of the bandgap are believed
p-type GaN 共close to the valence band兲, interface state densities of to be acceptor-like in nature and these states are responsible for the
1.1 ⫻ 1011 and 1 ⫻ 1012 cm−2 eV−1 have been extracted at ET scattering of free carriers in n-channel devices. For an n-channel
− EV = 0.2 eV for silane AD and TEOS AD, respectively. After MOSFET, only the upper bandgap acceptor states must be consid-
AN, the Dit is slightly increased to 4.2 ⫻ 1011 cm−2 eV−1 for silane ered because the lower bandgap donor states are neutral when the
AN, while for the TEOS AN, Dit was reduced to 2.9 inversion channel is formed. For this reason n-type capacitor char-
⫻ 1011 cm−2 eV−1, revealing an improvement of the interface. acteristics have attracted more attention. A rude comparison with
Summarizing, the deposited silane-based SiO2 presents the best previously reported Dit values could be done. Nevertheless, it should
interfacial properties in terms of low Dit, with a symmetric interface be considered that the Dit value depends on the extraction method
and in the experimental setup. Bae et al.16 reported a value for the
Dit around 共2 − 9兲 ⫻ 1011 cm−2 eV−1 using a Ga2O3 /SiO2 dielec-

Figure 4. 共Color online兲 High frequency C-V characteristics of metal-

insulator-semiconductor capacitors for the p-type GaN/SiO2 capacitors with
共a兲 AD silane-based SiO2, 共b兲 annealed silane-based SiO2, 共c兲 AD TEOS- Figure 6. 共Color online兲 Interface state density for the p-type GaN/SiO2
based SiO2, and 共d兲 annealed TEOS-based SiO2. capacitors for the AD and annealed silane- and TEOS-based SiO2.

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 Journal of The Electrochemical Society, 157 共11兲 H1008-H1013 共2010兲 H1011

Figure 8. 共Color online兲 Quantitative TOF-SIMS depth distribution profiles

of the aluminum, gallium, nitrogen, silicon, hydrogen, SiO, and SiO2 ele-
ments using 共a兲 Cs+ and 共b兲 O2− for the TEOS-based SiO2 deposited on GaN
and annealed at 800°C in N2 ambient during 2 min.

Cesium ions were first used to sputter etch the surface while mea-
Figure 7. 共Color online兲 AFM images of the SiO2 共a兲 silane-based on suring the depth profile 共Fig. 8a兲. A bare p-type GaN sample was
n-GaN, 共b兲 TEOS-based on n-GaN, 共c兲 silane-based on p-GaN, and 共d兲 also used as reference sample to provide a clear comparison of the
TEOS-based on p-GaN.
different involved mechanisms that could occur.
Different information can be extracted from this measurement.
There is a clear evidence of an unexpected aluminum signal at the
tric scheme. Lin and Lai17 reported a value of 5.9 SiO2 /GaN interface extending toward the GaN layer. The wafer pro-
⫻ 1010 cm−2 eV−1 共at 0.4 eV from the conduction band兲 for an vider 共TDI兲 corroborated that Al tails may be detected in SIMS
annealed sample using a GaOxNy /SiO2 stacked dielectric strategy. depth profile scans for some of their commercial samples and linked
Huang et al.13 has reported the lowest value, around 3.8 this phenomenon with a kick-off mechanism of diffusion via point
⫻ 1010 cm−2 eV−1 共at 0.2 eV from the conduction band兲 for an defects. It may be due to TMAl in the reaction chamber during the
annealed TEOS-based SiO2. Therefore, values reported here are growth, but no details concerning the growth were provided. An-
comparable to the state-of-the-art, especially for the annealed silane- other explanation could be that Al atoms can diffuse during the post
based SiO2. SiO2 deposition from the Al2O3 substrate into the GaN layer and
segregate into dislocations.20,21 A peak of GaOx also becomes evi-
Physical characteristics.— It was observed that for both silane dent at the interface revealing the presence of Ga extending toward
and TEOS, the surface morphology becomes rougher after AN. Fig- the SiO2, as shown by the tail spreading into the oxide layer. This
ure 7 shows AFM scans of the n-type and p-type SiO2 /GaN after could be explained by the out-diffusion of the Ga from GaN into the
anneal. For the n-type samples, the surface morphology of the SiO2 SiO2 layer.
silane AN and TEOS AN are similar. They present a relatively low When oxygen ions are used as the sputter medium for the mea-
mean roughness 关root-mean-square 共rms兲兴 of 2.9 and 2.6 nm, respec- surements 共Fig. 8b兲, Ga is detected in the whole SiO2 layer from the
tively. These values are higher than that before AN where the rms top down to the SiO2 /p-GaN interface. This indicates that diffusion
was 0.74 and 0.86 nm, for silane AD and TEOS AD, respectively. of Ga has occurred, even though no clear diffusion tail was ob-
For the p-type GaN samples, the surface morphology is significantly served. We suggest that, apart from the potential out-diffusion of Ga
rougher than for n-type. Before AN, rms values of 1.35 and 1.68 nm during high temperature treatments, Ga could be present in the SiO2
were extracted for silane AD and TEOS AD, respectively. After AN, as GaOx from the GaN/SiO2 interface oxidation.17 It was suggested
rms values of 3.7 and 18 nm were extracted for silane AD and TEOS that Ga begins to out-diffuse during the SiO2 deposition due to the
AD, respectively. As it can be seen in Fig. 7d, many islandlike presence of oxygen in the deposition chamber. In this sense, Lin and
aggregations of up to 1 ␮m diameter and 200 nm thick can be Lai17 already reported Ga diffusion into SiO2. The diffusion rate of
observed in the surface of the TEOS-based SiO2 AN. These islands Ga in SiO2 would be about 100 times faster than Si in GaN. The
remained after many cleaning processes, including an O2 plasma. faint peak of Ga observed at our interface seems to effectively con-
Nakano et al.18 reported similar islands in the early stage of firm a Ga diffusion process. Analogously, out-diffusion of Ga has
thermal oxidation of GaN:Mg and were composed of Ga and O. been reported during the NiOx deposition for contact realization on
They also found a high density of microholes in the GaN surface p-GaN. In this case, the oxygen assists the diffusion of Ga from
related to dislocations formed during the AN. Lin et al.19 also re- GaN and thus creates Ga vacancies below the contact and lowers the
ported some droplets in the oxidized n-type GaN surface at 800°C Fermi level.22 Al is also detected at the interface, probably bonded
suggesting a possible atom out-diffusion mechanism. with oxygen. Hydrogen is also observed. A light tail of silicon into
This p-type TEOS AN sample was further analyzed. A time of the GaN layer also seems indicating a possible diffusion, which
flight 共TOF兲 SIMS analysis has been performed to detect plausible probably occurs during the AN. Nevertheless, it should be men-
species interdiffusion mechanisms between the TEOS-based SiO2 tioned that due to the relatively high roughness obtained on the
and the p-type GaN after AN 共Fig. 8兲. TOF-SIMS 共using an TEOS AN sample, the SIMS nonabrupt interface may be magnified
IONTOF IV instrument兲 depth profiling was carried out using Bi as and the diffusion processes overestimated.
the high energy primary ion source 共25 keV兲, combined with low
energy sputter guns at 2 keV 共Cs+, O2−兲 with an angle of incidence Discussion
of 45° with respect to the surface normal. The sputtering ion beam is Compared to other semiconductor/SiO2 interfaces, the GaN/SiO2
scanned over a 300 ⫻ 300 ␮m area, while the primary beam is interface has not been extensively investigated and few works are
within an area of 50 ⫻ 50 ␮m in the center of the sputtered crater. available. The physics of the III-nitride/dielectric interface is rather

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 H1012 Journal of The Electrochemical Society, 157 共11兲 H1008-H1013 共2010兲

Table II. Summary of the physical and electrical characteristics higher negative flatband shift obtained compared to the TEOS-based
of the GaN SiO2 capacitors. SiO2. It can also be argued that during the N2 AN, N can be incor-
porated into SiO2, with the result that the Si–N bond or Si–O–N
Qeff Dit rms bond are formed in SiO2, and could explain the shift toward nega-
Sample ␧r 共cm−2兲 共cm−2 eV−1兲 共nm兲 tive values of the TEOS-based SiO2 C-V curve after the AN. More-
over, the N from N2 can react with the Si near the SiO2 /GaN inter-
n-Type face to form Si oxynitride, which can block the nitrogen out-
Silane AD 3.9 9.7 ⫻ 1011 1.1 ⫻ 1011 0.74 diffusion from the GaN substrate more effectively than SiO2. In fact,
Silane AN 3.9 8.9 ⫻ 1011 6.1 ⫻ 1010 2.9 we suggest that nitrogen from the GaN surface probably incorpo-
TEOS AD 4.9 3.2 ⫻ 1011 6 ⫻ 1011 0.86
rates into the oxide, thus creating a SiOxNy layer at the interface,
TEOS AN 4.9 7.9 ⫻ 1011 9.2 ⫻ 1011 2.6
and this nitrogen lowering in the GaN near surface renders the gal-
p-Type lium able to diffuse through the SiO2 and up to its surface, at least
Silane AD 3.9 1.7 ⫻ 1012 1.1 ⫻ 1011 1.35 for the TEOS-based SiO2 on p-type GaN.
Silane AN 3.9 1.6 ⫻ 1012 4.2 ⫻ 1011 3.7 Lin and Lai17 also reported the formation of SiGaON glass at the
TEOS AD 3.9 — 1 ⫻ 1012 1.68 interface or in the dielectric layer. Moreover, SIMS clearly indicates
TEOS AN 3.9 1.2 ⫻ 1012 2.9 ⫻ 1011 18 that species interdiffusion both into the oxide and the GaN layer and
that an interfacial region around 15 nm can be distinguished. AFM
measurements revealed the formation of islands that increased the
surface roughness significantly both at the GaN surface and SiO2
complicated because the III-nitrides surface is much more altered surface 共or GaN/SiO2 interface兲 of the TEOS-based SiO2 /p-GaN
than expected with air ambient and/or products exposure during the capacitors. These islands are either Ga metallic or Ga oxide or ox-
different technological processing steps. Their varying polarities, ynitride and could introduce additional interface states. However,
lattice mismatch with most dielectrics, initial defects densities the Ga-related interface states are probably not the only responsible
共mainly depending on the type of material and Al concentration兲, for the anomalous capacitance behavior observed after AN at
and the high temperature treatments required for device fabrication 800°C. The incorporated hydrogen during the SiO2 deposition,
also add difficulties to reliably reproduce and thus establish a refer- which passivates the Mg acceptors and acts as donors, reduces the
ence process. total number of acceptors. This could also explain the reduction of
It may be considered that GaN technology is still in its infancy. the accumulation capacitance and the presence of an inversion layer
Nowadays, commercial GaN wafers usually present an overall high in the p-type capacitors.
density of threading dislocations, which can seriously affect the de- The abnormal n-type conductivity behavior in the p-type GaN
vice behavior. The effects of such imperfections are still not well samples in the low frequency regime 共quasi-static兲 共Fig. 1 and 2兲
understood. The interaction of dislocations with impurities and, in indicates a decrease in the minority carrier’s response time. This fact
particular, silicon or oxygen, may create defects states in the band- could be attributed to the diffusion of Si or O atoms 共from the O
gap, acting as traps for carriers. As a general rule, any thermal precursor during deposition or from SiO2 during AN兲 into the Mg-
process in an ambient containing oxygen and/or hydrogen requires doped GaN layer. Thus, an undesired GaN region with Si or O
particular attention because it could seriously affect the GaN sur- impurities could introduce a reduced response time for the minority
face, favoring the defects formation/diffusion. This would be espe- carriers to an applied gate voltage. The minority carrier generation
cially relevant in p-type GaN because these species 共Si and O im- can be explained by deep level impurities introduced during the
purities and Mg dopants兲 migrate rapidly into the GaN. The SiO2 deposition. This explanation correlates well with the fact that
plausible cause of this accelerated migration is related with the pres- no inversion was observed in the TEOS AD SiO2 capacitor 共Fig. 1兲
ence of dislocations. Compensation is possible with oxygen atoms if because in this case the silicon atoms were already oxidized and
they were both present in a high enough concentration and electri- could not diffuse into GaN. However, after thermal treatment, the
cally active. The hydrogen can also strongly influence the activation inversion is observed, indicating a possible Si or O diffusion as it
of p-GaN, even when unintentionally present. In particular for GaN can be derived from the Si tail into the GaN layer from the SIMS
on sapphire, species from the Al2O3 substrate may diffuse within the 共Fig. 8兲.
disordered interfacial region, creating donors responsible for the for-
mation of an impurity band.23 It has been reported that the amount
of oxygen during the growth process can also induce an impurity Conclusions
band of ⬃78 meV below the conduction band.24 Moreover, the in-
corporation of oxygen into p-GaN after a SiO2 thin layer on top is In this work, we studied the properties of the SiO2 /GaN interface
annealed is also possible.25 Moreover, Al diffusion from the Al2O3 using different PECVD SiO2 oxides with silane and TEOS as pre-
substrate has also been definitively observed during the GaN cursors. n- and p-Type GaN on sapphire capacitors were fabricated
growth20,21 and could explain the result obtained in the Al peak at and physically/electrically characterized. An AN was performed at
the interface in the SIMS measurement. 800°C for 2 min in N2 ambient as an attempt to improve the elec-
In addition to the possible diffusion mechanism occurring in the trical characteristics. Before and after AN, C-V, G-V, current–
GaN/sapphire wafer, the TEOS and the silane process are inherently voltage, SEM, AFM, and TOF-SIMS measurements were per-
different. The TEOS-based deposited SiO2 films are more prone to formed. Globally, the p-type samples presented higher interface state
silanol 共Si–OH兲 incorporation due to the large size of the TEOS density and rougher surfaces. The surface roughness also increased
molecule. Therefore, a complete restructuring is required to form after AN. The interfacial trap density for the different SiO2 /GaN
dense SiO2 and eliminates the –OH groups, which can be compli- interfaces was determined. Silane samples exhibited lower Dit than
cated if the absorbed molecule is under the surface, covered by TEOS samples. For n-type, annealed SiO2 from silane was the
subsequent deposition. By contrast, in the silane-based SiO2, it is sample with the lowest Dit. The AN on the SiO2 from silane samples
only the elimination of the small hydrogen molecule that is required. seemed to be not so effective for the p-type with the Dit actually
Table II summarizes the electrical and physical properties ob- increasing. Some peculiar droplets were also observed on the sur-
tained for the different SiO2 capacitors. Comparing the interfacial faces of the p-type samples. These droplets could be related with
properties of silane and TEOS-based SiO2, it could be derived that atoms diffusing out of the oxide in the form of Ga clusters or local
the TEOS-based are more sensible to the AN processes. N atoms can GaxOy oxide becoming more evident after the high temperature AN.
also be introduced into the bulk oxide during the deposition of the The implication of different diffusion mechanisms was then dis-
silane-based SiO2, which uses N2O and N2 gases, explaining the cussed.

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 Journal of The Electrochemical Society, 157 共11兲 H1008-H1013 共2010兲 H1013

Acknowledgments 9. A. Pérez-Tomás, M. Placidi, X. Perpiñà, A. Constant, P. Godignon, X. Jordà, P.

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