Introduction to Backend
Assembly Processes
Chapter-1 (Lecture-2)
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Memory Evolution
Exponential growth in Bits and ~ 50,000X Cumulative Cost Reductions in 20 Years
2
Semiconductor/IC Packaging
• Semiconductor packages are designed to allow the Semiconductor die to communicate with the outside world
• Function of the package
– To encompass multiple functionality at one place
– Signal distribution
– Power distribution
– Heat dissipation
– Protection (Mechanical/Chemical/Electromagnetic)
Fig: Semiconductor Wafer to IC Package
Die Stack Encapsulation
Substrate Gold Wire
Solderball
Side View Top View
Fig: Various Components of a typical IC Package 3
Semiconductor Wafer/Packages – Representative images
Si Wafer 300 mm, ~900 um thickness Semiconductor Wafer Wafer, Separated Individual Die:
~900um thick into individual dies
bond pads on 4 sides
Bondpad
Flip Chip Die
Credit: Micron Inc
Credit: [Link]
Credit: [Link] products/plating-copper/microfab-spm-1100
Substrate Strip/Interposer Die stacking and interconnecting on Molded IC packaging IC Package (example)
substrate (Entire Substrate/strip form)
(unit level)
Credit: [Link]
Credit: [Link]
MOLDED-STRIP-OF-Mokhtar-Rasid/bc2ba8c870f31f79b5769f45157771c8a65b6e0e
Images taken from web ([Link]
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Packaging Assembly Process Flow
Die Stack Encapsulation
Substrate Gold Wire
Solder ball
Fig: Various Components of a typical IC Package
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount Electrical
Substrate + DCA Test
(Optional)
DCA: Direct Chip Attach 5
Assembly Process Flow
Die Bank Wafer Detape Die Attach
Substrate
with
Capacitor /
Controller
Attach
Wafer Tape
Laser Groove
Oven Cure
Plasma Clean 1
Wire Bond
Wafer Thinning
Wafer Saw
Wafer Mount
Plasma Clean 2
Ref 1:Disco inc, [Link] [Link]
Ref 2: [Link]
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Assembly Process Flow
Solderball Attach
Solder Flux printing
Encapsulation
Solder Ball Attach + Reflow
Singulation
BGA Bake
Laser Scribe Vision / Open Short Test Assembly Complete
Credit: [Link]
[Link] 7
[Link]
Why Memory/Semiconductor Packaging is Challenging
• Memory packages Deals with die thickness ranging from 300 um – 30um (Incoming wafer thickness 800-900 um)
Wafer Grinding – 30 -150 um Die Attach 1D – 32D
Wire Bond – ~ 400 wires 15-18 um Mold – Powder Molts Compression (PMC)
Credit: Photos taken from WEB
[Link]
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 9
Process Flow - Thinning
• A series of processes to remove excess silicon material from a wafer to achieve its required thickness.
• Generally, consist of the following subsidiary processes:
Wafer Tape Backgrind Polish (Optional)
Wafer
Thickness
Wafer Detape Wafer Mount Measurement
• Back grinding is the main process that remove excess silicon material
• Polishing removes the mechanical damages generated by thinning; typically used for thin wafer applications
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Wafer Dicing
• Wafer Dicing : A process of singulating wafer into individual dies for electronic packaging
Ref:
Hamamatsu Photonics
Fig: Various Dicing Technologies Disco
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 12
Die Attach
• Die attach is the process of removing singulated dies from the wafer and attaching them to the interposer
by use of adhesive (Die attach film).
Types of Adhesives
➢ Die Attach Film (DAF)
- Taped onto the back of the wafer/die
- certain DAFs will need oven cure after die attach
➢ Film Over Wire (FOW)
- taped onto the back of the wafer/die
- needs oven cure after die attach
➢ Epoxy paste
- dispensed onto the interposer
- needs oven cure after die attach
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Die Stacking Configurations
Wire-bond location
OR
Direct Shingled Stack Reverse Shingle on Shingled on Shingled Stack Flip-flop Stack Same Size Die Stacking
shingled Stack (RSOS)
Factors influencing die stacking configuration:
• Die size • Assembly process • Cost
• Package size • Substrate design
• Die bond pad location • Package warpage
• Signal integrity • Package reliability
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulatio Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) n and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 15
Plasma Treatment/Cleaning
• Plasma cleaning will be used to remove organic contaminants from surface
✓ Plasma before wire bond to remove the contaminants any on bond pads
✓ Plasma before Mold towards surface modification and contaminants removal
Fig: Plasma Cleaning at strip level
Credit: [Link]
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulatio Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) n and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 17
Wire Bond Process (Capillary assisted Thermosonic Bonding)
Wire bond is a Interconnect technology – to electrically connect semiconductor die to Substrate
Wire Bonding Sequence
1st Bond
Free Air Ball Looping
2nd Bond
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[Link]
Impact on stack-up on DA and Wirebond passes
SBS 8DS
1 pass DA + 1 pass WB
2x8RSOS
2 pass DA + 2 pass WB
4x4RSOS
4 pass DA + 4 pass WB
DA: Die Attach
WB: Wirebond
SBS: Side by SIDE
SOS- Shingle on Shingle
8x2RSOS
RSOS: Reverse Shingle on Shingle 8 pass DA + 8 pass WB
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
Treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 20
Encapsulation Process
Encapsulation as its name suggest, it is to form a protection barrier of epoxy mold compound to cover up the
silicone die and wire in the memory chip.
Moisture barrier Heat transfer
Encapsulant
(Epoxy resin)
Medium for laser
Electric insulator mark
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 22
Laser Mark Process
Laser Mark process is to mark the identity of the package.
2DID – Individual package identification
1) Pin 1 – Package Orientation Package
2) Lot Trace Code (LTC) - Lot level identification Before
3) Reject - Marking of reject unit Process
2 Types Laser technology that we are using
1) Green Laser
2) Red Laser REJECT UNIT GOOD UNIT
Process control
Laser mark readability Package
Laser Mark Depth After
Process 4
1
3
2
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
Treatment Treatment
Die
Preparation Die Attach Wire Bond Automated
Incoming Encapsulatio Laser Mark Ball Attach Singulation Visual
(Interconnect
Wafer (Thinning (and Cure) n and Baking Inspection
)
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 24
Ball Attach Process
• Ball Attach is to attach the solder balls permanently on the ball pads of the interposer
• This is achieved with temperature reflow (application of pre-determined heat for a duration of time) after
solder balls have been placed on the ball pads.
• The solder ball will form a metallic joint with the ball pad
Process control: Solder Ball Shear
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Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 26
Singulation Process
• Singulation is the separating process of the BGA package into individual units from its strip/ interposer form.
(Cutting a chocolate bar into individual chocolate)
Strip/ Interposer Individual packages &
Singulation/ Sawing
offload in tray
• There are two types of sawing technology that we are using
Ball Up Singulation Ball Down Singulation
Process control:
Package Dimension X & Y (Customer form fit function)
Images from web
[Link] 27
Packaging Assembly Process Flow
Fig: Semiconductor Wafer to IC Package
Plasma Plasma
treatment Treatment
Die
Preparation Die Attach Automated
Incoming Wire Bond Encapsulation Laser Mark Ball Attach Singulation Visual
Wafer (Thinning (and Cure) (Interconnect) and Baking Inspection
and Dicing)
Surface Mount
Substrate + DCA
(Optional)
Electrical
Test
DCA: Direct Chip Attach 28
OS Vision Process
Assembly Test
AVI
What do we do?
Pkg Outline Measurement:
• Ball Diameter, Height, Package X, Y , Z, coplanarity, warpage, pitch X Y etc
Package Visual Inspection (PVI) Inspects for gross external package defect
caused by:
• OS Testing
• Upstream processes (Encapsulation, Laser, Ball Attach, Singulation)
OS: Open Short Test
AVI: Automated Visual Inspection
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References
[Link]
[Link]
OF-Mokhtar-Rasid/bc2ba8c870f31f79b5769f45157771c8a65b6e0e
[Link]
Disco inc : [Link]
[Link]
[Link]
[Link]
[Link]
[Link]
[Link]
[Link]
[Link]
[Link]
Some images courtesy to public web material.
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