Verilog Testbench for 2x1 Multiplexer

The document describes a testbench module for a 2-to-1 multiplexer using three different modeling styles: gate-level, data flow, and behavioral. It includes variable declarations, instantiation of the design under test, and stimulus generation for testing the multiplexer functionality. The testbench monitors the input and output values during simulation to verify the correct operation of the multiplexer.

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Verilog Testbench for 2x1 Multiplexer

Uploaded by

pranavsrinivasan88

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Download as DOCX, PDF, TXT or read online on Scribd

TESTBENCHMODULE

DESIGNMODULE (Behavioral)
module Testbench_mux2x1();
module Gate_Level_Modeling_mux2x1(x1,x2,s,f);
//variable or port declaration
input x1,x2,s;
reg x1,x2,s;
output f; wire f;

wire s0,w0,w1; //Instantiation Design Under Test

not n1(s0,s); Gate_Level_Modeling_mux2x1 dut(x1,x2,s,f);

//Monitoring the values

and a0(w0,s0,x1);
initial begin
and a1(w1,s,x2);
$dumpfile("[Link]");
or o1(f,w0,w1); $dumpvars;
endmodule $monitor("s=%b | x1=%b | x2=%b | f=%b",s,x1,x2,f);

end
DESIGNMODULE (Data Flow)
//generating the stimuli
module initial begin
Data_Flow_Modelling_Style_mux2x1(x1,x2,s,f);
s=1'b0; x1=1'b0; x2=1'b0;
input x1,x2,s; #5 x1=1'b1;
output f; #5 x1=1'b0;

assign f = (~s & x1)| (s & x2); #5 x1=1'b1;

#5 x2=1'b1;
endmodule
#5 x2=1'b0;

DESIGNMODULE (Behavioral) #5 s=1'b1;

module Behavior_Modelling_If(x1,x2,s,f); #5 x2=1'b1;

input x1,x2,s; #5 x2=1'b0;

output reg f; #5 x1=1'b0;

always@(x1,x2,s) #5 $finish;

end
begin
endmodule
if(s)
f=x2;
else if(!s)
f=x1;
end
endmodule

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Verilog Testbench for 2x1 Multiplexer

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Verilog Testbench for 2x1 Multiplexer

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TESTBENCHMODULE

wire s0,w0,w1; //Instantiation Design Under Test

not n1(s0,s); Gate_Level_Modeling_mux2x1 dut(x1,x2,s,f);

//Monitoring the values

assign f = (~s & x1)| (s & x2); #5 x1=1'b1;

DESIGNMODULE (Behavioral) #5 s=1'b1;

module Behavior_Modelling_If(x1,x2,s,f); #5 x2=1'b1;

input x1,x2,s; #5 x2=1'b0;

output reg f; #5 x1=1'b0;

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