CPE3341: Digital System Design Lab

Design Lab # 4
Parameterized design in Verilog Behavioral Modeling
Objective : Lab #4 will familiarize students with more designs of digital circuits in
Verilog Behavioral Modeling. Students will also learn about how to write
parameterized modules in Verilog.

Tasks included in this Lab are :

1. Design behavioral model of an 8-bit adder/subtractor in Verilog HDL

2. Design behavioral model of an 8-bit accumulator in Verilog HDL

3. Design behavioral model of a parameterized Clock divider

4. Write a Stimulus to test the functionality of accumulator and clock divider

Complete your Lab Assignment in Lab and show the results to Lab Instructor.

4 Lab Assignment
Design of 8-bit Adder/Subtractor
(a). Create a new ModelSim project. Project will simulate a 8-bit adder/subtractor Module in
behavioral Modeling

(b). Add new file of type Verilog to the project. Write Verilog module for 8-bit adder/subtractor
in behavioral modeling in the file.

(c). Add new file of type Verilog to the same project. Write Stimulus module for testing and
verification of adder/subtractor in the file. Stimulus module should instantiate the 8-bit
adder/subtractor module.

Give four different combinations of inputs and select lines to the adder/subtractor module. Use
the $monitor to display all inputs and outputs of the design module.

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(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window. Also display adder/subtractor output waveform in waveform
window.

Verify the results and show them to the lab instructor

Below is circuit diagrams of adder/subtractor design schematic

Figure 22. 8-bit Adder/Subtractor Design Schematic

4.2 Design of an 8-bit Accumulator

(a). Create a new ModelSim project. Project will simulate an 8-bit Accumulator Module in
behavioral Modeling

(b). Add new file of type Verilog to the project. Write Verilog module for 8-bit Accumulator
with register, in behavioral modeling in the file.

Register in the accumulator will work on posedge of clock and will reset on negedge of reset
signal (active low reset).

(c). Add new file of type Verilog to the same project. Write Stimulus for testing and verification
of accumulator module in the file. Stimulus module should instantiate the 8-bit Accumulator
module.

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(d). Compile the project and correct any syntax errors. Next simulate the project and display
results in output window.

Verify the results and show them to the lab instructor

Below is circuit diagram of 8-bit Accumulator with select line and register

Figure 23. 8-bit Accumulator Schematic

4.3 Design of a parameterized Clock Divider

Write Verilog behavioral Module for a generalized clock divider that uses Verilog construct
‘parameter’ to make a generalized clock divider. By default clock divider should divide input
clock by 8. Instantiate three instances of clock divider module in Stimulus module. First instance
should divide input clock by 8, second instance should divide by 10 and 3 rd instance should
divide input clock by 20.

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(a). Create a new ModelSim project. Project will simulate a clock divider Module in behavioral
Modeling and will use Verilog ‘parameter’ to write parameterized clock divider code

(b). Add new file of type Verilog to the project. Write Verilog module for clock divider in
behavioral modeling in the file. Clock divider should divide input clock by 8 i.e. Output clock
frequency should be (Input Clock Freq.) / 8.

NOTE: Verilog Code for clock divider module will have following I/O ports :

// Clock Divider module in Verilog HDL

moduleClockDivider(clkin, clkout, reset);

parameterdividefactor = X; // Calculate X for 8 , 10 and 20

inputclkin , reset;
outputclkout;

...
...

endmodule

(c). Add new file of type Verilog to the same project. Write Stimulus for testing and verification
of clock divider module in the file. Stimulus module will generate active low Reset & input
Clock Signals .Stimulus will instantiate 3 instances of clock divider module. Instance 1 will
divide input clock by 8, Instance 2 will divide by 10 and instance 3 will divide by 20.

(d). Compile the project and correct any syntax errors. Next simulate the project and display
timing wavefors of Input an output clocks.

Verify the results and show them to the lab instructor

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 Design Lab # 4

Lab Assignments
Activity# 01

• Create a new project in ModelSim, add the files containing adder/subtactor module and
Stimulus module to the project
• Compile and run the simulation of 8-bit adder/subtractor in ModelSim
• Display inputs and outputs of 8-bit adder/subtractor using $monitor. Also show timing
waveforms to Lab Instructor

Activity# 02

• Write Verilog code in behavioral modeling for 8-bit accumulator

• Write Stimulus module to verify your accumulator design. Stimulus module should give
inputs to design module and display corresponding outputs using $monitor.
• Compile and run the simulation in ModelSim and display output waveforms as well

Activity# 03

• Write behavioral verilog module for generalized Clock Divider. Also write its Stimulus
in Verilog. Stimulus will instantiate 3 different instances of Clock Divider
• Create a ModelSim project, add Clock divider module and its stimulus to project
• Compile and run the simulation of Clock Divider in ModelSim and display/verify
outputs

Lab Check-Off

• Demonstrate your design and show outputs and wave window saved file for each Task
to Lab Instructor

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 Design Lab # 4
Lab Report
Student Name:_____________________ Reg. #________________

NOTE : Each Lab report will be submitted in hand written form

Answer the following :-

1. Explain objective of the Lab and outline the Lab tasks

2. Explain functionality of each Task implemented in the Lab

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 3. What is the difference between === and == ?

4. What is the difference between unary and logical operators ?

5. Draw waveform of input and output of a clock divider that divides input
clock by 4

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 Lab Exercise and Summary

Summary should cover Introduction, Procedure, Data Analysis and Evaluation.

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Student’s Signature: ________________ Date: ________________

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 LABORATORY SKILLS ASSESSMENT (Psychomotor)
Total Marks: 100

Criteria Level 1 Level 2 Level 3 Level 4 Score

(Max Marks) 0% ≤ S < 50% 50% ≤ S< 70% 70% ≤ S< 90% 90%≤ S ≤100% (S)
Procedural Selects Selects and applies Selects and applies Selects and
Awareness inappropriate appropriate skills the appropriate applies
(20) skills and/or and/or strategies strategies and/or appropriate
strategies required by the skills specific to the strategies and/or
required by the task with some task without skills specific to
task errors significant errors the task without
any error
Practical Makes several Makes few critical Makes some non- Applies the
Implementation critical errors in errors in applying critical errors in procedural
(30) applying procedural applying procedural knowledge in
procedural knowledge knowledge perfect ways
knowledge
Safety Requires constant Requires some Follows safety Routinely follows
(10) reminders to reminders to follow procedures with safety procedures
follow safety safety procedures only minimal
procedures reminders
Use of Uses tools, Uses tools, Uses tools, Uses tools,
Tool/Equipment equipment and equipment and equipment and equipment and
(20) materials with materials with materials with materials with a
limited some competence considerable high degree of
competence competence competence
Participation Shows little Demonstrates Demonstrates Actively helps to
to Achieve commitment to commitment to commitment to identify group
Group Goals group goals and group goals, but group goals and goals and works
(10) fails to perform has difficulty carries out assigned effectively to
assigned roles performing roles effectively meet them in all
assigned roles roles assumed
Interpersonal Rarely interacts Interacts with other Interacts with all Interacts
Skills in positively within a group members if group members positively with all
Group Work group, even with prompted spontaneously group members
(10) prompting and encourages
such interaction
in others

Marks Obtained

Instructor’s Signature: ________________ Date: ________________

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 LABORATORY SKILLS ASSESSMENT (Affective)

Total Marks: 40

Criteria (Max. Level 1 Level 2 Level 3 Level 4 Score

Marks) 0% ≤ S < 50% 50% ≤ S < 70% 70% ≤ S < 90% 90% ≤ S ≤ 100% (S)
Introduction Very little Introduction is brief Introduction is nearly Introduction complete
(5) background with some minor complete, missing some and well-written;
information mistakes minor points provides all necessary
provided or background principles
information is for the experiment
incorrect
Procedure Many stages of the Many stages of the The procedure could be The procedure is well
(5) procedure are not procedure are more efficiently designed and all stages
entered on the lab entered on the lab designed but most of the procedure are
report. report. stages of the procedure entered on the lab
are entered on the lab report.
report.
Data Record Data is brief and Data provides some Data is almost complete Data is complete and
(10) missing significant significant but has some minor relevant. Tables with
pieces of information and has mistakes. units are provided.
information. few critical Graphs are labeled. All
mistakes. questions are
answered correctly.
Data Analysis Data are presented Data are presented Data are presented in Data are presented in
(10) in very unclear in ways (charts, ways (charts, tables, ways (charts, tables,
manner. Error tables, graphs) that graphs) that can be graphs) that best
analysis is not are not clear understood and facilitate
included. enough. Error interpreted. Error understanding and
analysis is included. analysis is included. interpretation. Error
analysis is included.
Report Report contains Report is somewhat Report is well organized Report is well
Quality many errors. organized with and cohesive but organized and
(10) some spelling or contains some cohesive and contains
grammatical errors. grammatical errors. no grammatical errors.
Presentation seems
polished.

Marks Obtained
LABORATORY SKILLS ASSESSMENT (Cognitive)

Total Marks: 10
( If any )
Marks Obtained

Instructor’s Signature: ________________ Date: ________________

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