Chapter 4: Theory of

Operation

This chapter describes the theory of operation for the Card Affixer module.

Introduction 4-2

System Overview 4-2

General Functional Description 4-4

Mechanical Sequence 4-4
Production Cycle Sequence (Standard Speed) 4-5
Electrical Sequence 4-7
Standard Speed Card Affixer Module Electrical Block Diagrams 4-7
Card Affixer Control Board Detailed Block Diagrams 4-9
Sensor Interface 4-11
Power Amplifiers 4-13
Power Requirements 4-14
Card Affixer Module CB Parts Description 4-15
Form Buffer Electrical Description 4-17
System Processor 4-17
Memory 4-18
Logic Control 4-18
System Interface 4-18
Sensor Interface 4-18
Stepper Motors 4-18
Power Supply 4-18
Interlock 4-18
Electrical Theory 4-19
System Power Interconnect 4-19
Circuit Schematics 4-21
High Speed Card Affixer Module Electrical Block Diagrams 4-48
High Speed UltraForm System Power Interconnect 4-49
High Speed UltraForm System DC Block Diagram 4-50
High Speed UltraForm Interlock System Block Diagram 4-51
High Speed UltraForm System Cabling Diagram 4-52

Card Affixer Module Maintenance Manual 4-1

Introduction
This chapter provides a general overview of the mechanical and electrical functions
of the Card Affixer module and optional Form Buffer for duplex printing. The
overview includes mechanical sequence, electrical sequence, and electrical block
diagrams. Also included is a detailed theory of operations including wiring
diagrams, signal flow diagrams, and functional schematics.

System Overview
The Card Affixer module is an electro-mechanical device used to apply from one
through six cards onto a form. The Affixer is controlled by the Control Board (CB).
The optional Form Buffer (for duplex printing), also an electro-mechanical device, is
controlled by its own PCB.

The Card Affixer consists of the following major assemblies (refer to Figure 4-1 and
Figure 4-2):

• Main cabinet
• Affixer Mechanism
• Control Board (CB)
• +24V DC power supply (Standard Speed)
• +36V DC power supply (High Speed)
• Form Buffer (Optional Duplex Printing)
Operation and control of the Transport In, Servo Motor Control, and Transport Out
consists of the following major electrical functions:

• AC power distribution
• DC power distribution
• System interface between the Card Affixer and Controller modules.
• Control board to drive module prime movers, receive sensor inputs, and
provide data to the interface.
• Steppers and DC motors to drive the Card Affixer card transport.
• Solenoids to affix cards and divert paper to the unfolded forms tray.
• Photocell sensors to return mechanical status to the CB.

4-2 Theory of Operation

 Intermediate Entry
Roller
Assembly Roller
Assembly
Rotary Mechanism
Exit
Roller
Assembly

Unfolded Forms
(Bypass) Drive
Assembly

Unfolded Forms
(Bypass) Tray

34870-94

Card
Carriage
Assembly Card
Entry

Figure 4-1: Card Affixer Module Major Mechanical Assemblies

Cover and Upper Paper
Guide Assembly

Entry
Guide Assembly

Controller Board
Assembly
64350-8

Figure 4-2: Form Buffer Module Major Mechanical Assemblies

Card Affixer Module Maintenance Manual 4-3

General Functional Description
The general functional description includes a mechanical sequence description with
simplified mechanical diagrams and an electrical sequence description with
functional block diagrams.

Mechanical Sequence
The purpose of the Card Affixer mechanical parts and optional Form Buffer
attachment is to supply a printed form to the Folder mechanism with from one
through six cards affixed to the form, double-fold the form, and then deposit the
completed form into the reject or good form stack (or place the completed form into
an envelope and stack the envelopes if the Stuffer option is present).

This operation, called the production cycle, requires a distinct sequence of events as
shown in Figure 4-3.

5 7 8 10 12
3
1
15E

15C 15D

14B

14A

9 11 14B
4

14A
4 15B
34870-91
4 14A
15A 15E
14A 14B

14B

Figure 4-3: Card Affixer Module Mechanical Sequence

4-4 Theory of Operation

Production Cycle Sequence (Standard Speed)
Figure 4-3 represents a cutaway of the basic mechanical and electro-mechanical
components resident in the Card Affixer assembly required to transport a printed
form to the folder. The sequence of events for this move are:

1. Start the paper entry roller motor.

2. Start the bed vacuum fan motor.
3. Wait until a form blocks the paper entry sensor. If a form does not block this
sensor within twenty seconds, an error is returned to the CIS Controller.
4. Start the main paper drive roller motor to move the form to the "home" position
on the bed. The "home" position is the point at which the bottom edge of a card
lines up with the bottom edge of the paper.
5. Wait for a card to fully enter the card carrier mechanism. If the card does not
fully enter the carrier, an error is returned to the CIS Controller.
6. If the paper must be moved to correctly position the card, start the paper
moving toward that position.
7. Start moving the card carrier away from the home position. After a short
movement away from the carriage home position, the card starts rotating down
to a 45° angle.
8. After the paper stops moving, the card carrier rotates down an additional 45° to
make the card parallel to the bed.
9. The card affixing solenoid fires to release the card from the carrier and press the
card against the bed with the card affixing roller.
10. The card carrier moves back toward its home position with the card affixing
roller pressing down on the card.
11. After the Card Affixer roller moves across the entire width of the card, the card
affixing solenoid is released.
12. The card carrier rotates up to the vertical position at the same time the carrier
moves back to its home position.
13. Steps 5 through 12 repeat until all cards are affixed to the form. Then steps 14 or
15 move the form out of the Card Affixer.
14. Moving the form to the folder mechanism involves the following steps:
a. Start the main paper drive roller motor.
b. Stop the main paper drive roller motor when the form blocks the paper exit
sensor. If the completed form does not reach this sensor, an error is reported
back to the CIS Controller.
c. When an eject command is received from the Controller PC, the main paper
drive motor is started to move the form out of the Card Affixer. If the form
does not clear the paper exit sensor, an error is reported back to the CIS
Controller.

Card Affixer Module Maintenance Manual 4-5

 d. Turn off the main paper drive motor.
15. Moving the form to the unfolded forms tray involves the following steps:
a. Energize the unfolded forms diverter solenoid. This raises the "fingers" that
direct the form to the unfolded forms tray.
b. Start the main paper drive roller motor.
c. Start the unfolded forms drive roller motor.
d. After the paper has had enough time to clear the upper tray paper sensor
switch, the state of the switch is checked. If the switch indicates that the tray
is full or the form did not reach this sensor, an error is reported back to the
CIS Controller.
e. Turn off the paper drive motors and the diverter solenoid.
Figure 4-4 represents a cutaway of the basic mechanical and electro-mechanical
components resident in the Form Buffer assembly required to transport a printed
form to the Card Affixer. The sequence of events for this move are:

1. Start the paper entry roller motor.

2. Wait until a form blocks the paper entry sensor. If a form does not block this
sensor within twenty seconds, an error is returned to the CIS Controller.
Start the main paper drive roller motor to move the form to the "home" position on
the bed.

Form Buffer Form Buffer

2 Sensor 3 Sensor

Form Buffer
Entry Sensor
64350-5
Form Buffer Form Buffer
2 Motor 3 Motor

Figure 4-4: Form Buffer Module Mechanical Sequence

4-6 Theory of Operation

Electrical Sequence
The controller board is responsible for properly sequencing a card through the
production cycle as determined by the configuration of the system and software
commands. The actual sequence and signal timing associated with card movement
for the production cycle is described for each module in the Theory of Operation
Chapter for each of the modules and at the system level in the 9000 system Theory of
Operation Chapter.

The information below describes the electrical theory of operation for the
Standard Speed Card Affixer Module. This information is then followed by an
electrical theory of operation for the High Speed Card Affixer Module (see Page
4-48).

Standard Speed Card Affixer Module Electrical Block Diagrams

The electrical block diagrams for the Standard Speed Card Affixer module are
described in the following section.

Figure 4-5 represents the Standard Speed Card Affixer system block diagram.

The Power Supply and Printer are supplied OEM items. See manufacturer’s data
for circuit information.

Card Affixer Module Maintenance Manual 4-7

 PSD503
64K X 16 Eprom
80C186 Microprocessor Address Latch
Address Decoding
4 Sixteen Bit Timers

RAM

Note: Components may not be populated JP9

for Card Affixer Module Parallel Port
TL16C552
RS-232
RS-232 JP8
80C152 PSD301 Interface
Microprocessor 32K Eprom Port
RS-232 U58
Interface JP7

Sensor Interface
BIF 32K XILINX#2 U4, U5, U6, U7
Interface SRAM U12
62256 JP15 JP15
X8 X8

Power Amp Units

U23, U24, U37, U43, U44
BIF Out BIF In
JP4 JP3 JP17 JP18 JP19

JP12 ADC
Current Sense
U31
XILINX#1 Control Unit
U13 U3, U19, U40

Power Amp 1 Power Amp 2 Power Amp 3 Power Amp 4

U18, U25 U26, U27 U8, U9, U10, U11 U14, U15, U16, U17

JP13 JP14 JP11 JP10

34870-4-2

Figure 4-5: Card Affixer System Block Diagram (Standard Speed only)

4-8 Theory of Operation

Card Affixer Control Board Detailed Block Diagrams

The design of the UltraForm Control Board (CB) is a collection of two

microprocessors, several amplifiers to power up electromechanical actuators, sensor
interface circuitry, high speed and RS-232 serial communication, an IBM PC
compatible parallel port, an 8-bit high speed A/D converter. The design is flexible
because of the nature of the control hardware. The FPGA technology is used in this
design to provide a considerable flexibility in the configuration of this board for
various applications. Figure 4-6 shows a block diagram of the CB.

Microprocessor

The Control Board includes a 80C186 microprocessor.

80C186 Microprocessor:

The 80C186 microprocessor controls the following items:

• Two Xilinx chips U12 and U13.

• PSD503 U20.
• Sensor interface IC’s MAX516’s. U4, U5, U6, U7.
• Current Reference IC’s U3, U19, U44.
• An eight-bit analog to digital converter (ADC) U31.
• Two channel serial port and an eight-bit parallel port U51.
• An eight-bit parallel port between the 80C152 and the 80C186.

Card Affixer Module Maintenance Manual 4-9

 Paper Input Pin 6
Paper First Interm Pin 16
Paper Second Interm Pin 26
Paper Out Pin 36
Paper Reject Tray Full Pin 5
Card Rotary Home Pin 35
Card Verification LeftPin 15
Card Verification RightPin 25

Card Sticker Output Pin 26

Card Input Pin 6
Card Carriage Home Pin 16

Figure 4-6: Card Affixer Control Board Detailed Block Diagram (Standard Speed)

XILINX U12

A XC3042 device is used to provide control to the power amps U24, U37, U23, U43,
U44 a 12-bit sensor interface unit, two momentary contact switches and a seven-
segment LED (Light Emitting Diode), and an eight-bit bi-directional bus interface to
the 80C186 microprocessor. The seven-segment LED is a low current common
collector LED and is placed in U58. The two momentary switches are located at S1
and S2.

4-10 Theory of Operation

XILINX U13

A XC3042 device is used to provide control to the power amps U18, U25, U26, U27,
U8, U9, U10, U11, U14, U15, U16, U17. An eight-bit parallel port between the 80C152
and the 80C186 is controlled by U13. The four-bit output of the 16-bit timers from the
PSD503 device is terminated to U13. The external address decoding of the amplifier
current sensors are connected to the U13.

PSD503

PSD503 from WSI is used as the 64Kx16 EPROM, address latch for the 17-bit MUX
address and data bus of the 80C186, the four 16-bit timers to control stepper motors,
address decoding logic to control the U3, U19, U40 and the U31 (ADC) programming
the Xilinx device. The pin description for this device is given in Table 4-1.

RS-232 Communication Interface

U51 is universal communication interface protocol that is used to provide two serial
RS-232 communication channel and an eight-bit PC compatible PARALLEL port.
The PCS4 through PCS6 is used to control the chip selects on U51. The two serial
port on U51 are connected to U46 and U47, the MAX233 chips, to provide RS-232
compatible interface to the outside users. The RS-232 connection to these ports are on
JP7 for comm channel two and the JP8 for comm channel one. The parallel port for
this device is connected to JP9.

Sensor Interface
There are sixteen sensor inputs to the Affixer CB on JP15 and JP16. JP15 and JP16
each handles eight inputs. The sensor outputs are terminated by a 4.7 K pull-up to +5
VDC. In addition there is a drive resistor of 200 ohms as an output to drive a given
sensor if needed. Also there a is +5V DC supply to each sensor if a sensor needs a
supply. Figure 4-7 shows a typical sensor interface to the Card Affixer module CB.

Card Affixer Module Maintenance Manual 4-11

 TYPICAL SENSOR CONTROL BOARD

+5 V +5 V +5 V
SENSOR SUPPLY

200 Ohms 4.7K Ohms

SENSOR DRIVER

SENSOR OUTPUT

GROUND

Figure 4-7: Typical Sensor Termination

The output of each sensor is terminated to the sensor interface IC’s U4, U5, U6 and
U7. The sensor interface IC’s are MAX516. MAX516 is a quad comparator with eight-
bit software programmable threshold. Threshold for the COMPARATOR is under
software control. In this schematic, the input from each sensor input is monitored
and an optimum threshold is set for a given sensor. Figure 4-8 shows a typical sensor
interface to the sensor interface unit. The twelve sensor output signals from U5, U6,
and U7 are terminated to the Xilinx U12 and the remaining four sensor output
signals from U4 are connected to the P6.0 to P6.3 of the U52 the 80C152. The
schematic on Figure 4-12 shows the connections of these sensor units.

+5 V

FROM SENSOR INPUT

DIGITAL OUTPUT

8 BIT BUS ADC

FROM 80C186 SENSOR THRESHHOLD
VOLTAGE

Figure 4-8: Typical Sensor Threshold Detect

Sensor Adjust PWB

The Sensor Adjust PWB is designed to provide four inline sensor LED current
adjustment and phototransistor output test points. This assembly is placed in-line
with the sensor cable assembly connected to either JP15 or JP16 on the Card Affixer
CB. VR1 to VR4 control the sensor LED currents for the first four connected
to the even side of the 40-pin connector. Reference the following tables for the
location and description of each variable sensor:

4-12 Theory of Operation

 JP16

Sensor Variable Resistor Testpoint

Form Input VR1 TP1
Form First Intermediate VR2 TP2
Form Second Intermediate VR3 TP3
Form Output VR4 TP4

JP15

Sensor Variable Resistor Testpoint

Card Entry* VR1 TP1
Carriage Home* VR2 TP2
Sticker Exit* VR3 TP3
Form Entry VR4 TP4

* Wiper on variable resistor should be zeroed to avoid interfering with normal

operation of these sensors.

Analog to Digital Converter (ADC) Control Unit

An eight-bit high speed ADC (Analog to Digital Converter) MAX153 is used to
convert analog input signal to an eight-bit digital form. The input to this device is
from 0 to +5 VDC. The conversion rate of this ADC is at 2µsec. The ADC is located at
U31. The reference voltage for the ADC is set at +5 VDC. The input to the amplifier
is buffered from the U50A. U50A is a rail-to-rail operational amplifier MC34072. The
amplifier is configured as a voltage follower type. The input to this amplifier is from
JP12. The input to the amplifier from pin 1 of the JP12 is pulled down to the ground
voltage by a 6.04K resistor. Pin two of the JP12 is pulled to +5 VDC by a 220-Ohm
resistor. The Figure 4-23 schematic shows all the connections to this device. The
input impedance of the JP12 is set up for a thermocouple interface.
Power Amplifiers
There are seventeen L6203 power amplifiers on this board (U8, U9, U10, U11, U14,
U15, U16, U17, U18, U23, U24, U25, U26, U27, U37, U43, U44). U8, U10 and U9, U11
and U14, U15, and U16, U17 are connected in parallel so the current rating for pairs
of amplifiers is doubled. U44 is connected in a voltage mode. Resistor R101 is used
as a limiting resistor for a short circuit protection. U18, U23, U24, U25, U26, U27, U37
and U43 are connected as an individual amplifiers. The operation of each amplifier is
programmed by U12 and U13. Except U44 the reset of these amplifiers could be
configured to operate as a voltage source or current source amplifiers. In the current
mode the current reference to these amplifiers are set by the three eight-bit quad
DAC’s (Digital to Analog Converters) U3, U19 and U40. The reference voltage to
these DAC’s are at 2.5 volts. The current gain from the DAC’s to the amplifier is two.
With this gain ratio the maximum attainable current from the amplifiers are limited

Card Affixer Module Maintenance Manual 4-13

 to five amps. LM336 (U48) is used as a precision voltage reference. The output of the
LM336 is buffered through the U50B operational amplifier to source the +VREF at
2.5 volts. Refer to the schematic on Figure 4-23 for the detail drawings of the DAC’s.
Figure 4-17, Figure 4-19, Figure 4-20, Figure 4-21, and Figure 4-22 show each
amplifier.
Power Requirements
The power input to the Card Affixer module is a +24 VDC at the JP1. A switching
DC to DC converter converts the +24 VDC to +5 VDC for the logic and sensory
inputs. The +5 VDC switching power supply is LT1074, U4 which is a 5-amp
regulated power supply. The +24 VDC is divided into two separate power sources as
+24 V1 and +24 V2 by the relays K1 and K2. K1 and K2 are controlled by the
interlock switch connected through the BIF connection and controlled from JP2. The
+24 V1 and +24 V2 are the power source for all the power amps on the boards. In the
case of an interlock connection being opened, the +24 V1 and +24 V2 are
disconnected but the +24 VDC and the +5 VDC are available on each board. There
are four LED’s (Light Emitting Diodes) on the board: D22, D17, D20, D21. They are
connected to the +24 VDC, +24 V1, +5 VDC and +24 V2, respectively. If the LED’s
D22, D17, D20 and D21 are lit, the respective power to the board is available. The
table below shows summarizes the power requirements to the CB.
Power Requirements Input +24 V
Power Available On The Board +24 V1, +24 V2, +5 VDC @ 5 AMPS

4-14 Theory of Operation

Card Affixer Module CB Parts Description
The CB is configured to operate the CA module by programming the Xilinx chips
U12 and U13. The basic electrical requirements for this module are summarized in
Table 4-1. The communication between the Card Affixer module and the Controller
PC is done on the serial communication chip U51. The U52, U53, U55, U56, U57, U59,
U60, JP3, JP4, JP12 and K3 are optional for Card Affixer module.

Table 4-1: Card Affixer Module CB Parts Description

Item Description Terminal Connection

1- Stepper Motor Card Carriage Motor CONNECTION AT JP10
CURRENT REF : CUR_REF4
CURRENT REF : CUR_REF5
2- Stepper Motor Card Rotary Motor CONNECTION AT JP11
CURRENT REF : CUR_REF6
CURRENT REF: CUR_REF7
3- Stepper Motor Paper Entry Motor CONNECTION AT JP13
CURRENT REF : CUR_REF0
CURRENT REF : CUR_REF1
4- Stepper Motor Main Drive Motor CONNECTION AT JP14
CURRENT REF : CUR_REF2
CURRENT REF : CUR_REF3
5- Stepper Motor Upper Tray Motor CONNECTION AT JP18
CURRENT REF : CUR_REF8
CURRENT REF : CUR_REF9
1- Solenoid Card Affixer Solenoid CONNECTION AT JP19
PINS 1 AND 2
2- Solenoid Upper Tray Diverter CONNECTION AT JP19
Solenoid PINS 3 AND 4
1- DC Motor Fan Control Motor CONNECTION AT JP17
16 Sensor Input Form Input JP16 PIN 6
Form First Intermediate JP16 PIN 16
Form Second Intermediate JP16 PIN 26
Form Output JP16 PIN 36
Form Reject Tray Full JP16 PIN 5
Card Affixer Output JP15 PIN 26
Card Input JP15 PIN 6
Card Rotary Home JP16 PIN 35
Card Carriage Home JP15 PIN 16
Card Verification Left JP16 PIN 15
Card Verification Right JP16 PIN 25
1 Shared Output Sensor Card Affixer Output JP5 PIN 3 OUTPUT

Card Affixer Module Maintenance Manual 4-15

CB LED's

The LED's on the board edge provide quick operational indications of various
circuits in the module. The four LED's on the board’s edge are described below:

LED Marking Description

D17 This is a red LED on the board. Indicates that 24V power
is available to the CB.

D20 This is a red LED on the board. Indicates that 24 V1

power is available to the CB.

D22 This is a red LED on the board. Indicates that 24 V2

power is available to the CB.

D21 This is a red LED on the board. Indicates that 5V power is

available to the CB.

7-segment This is an alphanumeric red LED indicator. Electrically

there is no definition for its operation. Refer to the
operational software section for its description.

Power Supplies

The control board receives +24 VDC from an external +24 V DC power supply. The
control board converts the +24 VDC into +5 VDC and +12 VDC. These voltages are
then distributed throughout the control board.

The +12 volt supply is used to power the op-amps. This supply uses a three-
terminal linear regulator powered by +24 VDC.

The +5 volt supply is used to power the logic devices, sensors, and motor control
circuits in the module. This supply is a step down switching regulator with
overvoltage protection. The voltage conversion is provided by a switch mode
regulator (LT1074) device. This component integrates the regulator, power output
stage, and protection circuit. The few external components used by the regulator
are a coil, flyback diode, and configuration resistors. The coil stores energy
provided by the regulators pass transistor output stage. When the transistor is on,
the coil charges. When the transistor turns off, the coil discharges through the
flyback diode and charges the output capacitor, providing power to the output
circuits. The resistor/capacitor connected to the control chip establishes the
switching frequency and protection circuit trip points. When an overvoltage
condition occurs, the control chip enables the SCR which clamps the +5 volts to
ground, protecting the output circuits from damage.

Stepper control circuit

The stepper motors in the module transport the forms and cards to their
appropriate places in the machine. These motors provide an incremental method

4-16 Theory of Operation

 of advancing the mechanisms. Motor control is based on the processors internal
control algorithm.

Form Buffer Electrical Description

The PCB within the Form Buffer is configured to control two stepper motors,
monitor the state of various sensors, control of a set of ultrasonic sensors and
interface to the PC within the Card Affixer (UltraForm PC). A block diagram for this
design is shown below.

STEPPER MOTOR #1

ULTRAFORM
RS232 STEPPER MOTOR #2
PC
COM 2 FORM BUFFER
INTERFACE PCB
598474-001
SENSORS POWER SUPPLY &
SENSORS INTERLOCK
INTERFACE

System Processor
An Intel 80C186 at 16 MHz is used as the microprocessor to control the PCB on the
Form Buffer. The figure below shows a block diagram for the PCB.
+24 VDC In Interlock

JP2 JP1

+24 VDC Input Interlock

Supply interface

+24 VDC1
Supply
+5VDC
Switching
Supply

System
RS-232
Interface JP6
Interface
RS-232

80C186 PSD 503

Microprocessor EPROM/SRAM
16Mhz Clock Logic

Logic Stepper
Control Motor
Xilinx Control

Stepper #1
Ultra JP10
Sensor Interface Sonic
Sense Stepper #2
JP11

JP3 Sensor Connections JP4

64340-1a

Card Affixer Module Maintenance Manual 4-17

Memory
64 K of EPROM is available as the program memory. An external 64 K of SRAM and
256 bytes of internal memory is available for data handling.

Logic Control
A XILINX logic array is used for the Stepper Motor Control and sensor interface.

System Interface
The RS232 communication channel on board of 16C552 is used as the system
interface between the CAPC and the buffer board.

Sensor Interface
There are four sensor channels available for the module. The sensors have thresholds
that are programmable by the software. The sensor interface is designed to support
optical, hall effect, and/or ultrasonic sensors. All sensors operate at +5VDC.

Stepper Motors
The PCB is designed to support two 3.9-amp stepper motors. The rate of current to
the stepper motors is under software control.

Power Supply
The Form Buffer control board receives +24 VDC from the Sticker Applicator
Module external +24 V DC power supply. The control board converts the +24 VDC
into +5 VDC and +12 VDC to provide power to the system microprocessor and
various support elements. These voltages are then distributed throughout the control
board. The current rating for the +5VDC is 5 AMPS maximum.

Interlock
The system interlock will control the +24VDC to the stepper motors.

4-18 Theory of Operation

Electrical Theory
The electrical description that follows includes a description of the Card Affixer
module circuits by function with associated diagrams and schematics.

System Power Interconnect

Figure 4-9 and Figure 4-10 represent the system power interconnect wiring for the
Card Affixer module.

Printer AC Cable
DC Power Cable
Black 4
DC Power Black 3
To Utraform Red 2
Module Red 1

+24V Out
AC Line Out Brown
ACL
AC Neutral Out Blue
ACN Ground
Green/Yellow
Chassis

PC

1 2 3 1 2 3 JP2
JP4
CB1
250VAC 5A 6A
Brown
AC Line In
Blue
AC Neutral In
Blue
AC Neutral In
Brown
AC Line In
JP3 JP1 JP1

AC Distribution Board 34870-21

598036-001

Figure 4-9: Standard Speed Card Affixer 230V AC Power Interconnect Diagram

Card Affixer Module Maintenance Manual 4-19

4-20
PRINTER SHEET
FEEDER

BULKHEAD BULKHEAD ULTRAFORM STCK AXFR FOLDER

P.S.
CONNECTOR CONNECTOR PC P.S. P.S.

1 2 3 1 2 1 2 1 2 1 2 1 2

JP4 JP2 JP4 JP2 JP4 JP2

1 2 3 1 2 3 BROWN BROWN BROWN
1 1 1 1 1 1 1
AC LINE POWER BROWN JP1 JP3 BLUE BLUE BLUE
WP1 2 2 2 2 2 2 2
POWER NEUTRAL FILTER BLUE BLUE BLUE BLUE
WP2 3 3 3 3 3 3 3
CORD GRND BROWN JP3 JP1 BROWN JP3 JP1 BROWN JP3 JP1
JP4 4 4 4 4 4 4 4

595743-012 598036-001 599887-001 599887-001

Figure 4-10: Standard Speed UltraForm AC Interconnect Diagram

DATACARD CORP.
Size Document Number REV
B 01
Date: September 1, 1995 Sheet of

Theory of Operation
Circuit Schematics
Figure 4-11 through Figure 4-27 represent the schematics for the Standard Speed
Affixer Control board. These schematics provide additional detail to the block
diagram shown in Figure 4-6.

Figure 4-28 through Figure 4-34 represent the schematics for the Form Buffer Control
board. These schematics provide additional detail to the block diagram shown in
Figure 4-6.

Card Affixer Module Maintenance Manual 4-21

4-22
MAIN_PROCESSOR_CONTROL_186 XILINX_1
WSI_T[0..3]
PG_DONE WSI_T[0..3] WSI_T[0..3] PG_DONE
XIL_CCLK XIL_CCLK XIL_DOUT
XIL_DIN PCS[0..6] XIL_DIN
SEN_INT PCS[0..6]
RST_186 186_D[0..15] RST_186
186_D[0..15] 186_D[0..15]
186_A[0..17] INTERLOCK
186_A[0..17] 186_A[0..17]
152_CB[0..3] XIL_CS 152_D[0..7]
186_RD 152_D[0..7]
186_WR 152_CB[0..5]
CLOCK_8M CLOCK_8M
CLOCK_16M 186_RD CUR_REF[0..11]
186_TMR0 186_WR
186_TMR1 CS_B[0..4]
CS_B[0..4] CS_B[0..4]
MFHS_M6.SCH
MFHS_M2.SCH

152_CB[0..3]
SENSOR_INTERFACE_UNIT
BIF_80C152_CONTROLLER CLOCK_8M
RST_186 152_CB[0..5] 186_WR
CLOCK_16M
PG_DONE 152_D[0..7]
INT_LCK1
INT_LCK2 PWR_CTL1 PCS[0..6]
RST_301 PWR_CTL2 186_A[0..17]
186_D[0..15]
SEN_I[0..15] DCDE_B[0..3]
SEN_I[0..15]
MFHS_M14.SCH
DCDE_B[0..3]
MFHS_M1.SCH
SEN_I[0..15]
XILINX_2
XIL_CCLK DCDE_B[0..3]
SEN_I[0..15]
PG_DONE
186_D[0..15]
186_A[0..17]
CLOCK_8M
CS_B[0..4]
XIL_DIN
186_WR
POWER_CONTROL 186_RD SEN_INT
RST_186 XIL_CS 186_TMR0
PWR_CTL1 XIL_DOUT 186_TMR1
PWR_CTL2 INTERLOCK RST_186
INT_LCK1 CUR_REF[0..11]
INT_LCK2
RST_301 MFHS_M7.SCH

CUR_REF[0..11]

DataCard Corp.
MFHS_M13.SCH
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
B 598324 A
Date: July 7, 1995 Sheet 1 of 17

Figure 4-11: Standard Speed Affixer CB Interconnect Diagram (Sheet 1 of 17)

Theory of Operation
 CLOCK_16M
PG_DONE
+5V LC10 CS_B[0..4]
2 1000pF CS_B[0..4]
CB45 186_A[0..17]
186_A[0..117]
1 3 .01UF

CB46 4 LC6 +5V

1 3 .01UF 3 9 U20 1000pF
59 17 186_AD0 186_AD0 9 18 3 1
LC7 X1 V V AD0 186_AD1 186_AD1 AD0/A0 VCC
C C AD1 15 8 AD1/A1 VCC 52
2 1000pF C C 13 186_AD2 186_AD2 7 CB47
58 AD2 186_AD3 186_AD3 AD2/A2 186_A0 .01UF 2
X2 AD3 11 6 AD3/A3 PC0 17
8 186_AD4 186_AD4 5 16 186_A1
20 AD4 6 186_AD5 186_AD5 4 AD4/A4 PC1 15 186_A2
186_TMR0 TI0 AD5 186_AD6 186_AD6 AD5/A5 PC2 186_A3
186_TMR1 21 TI1 AD6 4 3 AD6/A6 PC3 14
2 186_AD7 186_AD7 2 13 186_A4
AD7 186_AD8 AD7/A7 PC4 186_A5
RST_186 24 RES AD8 16 PC5 12
47 14 186_AD9 186_AD8 68 11 186_A6 LC4
TEST AD9 12 186_AD10 186_AD9 67 AD8/A8 PC6 10 186_A7 1000pF
AD10 186_AD11 186_AD10 AD9/A9 PC7
18 DRQ0 AD11 10 66 AD10/A10 3 1
19 7 186_AD12 186_AD11 65 60 186_A8
DRQ1 AD12 186_AD13 186_AD12 AD11/A11 PD0 186_A9 CB43
AD13 5 64 AD12/A12 PD1 59
45 3 186_AD14 186_AD13 63 58 186_A10 .01UF 2
SEN_INT 44 INT0 AD14 1 186_AD15 186_AD14 62 AD13/A13 PD2 57 186_A11
INT1 AD15 186_AD15 AD14/A14 PD3 186_A12
A16/S3 68 61 AD15/A15 PD4 56
COM_INT0 42 67 55 186_A13
COM_INT1 INT2/TA0 A17/S4 PD5 186_A14
41 INT3/TA1 A18/S5 66 38 PE0 PD6 54
65 37 53 186_A15
55 A19/S6 36 PE1/ALE PD7
+5V ARDY 186_A16 PE2 WSI_T0
49 SRDY BHE/S7 64 34 PE3 PA0 27
46 61 33 26 WSI_T1
NMI ALE/QS0 PE4 PA1 WSI_T2
50 HOLD WR/QS1 63 32 PE5 PA2 25
R69 62 186_A17 31 24 WSI_T3
4.7K RD/QSMD CS_B4 PE6 PA3 CS_B0
38 MCS0 30 PE7 PA4 23
R94 37 MCS1 TO0 22 PA5 22
4.7K 36 MCS2 TO1 23 41 RD PA6 21
35 MCS3 UCS 34 29 WR PA7 20
LCS 33 40 RESET
PCS0 25 52 39 50 WSI_T[0..3]
PCS1 27 PCS0 S0 53 42 CSI PB0 49 WSI_T[0..3]

Card Affixer Module Maintenance Manual

PCS2 PCS1 S1 CLKIN PB1 PCS0
28 PCS2 S2 54 PB2 48
PCS3 29 L6 1 47 PCS2
PCS4 PCS3 GND PB3 PCS3
30 PCS4 CLKO 56 35 GND PB4 46
PCS5 31 57 19 45
PCS6 32 PCS5/A1 RESET 51 51 GND PB5 44 CS_B3
PCS6/A2 HLDA GND PB6 CS_B1
DT/R 40 PB7 43
DEN 39 28 VSTDBY
LCK 48 XIL_CCLK
PSD503-12 CLOCK_8M
U39 XIL_DIN
80C186 806346-001

PCS[0..6]
PCS[0..6]
186_WR
186_RD
LC8
1000pF U38 L7
+5V 1 3 CB44 14 8
U21 1 .01UF 186_MEMORY
186_AD0 186_D0 234567890 2
2 A1 B1 18 7 1 186_RD
186_AD1 3 17 186_D1
186_AD2 4 A2 B2 16 186_D2 16Mhz 186_WR
186_AD3 A3 B3 186_D3 186_A[0..17]
5 A4 B4 15
186_AD4 6 A5 14 186_D4
COM_INT[0..2] 186_AD5 B5 186_D5 186_LCS
7 A6 B6 13
186_AD6 8 A7 12 186_D6
SERIAL_COMM 186_AD7 9 B7 11 186_D7 186_UCS
A8 B8 1 RP3
PCS[0..6] 4.7K 186_D[0..15]
186_RD 19 G
186_WR 1 DIR +5V
RST_186 MFHS_M16.SCH
186_A[0..16] 74LS245
186_D[0..7] U29 U22
186_AD8 2 18 186_D8 1 12
COM_INT[0..2] 186_AD9 A1 B1 186_D9 LD F0 186_D[0..15]
3 A2 B2 17 2 I0 F1 13
MFHS_M15.SCH 186_AD10 4 16 186_D10 PCS0 3 14
186_AD11 A3 B3 186_D11 PCS1 I1 F2
5 A4 B4 15 4 I2 F3 15
186_AD12 6 14 186_D12 PCS2 5 16 MAIN_PROCESSOR_CONTROL_186
186_AD13 A5 B5 186_D13 PCS3 I3 F4
7 A6 B6 13 6 I4 F5 17
186_AD14 8 12 186_D14 PCS4 7 18 DataCard Corp.
186_AD15 A7 B7 186_D15 PCS5 I5 F6
9 A8 B8 11 8 I6 F7 19
PCS6 9 Title
19 11 I7
G OE SCHEMATIC, PWB, COMMON BOARD
1 DIR
16V8 Size Document Number REV
74LS245 B 598324 A
Date: July 7, 1995 Sheet 2 of 17

Figure 4-12: Standard Speed Affixer CB Interconnect Diagram (Sheet 2 of 17)

4-23
4-24
186_D[0..15]

186_A[0..15]

U32 U33
186_A1 12 13 186_D8 186_A1 12 13 186_D0
186_A2 A0 D0 186_D9 186_A2 A0 D0 186_D1
11 A1 D1 14 11 A1 D1 14
186_A3 10 15 186_D10 186_A3 10 15 186_D2
186_A4 A2 D2 186_D11 186_A4 A2 D2 186_D3
9 A3 D3 17 9 A3 D3 17
186_A5 8 18 186_D12 186_A5 8 18 186_D4
186_A6 A4 D4 186_D13 186_A6 A4 D4 186_D5
7 A5 D5 19 7 A5 D5 19
186_A7 6 20 186_D14 186_A7 6 20 186_D6
186_A8 A6 D6 186_D15 186_A8 A6 D6 186_D7
5 A7 D7 21 5 A7 D7 21
186_A9 27 186_A9 27
186_A10 A8 186_A10 A8
26 A9 26 A9
186_A11 23 186_A11 23
186_A12 A10 186_A12 A10
25 A11 25 A11
186_A13 4 186_A13 4
186_A14 28 A12 186_A14 28 A12
186_A15 A13 186_A15 A13
3 A14 3 A14
186_A16 31 186_A16 31
186_A17 A15 186_A17 A15
2 A16 2 A16
186_UCS 22 CS1 22 CS1
+5V 30 CS2 +5V 30 CS2
186_RD 24 OE 24 OE
186_WR 29 WE 29 WE
186_LCS MB841000-80 MB841000-80

186 MEMORY

DataCard Corporation
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
B 598324 A
Date: July 7, 1995 Sheet 3 of 17

Figure 4-13: Standard Speed Affixer CB Interconnect Diagram (Sheet 3 of 17)

Theory of Operation
 +5V +5V
LC12 LC9 LC15
1000pF 1000pF 1000pF
1 3 3 1 1 3
CB49 CB48 CB50
2 .01UF .01UF 2 2 .01UF
U46
2 T1I T1O 5 JP8
1 T2I T2O 18 1
186_D[0..7] 4 3
186_D[0..7] R1I R1O 2
U51 19 R2I R2O 20 3
23 VDD TXRDY0 22 4
40 24 +5V
64 VDD RTS0 25 5
VDD DTR0
26 7
6
SOUT0 VCC 7
SIN0 41 8 C1+ V+ 14 8
186_A[0..16] 186_D0 14 29 13
186_A[0..16] 186_D1 DB0 DCD0 C1- 9
15 DB1 RI0 30 15 C2+ C2- 10
186_D2 16 31 11 16 CONN 9
186_D3 DB2 DSR0 C2+ C2-
17 DB3 CTS0 28 6 GND V- 12
186_D4 18 9 9 17
186_D5 DB4 RXRDY0 GND V-
19 DB5
186_D6 20 42 MAX233
186_D7 21 DB6 TXRDY1 12
DB7 RTS1
DTR1 11
186_A3 35 10
186_A1 A0 SOUT1
34 A1 SIN1 62
PCS[0..6] 186_A2 33 8
PCS[0..6] A2 DCD1 6
RI1
RST_186 39 RESET DSR1 5 U47
CTS1 13 2 T1I T1O 5 JP7
PCS4 32 61 1 18
PCS5 CS0 RXRDY1 T2I T2O 1
3 CS1 4 R1I R1O 3 2
PCS6 38 53 PAR_B0 19 20
COM_INT0 45 CS2 PD0 52 PAR_B1 +5V R2I R2O 3
COM_INT1 INT0 PD1 PAR_B2 4
60 INT1 PD2 51 5
59 50 PAR_B3
INT2 PD3 PAR_B4 6
PD4 49 7 VCC 7
36 48 PAR_B5 8 14
186_WR 37 IOW PD5 47 PAR_B6 13 C1+ V+ 8
186_RD IOR PD6 PAR_B7 C1- 9
44 BD0 PD7 46 15 C2+ C2- 10
11 C2+ C2- 16 CONN 9

Card Affixer Module Maintenance Manual

43 68 PAR_B8 6 12
ENIRQ ACK PAR_B9 GND V-
2 TRI PEMD 1 9 GND V- 17
67 PAR_B10
4 PE PAR_B11
CLK BUSY 66 MAX233
65 PAR_B12
SLCT PAR_B13
ERR 63
58 PAR_B14
54 SLIN 57 PAR_B15
GND INIT PAR_B16
27 GND AFD 56
7 55 PAR_B17
GND STB
TL16C552

COM_INT[0..2]
COM_INT[0..2]
PAR_B[0..17]
JP9
PAR_B0
+5V PAR_B1 1
PAR_B2 2
LC11 PAR_B3 3
PAR_B4 4
1000pF U49 L9 5
1 3 14 8 PAR_B5
PAR_B6 6
CB51 R107 PAR_B7 7
2 .01UF 7 1 68 PAR_B8 8
PAR_B9 9
PAR_B10 10
18.432M 11
PAR_B11
C89 PAR_B12 12
220pF PAR_B13 13
+5V PAR_B14 14
PAR_B15 15
PAR_B16 16
PAR_B17 17
18
19 SERIAL COMM
20
21
22 DataCard Corp.
23
24 Title
25 SCHEMATIC, PWB, COMMON BOARD
26 Size Document Number REV
CONN 26 B 598324 A
Date: July 7, 1995 Sheet 4 of 17

Figure 4-14: Standard Speed Affixer CB Interconnect Diagram (Sheet 4 of 17)

4-25
4-26
152_CB[0..5]
152_CB[0..5]

5,11 1000pF
152_D[0..7] 1 3
152_D[0..7] +5V
LC14 CB42
RST_301 2 .01UF
3,11 RST_186
+5V 152_A[0..15]
LC13
1000pF
1 3 152_D[0..7]
CB41 4
2 .01UF U52 4
2 27 152_D0 U54
VCC AD0 152_D1 152_D0 V 152_A0 152_A0 152_D0
3 GND AD1 28 23 AD0/A0 C PA0 21 10 A0 O0 11
33 29 152_D2 152_D1 24 C 20 152_A1 152_A1 9 12 152_D1
GND AD2 152_D3 152_D2 AD1/A1 PA1 152_A2 152_A2 A1 O1 152_D2
AD3 30 25 AD2/A2 PA2 19 8 A2 O2 13
34 152_D4 152_D3 26 18 152_A3 152_A3 7 15 152_D3
AD4 152_D5 152_D4 AD3/A3 PA3 152_A4 152_A4 A3 O3 152_D4
CLOCK_16M 32 X1 AD5 35 27 AD4/A4 PA4 17 6 A4 O4 16
31 36 152_D6 152_D5 28 16 152_A5 152_A5 5 17 152_D5
X2 AD6 152_D7 152_D6 AD5/A5 PA5 152_A6 152_A6 A5 O5 152_D6
13 RST AD7 37 29 AD6/A6 PA6 15 4 A6 O6 18
56 152_D7 30 14 152_A7 152_A7 3 19 152_D7
EA 55 AD7/A7 PA7 152_A8 25 A7 O7
ALE 152_A8 152_CB0 152_A9 A8
31 AD8/A8 PB0 11 24 A9
17 41 152_A8 152_A9 32 10 152_CB1 152_A10 21
P5.0 A8 152_A9 152_A10 AD9/A9 PB1 152_CB2 152_A11 A10
SEN_I[0..15] 20 P5.1 A9 42 33 AD10/A10 PB2 9 23 A11
R108 21 43 152_A10 152_A11 35 8 152_CB3 152_A12 2
68 22 P5.2 A10 44 152_A11 152_A12 36 AD11/A11 PB3 7 152_CB4 152_A13 26 A12
SEN_I[0..15] P5.3 A11 152_A12 152_A13 AD12/A12 PB4 152_CB5 152_A14 A13
38 P5.4 A12 45 37 AD13/A13 PB5 6 1 A14
39 46 152_A13 152_A14 38 5
P5.5 A13 152_A14 152_A15 AD14/A14 PB6
40 P5.6 A14 47 39 AD15/A15 PB7 4 20 CE
C90 49 48 152_A15 22
220PF P5.7 A15 OE
22 RD A16/CS8/PC0 40 27 WE
PSEN 54 2 WR/VPP A17/CS9/PC1 41
1 BHE/PSEN 62256
SEN_I12 67 65 13 42
SEN_I13 P6.0 P4.0 ALE A18/CS10/PC2
66 P6.1 P4.1 64 3 RESET A19/CSI 43
SEN_I14 52 63
SEN_I15 57 P6.2 P4.2 62 U41C
P6.3 P4.3
50 P6.4 P4.4 61 U53
68 60 PSD301-12 152_A15 5 6
P6.5 P4.5
1 P6.6 P4.6 59
PG_DONE 51 P6.7 P4.7 58
74LS04

4 GRXD RXD 14
5 GTXD TXD 15
6 DEN INT0 16
7 TXC INT1 18
8 RXC T0 19
9 HLD T1 23
10 HLDA WR 24 U55
11 P1.7 RD 25 2 T1I T1O 5
1 T2I T2O 18
EBEN 12 4 R1I R1O 3 JP6
EPSEN 53 19 R2I R2O 20 1
80C152JD +5V 2
3
4
7 VCC 5
8 C1+ V+ 14 6
13 C1- 7
15 C2+ C2- 10 8
11 C2+ C2- 16 9
6 GND V- 12 10
9 GND V- 17
CONN 10
MAX233

BIF_INTFC
BIF 152 CONTROLLER
152_DEN
152_TXC
152_GTXD DataCard Corp.

152_GRXD Title
152_HLDA SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
MFHS_M17.sch B 598324 A
Date: July 7, 1995 Sheet 5 of 17

Figure 4-15: Standard Speed Affixer CB Interconnect Diagram (Sheet 5 of 17)

Theory of Operation
 +5V
R112
U57

152_TXC 1 8 120
2 7 AENIN-
3 6 AENIN+
4 5 PWR_CTL1
PWR_CTL2
DS3695 JP3
+5V
16
15
+5V 14
R111 13
10K 12
U56 11
1 8 10
152_GRXD -DATA/CLK- 9
U41B 2 7 8 IN
+DATA/CLK+ 7
152_DEN 3 4 3 6 6
4 5 5
4
74LS04 3
152_GTXD DS3695 2
1
CONN 16
K3
2
R125
3
120 4
9 +5V
R126
8
+5V R122
120 7 10K
10 +5V
+5V D18 D19 R124 R113

Card Affixer Module Maintenance Manual

1N4002 1N4002
1 U59
750 120
1 8
RELAY DPDT 2 7 AENOUT- JP4
AENOUT+ 16
3 6 15
152_HLDA 4 5 R123 14
13
12
DS3695 750 11
10
9 OUT
+5V 8
7
U60 6
5
1 8 4
3
2 7 2
1
3 6
4 5 CONN 16

DS3695

BIF INTFC

DataCard Corporation
Title
INT_LCK1 SCHEMATIC, PWB, COMMON BOARD
INT_LCK2 Size Document Number REV
B 598324 A
Date: June 14, 1995 Sheet 6 of 17

Figure 4-16: Standard Speed Affixer CB Interconnect Diagram (Sheet 6 of 17)

4-27
4-28
SEN_I[0..15]
SEN_I[0..15]
186_D[0..15]
1 186_D[0..15]
CB35 RP1
.01UF 4.7K
R10 R14 R18 R22 R24 R20 R16 R11 +5V
200 200 200 200 150 150 150 150
U7 186_WR
1 19 3
098765432 VREF VCC
VDD 22
5 AIN0
4 18 186_D0
21 AIN1 D0 17 186_D1
AIN2 D1 186_D2
20 AIN3 D2 16
15 186_D3
SEN_I0 D3 186_D4
2 C0 D4 14
SEN_I1 1 13 186_D5
SEN_I2 24 C1 D5 12 186_D6
SEN_I3 C2 D6 186_D7
23 C3 D7 11
7 DCDE_B0
CS
WR 8
10 186_A2
A0 186_A1
A1 9
+5V 6
GND
MAX516
U6
19 VREF VCC 3
VDD 22
5 AIN0
4 18 186_D0
21 AIN1 D0 17 186_D1
AIN2 D1 186_D2
20 AIN3 D2 16
15 186_D3
SEN_I4 D3 186_D4
2 C0 D4 14
SEN_I5 1 13 186_D5
+5V SEN_I6 24 C1 D5 12 186_D6
2468111112222233333433333222221111197531 SEN_I7 C2 D6 186_D7
0246802468024680975319753197531 L1 23 C3 D7 11
JP16 7 DCDE_B1
CONN 40SENSOR CS
1 WR 8
10 186_A2
186_A[0..17] A0 186_A1
186_A[0..17] RP2 C3 A1 9
4.7K .001UF
DCDE_B[0..3] +5V 6
DCDE_B[0..3] GND
MAX516
U5
1 19 3
098765432 VREF VCC
VDD 22
5 AIN0
4 18 186_D0
21 AIN1 D0 17 186_D1
AIN2 D1 186_D2
R9 R13 R17 R21 R23 R19 R15 R12 20 AIN3 D2 16
150 150 150 200 150 150 150 150 15 186_D3
SEN_I8 D3 186_D4
2 C0 D4 14
SEN_I9 1 13 186_D5
SEN_I10 24 C1 D5 12 186_D6
SEN_I11 C2 D6 186_D7
23 C3 D7 11
7 DCDE_B2
CS
WR 8
10 186_A2
A0 186_A1
A1 9
+5V 6
GND
MAX516
U4
19 VREF VCC 3
VDD 22
5 AIN0
4 18 186_D0
21 AIN1 D0 17 186_D1
AIN2 D1 186_D2
20 AIN3 D2 16
15 186_D3
SEN_I12 D3 186_D4
2 C0 D4 14
SEN_I13 1 13 186_D5
SEN_I14 24 C1 D5 12 186_D6 SENOR INTERFACE UNIT
SEN_I15 C2 D6 186_D7
23 C3 D7 11
L5 DataCard Corp.
7 DCDE_B3
CS
WR 8 Title
2468111112222233333433333222221111197531 10 186_A2
0246802468024680975319753197531 A0 SCHEMATIC, PWB, COMMON BOARD
9 186_A1
A1 Size Document Number REV
JP15
CONN 40SENSOR GND 6 B 598324 A
MAX516 Date: July 7, 1995 Sheet 7 of 17

Figure 4-17: Standard Speed Affixer CB Interconnect Diagram (Sheet 7 of 17)

Theory of Operation
 PG_DONE
INTERLOCK CUR_S[0..11]
+5V STEPPER_1_AND_2
R41 4.7K STP1_C[0..5] CUR_S4
STP1_C[0..5] S1_SENS1 CUR_S5
WSI_T[0..3] CUR_REF[0..11] S1_SENS2
WSI_T[0..3] STP2_C[0..5] CUR_S6
186_A[0..17] STP2_C[0..5] S2_SENS1 CUR_S7
186_A[0..17] S2_SENS2

MFHS_M3.SCH
U13
22 VCC RDATA/M1 31
64 VCC
IO* 38
12 39 186_A4
CLOCK_8M +5V PWRDWN IO 186_A2
32 RTRIG/M0 IO 40
54 41 SEN_B3
RST_186 55 RESET IO* 42 STP2_C4
PG/DONE IO/INIT STP2_C3
XIL_CCLK 74 CCLK IO 44
45 CUR_S10
+5V LC5 STP3_C1 IO STP2_C2
2 IO IO 46
1000pF STP3_C0 3
1 3 CUR_S9 4 IO 47 STP4_C0
152_CB2 IO IO STP4_C1 STEPPER_3
5 IO IO 48
CB57 CUR_S9 6 49 WSI_T3 STP3_C[0..5] CUR_S8
2 .01UF WSI_T0 IO* IO STP3_C[0..5] S3_SENS1 CUR_S9
7 IO* IO* 50 CUR_REF[0..11] S3_SENS2
STP3_C4 8 51 STP4_C4
152_D3 9 IO IO* 52 CUR_S11
IO IO STP4_C5
IO/XTL2 53
LC2 STP3_C5 10 IO IO/D7 56 STP4_C3
1000pF 11 IO
1 3 186_D3 13 IO IO/XTL1 57 STP4_C2 MFHS_M4.SCH
186_D2 14 IO* IO/D6 58 152_D4
CB56 152_D2 15 IO IO 59 152_D5
2 .01UF WSI_T2 16 60 186_D4 STEPPER_4
152_D1 IO IO/D5 186_D5 STP4_C[0..5] CUR_S10
17 IO IO/CS0 61 STP4_C[0..5] S4_SENS1
186_D6 18 IO 62 152_CB0 CUR_S11
+5V IO/D4 CUR_REF[0..11] S4_SENS2
IO 63
186_D1 19 IO 65 152_CB1
186_A6 IO/D3
R42 20 IO
STP2_C0 152_D0 21 IO 66 186_D0
IO/CS1

Card Affixer Module Maintenance Manual

186_D7 23 IO 67 152_CB4
4.7K 152_D7 24 IO/D2 152_CB5
IO IO 68 MFHS_M9.SCH
152_D6 25 IO 69 152_CB3
186_A1 26 IO*
IO IO/D1 70
27 71 STP1_C0
186_RD IO IO/RDY/BUSY CUR_REF[0..11]
IO/DIN/D0 72
28 73 STP1_C1
186_WR STP2_C5 29 IO IO
CUR_S6 IO STP1_C5
30 IO IO/WS 75
STP2_C0 33 76 SEN_B0 CUR_REF[0..7]
STP2_C1 IO/M2 IO/CS2 STP1_C4
34 IO/HDC IO 77
CS_B4 35 78 STP1_C3
WSI_T1 IO IO STP1_C2 CURRENT_SENSOR_INTERFACE
36 IO/LDC IO* 79
186_A3 37 80 SEN_B1
IO IO* 186_D[0..7] CUR_REF[0..11]
IO 81
1 82 STP3_C3
GND IO 186_A[0..17]
43 GND
83 186_A5
IO 84 STP3_C2 CS_B[0..4]
IO 186_WR
XC3042-70 186_RD

MFHS_M8.SCH

186_D[0..15]
186_D[0..15]

XIL_DIN XIL_DOUT

152_CB[0..5]
152_CB[0..5]
152_D[0..7] XLINIX 1
152_D[0..7]
DataCard Corp.
CS_B[0..4]
CS_B[0..4]
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
B 598324 A
Date: June 14, 1995 Sheet 8 of 17

Figure 4-18: Standard Speed Affixer CB Interconnect Diagram (Sheet 8 of 17)

4-29
4-30
CUR_REF[0..7]
CUR_REF[0..7]
R59 +24V1 +5V
STP1_C4 +24V1 100K
R49 8 U28A R56
4.7K C39 R54 10K
C42 1.0 CUR_REF0 3
.22 U18 R58 1 S1_SENS1
2 VS 100 2
9 VREF OUT1 3
STP1_C4 11 ENABLE R48 100 D5 LM393
STP1_C0 5 IN1 1 .499 C51 1N5818 4 +24V1
OUT2
.01
STP1_C1 7 IN2 SENSE 10 2
4 BOOT1 CR3
8 BOOT2 MBR1545
6 GND
C40 C41 1 3 JP13
.01 .01 L6203 1
STP1_C5 2
3
+24V1 +5V 4
R50 R60
4.7K +24V1 100K CONN 4

8 U28B R57
C43 R55 10K
1.0 CUR_REF1 5
C46 U25 R61 7 S1_SENS2
.22 2 VS 100 6
9 VREF 3 +24V1
STP1_C5 OUT1
11 ENABLE R51 100 D6 LM393
STP1_C2 5 IN1 1 .499 C52 1N5818 4 2
OUT2
.01 CR6
STP1_C3 7 IN2 10 MBR1545
SENSE
4 BOOT1
8 BOOT2 1 3
6 GND
C44 C45
.01 .01 L6203

STP1_C[0..5]
STP1_C[0..5] R67 +24V1 +5V
5 +24V1 100K
STP2_C4
8 U30A R63
R53 C47 R65 10K
4.7K 1.0 CUR_REF2 3
C50 U26 R66 1 S2_SENS1
.22 2 VS 100 2
9 VREF OUT1 3
STP2_C4 11 ENABLE R52 100 D11 LM393
STP2_C0 5 IN1 1 .499 C77 1N5818 4 +24V1
OUT2 .01
STP2_C1 7 IN2 SENSE 10 2
4 BOOT1 CR7
8 BOOT2 MBR1545
6 GND
C48 C49 1 3 JP14
.01 .01 L6203 1
STP2_C5 2
3
R92 R68 +24V1 +5V 4
4.7K +24V1 100K CONN 4

8 U30B R64
C73 R62 10K
C76 1.0 CUR_REF3 5
.22 U27 R93 7 S2_SENS2
2 VS 100 6
9 VREF 3 +24V1
STP2_C5 OUT1
11 ENABLE R91 100 D12 LM393
STP2_C2 5 IN1 1 .499 C78 1N5818 4 2
OUT2 .01 CR8
STP2_C3 7 IN2 10 MBR1545
SENSE
4 BOOT1
8 BOOT2 1 3
6 GND
C74 C75
.01 .01 L6203 STEPPER 1 AND 2

DataCard Corp.
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
STP2_C[0..5]
STP2_C[0..5] B 598324 A
Date: June 14, 1995 Sheet 9 of 17

Figure 4-19: Standard Speed Affixer CB Interconnect Diagram (Sheet 9 of 17)

Theory of Operation
 +24V1
STP3_C4
R33 C6
4.7K 1.0
C9
.22 U8
2 VS
9 VREF OUT1 3
STP3_C4 11
STP3_C0 ENABLE
5 IN1 OUT2 1
STP3_C1 7 10
IN2 SENSE
4 BOOT1
8 BOOT2
6 GND
C7 C8
.01 .01 L6203

+24V1 R3 +24V1 +5V

100K
C16 C14 8 U1A R2
.22 1.0 R7 10K
CUR_REF4 3
U10 R1 1 S3_SENS1
2 VS 100 2
9 VREF OUT1 3
STP3_C4 11 R34 100 D1 LM393
STP3_C0 ENABLE
5 IN1 OUT2 1 .499 C1 1N5818 4
.01 +24V1
STP3_C1 7 10
IN2 SENSE 2
4 BOOT1
8 BOOT2 CR1
6 GND MBR1545
C15 C17
.01 .01 L6203 1 3

Card Affixer Module Maintenance Manual

+24V1

C13 +24V1 JP10

.22 C10 1
1.0 2 2
CR4 3
U9 MBR1545 4
2 VS
9 3 1 3 CONN 4
STP3_C5 VREF OUT1
11 ENABLE
STP3_C2 5 1
IN1 OUT2
STP3_C3 7 10
4 IN2 SENSE
BOOT1
8 BOOT2
6 GND
C11 C12
.01 .01 L6203
STP3_C5
R36 +24V1 R4 +24V1 +5V
4.7K 100K
C18 C20 8 U1B R5
.22 1.0 R8 10K
CUR_REF5 5
U11 R6 7 S3_SENS2
2 VS 100 6
9 VREF OUT1 3
STP3_C5 11 R35 100 D2 LM393
STP3_C2 ENABLE
5 IN1 OUT2 1 .499 C2 1N5818 4
.01
STP3_C3 7 10
4 IN2 SENSE
BOOT1
8 BOOT2
6 GND
C21 C19
.01 .01 L6203
STEPPER 3

DataCard Corp.
Title
STP3_C[0..5] SCHEMATIC, PWB, COMMON BOARD
STP3_C[0..5] Size Document Number REV
CUR_REF[0..7]
CUR_REF[0..7] B 598324 A
Date: June 14, 1995 Sheet 10 of 17

Figure 4-20: Standard Speed Affixer CB Interconnect Diagram (Sheet 10 of 17)

4-31
4-32
STP4_C4 +24V2
R46
4.7K C38
1.0
C35
.22 U17
2 VS
9 VREF OUT1 3
STP4_C4 11
STP4_C0 ENABLE
5 IN1 OUT2 1
STP4_C1 7 10
IN2 SENSE
4 BOOT1
8 BOOT2
6 GND
C37 C36
.01 .01 L6203

+24V2 R29 +24V2 +5V

100K
C30 C28 8 U2A R28
.22 1.0 R26 10K
CUR_REF6 3
U15 R27 1 S4_SENS1
2 VS 100 2
9 VREF OUT1 3
STP4_C4 11 R45 100 D3 LM393
STP4_C0 ENABLE
5 IN1 OUT2 1 .499 C4 1N5818 4
.01 +24V2
STP4_C1 7 10
IN2 SENSE 2
4 BOOT1
8 BOOT2 CR5
6 GND MBR1545
C27 C29
.01 .01 L6203 1 3

+24V2

C31 +24V2 JP11

.22 C34 1
1.0 2 2
CR2 3
U16 MBR1545 4
2 VS
9 3 1 3 CONN 4
STP4_C5 VREF OUT1
11 ENABLE
STP4_C2 5 1
IN1 OUT2
STP4_C3 7 10
4 IN2 SENSE
BOOT1
8 BOOT2
6 GND
C33 C32
.01 .01 L6203

STP4_C5
+24V2 R30 +24V2 +5V
R43 100K
4.7K
C24 8 U2B R31
1.0 R25 10K
CUR_REF7 5
C26 U14 R32 7 S4_SENS2
.22 2 VS 100 6
9 VREF OUT1 3
STP4_C5 11 R44 100 D4 LM393
STP4_C2 ENABLE
5 IN1 OUT2 1 .499 C5 1N5818 4
.01
STP4_C3 7 10
4 IN2 SENSE
BOOT1
8 BOOT2
6 GND
C25 C23
.01 .01 L6203
STEPPER 4

DataCard Corp.
STP4_C[0..5]
Title
SCHEMATIC, PWB, COMMON BOARD
STP4_C[0..5] Size Document Number REV
CUR_REF[0..7]
CUR_REF[0..7] B 598324 A
Date: June 14, 1995 Sheet 11 of 17

Figure 4-21: Standard Speed Affixer CB Interconnect Diagram (Sheet 11 of 17)

Theory of Operation
 CUR_REF[0..11]
CUR_REF[0..11]
186_D[0..7]
186_D[0..7]

+5V +5V +5V

U19 U3 U40
186_D0 14 18 186_D0 14 18 186_D0 14 18
186_D1 D0(LSB) VDD 186_D1 D0(LSB) VDD 186_D1 D0(LSB) VDD
13 D1 13 D1 13 D1
186_D2 12 186_D2 12 186_D2 12
186_D3 11 D2 2 CUR_REF0 186_D3 11 D2 2 CUR_REF4 186_D3 11 D2 2 CUR_REF8
186_D4 D3 VOUTA 186_D4 D3 VOUTA 186_D4 D3 VOUTA
10 D4 10 D4 10 D4
186_D5 9 1 CUR_REF1 186_D5 9 1 CUR_REF5 186_D5 9 1 CUR_REF9
186_D6 D5 VOUTB 186_D6 D5 VOUTB 186_D6 D5 VOUTB
8 D6 8 D6 8 D6
186_D7 7 20 CUR_REF2 186_D7 7 20 CUR_REF6 186_D7 7 20 CUR_REF10
D7(MSB) VOUTC D7(MSB) VOUTC D7(MSB) VOUTC
CS_B0 15 19 CUR_REF3 CS_B1 15 19 CUR_REF7 CS_B2 15 19 CUR_REF11
186_A1 WR VOUTD 186_A1 WR VOUTD 186_A2 WR VOUTD
16 A1 16 A1 16 A1
186_A2 17 VREF 186_A2 17 VREF 186_A1 17 VREF
A0 A0 A0
VREF 4 VREF 4 VREF 4
6 DGND 6 DGND 6 DGND
AGND 5 AGND 5 AGND 5
VSS 3 VSS 3 VSS 3
MAX506 MAX506 MAX506
CS_B[0..4]
CS_B[0..4]

186_A[0..17]
186_A[0..17]

+5V
+5V
R129

Card Affixer Module Maintenance Manual

220 +5V
C924 R106
.001UF +5V +5V 1K
JP12 L13 8 U50A
+5V
1 U31 VREF
2 3
1 1 VIN VDD 20
CONN 2 L12 2 8 U50B
12 2 186_D0
+VREF D0 186_D1
R128 C88 MC34072 11 -VREF D1 3 5
4.22K 0.1 4 4 186_D2 7
D2 186_D3
D3 5 6
14 186_D4 U48
R105 6 D4 15 186_D5 2 MC34072
WR/RDY D5 186_D6
7 MODE D6 16 4
8 17 186_D7
1K RD D7 C87
CS_B3 13 9 0.1 1
18 CS INT
PWRDN
LM336
186_WR 19 VSS 3
186_RD 10 GND
MAX153

CURRENT_SENSOR_INTERFACE

DataCard Corp.
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
B 598324 A
Date: July 7, 1995 Sheet 12 of 17

Figure 4-22: Standard Speed Affixer CB Interconnect Diagram (Sheet 12 of 15)

4-33
4-34
186_D[0..15]
186_D[0..15]
CUR_S[0..11]
SEN_I[0..15]
SEN_I[0..15] STEPPER_5_AND_6
STP5_C[0..5] CUR_S0
VCC +5V STP5_C[0..5] S5_SENS1 CUR_S1
LC1 LC3 CUR_REF[0..11] S5_SENS2
1000pF 1000pF
3 1 1 3 +5V STP6_C[0..5] CUR_S2
R40 STP6_C[0..5] S6_SENS1 CUR_S3
CB53 +5V 4.7k S6_SENS2
2 2 .01UF
U12 MFHS_M5.SCH
CB52 R38 22 VCC RDATA/M1 31
.01UF 4.7K 64 VCC STEPPER_7
38 186_D1 STP7_C[0..2]
12 IO* 39 STP5_C1 STP7_C[0..2]
PWRDWN IO SEN_I6
32 RTRIG/M0 IO 40
54 41 STP5_C0
RST_186 RESET IO* DIS_B1
PG_DONE 55 PG/DONE IO/INIT 42
74 44 DIS_B0
XIL_CCLK CCLK IO 45 186_D6
IO 186_D7
2 IO IO 46 MFHS_M11.SCH
SEN_I8 3 SWITCH_AND_LED_CONTROL
SEN_I9 IO SEN_I7 DIS_B[0..7]
4 IO IO 47 DIS_B[0..7] SW_1
STP5_C5 5 48 DIS_B3
STP5_C4 6 IO IO 49 DIS_B2 SW_2
186_A[0..17] 186_D3 IO* IO DIS_B6
186_A[0..17] 7 IO* IO* 50
8 51 DIS_B7
SEN_I2 IO IO* STP5_C2
9 IO IO 52
IO/XTL2 53
SEN_I3 10 IO IO/D7 56 MFHS_M10.SCH
CLOCK_8M 11 IO
186_A4 13 IO IO/XTL1 57 STP5_C3
14 58 STP6_C5
186_RD 15
IO* IO/D6
59 STP6_C4
186_WR 186_A3 16
IO IO
60 SEN_I4
CS_B4 17 IO IO/D5 61
CS_B2 IO IO/CS0 STP6_C3
18 IO IO/D4 62
R37 63 SEN_I5
68 186_D2 19 IO
IO IO/D3 65 SEN_INT
SEN_I0 20 IO
DCDE_B2 21 IO 66 STP6_C2
SEN_I1 23 IO/CS1 CUR_S2
IO IO/D2 67
C22 186_A1 24 IO 68 CUR_S3
220pF +5V 186_A6 25 IO STP6_C1
IO IO* 69
26 IO 70 STP6_C0
DCDE_B0 27 IO/D1 71 STP7_C0
IO IO/RDY/BUSY
R39 IO/DIN/D0 72
4.7K 186_A2 28 73 STP7_C1
IO IO
29 IO 186_TMR0
DCDE_B1 30 75 STP7_C2
IO IO/WS DIS_B4 186_TMR1
33 IO/M2 IO/CS2 76
DCDE_B3 34 77 DIS_B5
+5V CUR_S0 IO/HDC IO 186_D5
35 IO IO 78
CUR_S1 36 79 186_D4
186_D0 IO/LDC IO*
37 IO IO* 80
IO 81
1 82 SEN_I11
GND IO
43 GND
JP5 83 SEN_I10
L2 IO 186_A5
1 IO 84
2 XC3042-70
3
4 CB55
5 .01UF
6 L3
CONN 6
L4
XIL_DOUT
CB54 DCDE_B[0..3]
DCDE_B[0..3]
.01UF

CS_B[0..4]
CS_B[0..4]
CUR_REF[0..11] XLINIX 2
CUR_REF[0..11]
DataCard Corp.
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
B 598324 A
Date: July 7, 1995 Sheet 13 of 17

Figure 4-23: Standard Speed Affixer CB Interconnect Diagram (Sheet 13 of 17)

Theory of Operation
 CUR_REF[0..11]
CUR_REF[0..11] +24V2
R76 +5V
+24V2 100K
STP5_C4
8 U34A R73
R88 C68 R83 10K
4.7K C65 1.0 CUR_REF8 3
.22 U24 R74 1 S5_SENS1
2 VS 100 2
9 VREF OUT1 3
STP5_C4 11 ENABLE R47 100 D7 LM393
STP5_C0 5 IN1 1 .499 C57 1N5818 4 +24V2
OUT2
.01
STP5_C1 7 IN2 10 2
SENSE CR10
4 BOOT1
8 BOOT2 MBR1545
6 GND
C67 C66 1 3 JP18
.01 .01 L6203 1
STP5_C5 2
3
+24V2 +5V 4
R90 R75
4.7K +24V2 100K CONN 4
C69 8 U34B R70
.22 C72 R84 10K
1.0 CUR_REF9 5
U37 R77 7 S5_SENS2
2 VS 100 6
9 VREF 3 +24V2
STP5_C5 OUT1
11 ENABLE R89 100 D8 LM393
STP5_C2 5 IN1 1 .499 C58 1N5818 4 2
OUT2
.01 CR11
STP5_C3 7 IN2 SENSE 10 MBR1545
4 BOOT1
8 BOOT2 1 3
6 GND
C71 C70
.01 .01 L6203

Card Affixer Module Maintenance Manual

STP5_C[0..5]
STP5_C[0..5] R81 +24V2 +5V
+24V2 100K
STP6_C4
8 U35A R80
R71 C53 R85 10K
4.7K 1.0 CUR_REF10 3
C56 U23 R78 1 S6_SENS1
.22 2 VS 100 2
9 VREF OUT1 3
STP6_C4 11 ENABLE R72 100 D9 LM393
STP6_C0 5 IN1 1 .499 C59 1N5818 4 +24V2
OUT2 .01
STP6_C1 7 IN2 SENSE 10 2
4 BOOT1 CR9
8 BOOT2 MBR1545
6 GND
C54 C55 1 3 JP19
.01 .01 L6203 1
STP6_C5 2
3
R96 R82 +24V2 +5V 4
4.7K +24V2 100K CONN 4
C64 8 U35B R79
.22 C61 R95 10K
1.0 CUR_REF11 5
U43 R86 7 S6_SENS2
2 VS 100 6
9 VREF 3 +24V2
STP6_C5 OUT1
11 ENABLE R87 100 D10 LM393
STP6_C2 5 IN1 1 .499 C60 1N5818 4 2
OUT2 .01 CR12
STP6_C3 7 IN2 10 MBR1545
SENSE
4 BOOT1
8 BOOT2 1 3
6 GND
C62 C63 STEPPER 5 AND 6
.01 .01 L6203

DataCard Corp.
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
STP6_C[0..5]
STP6_C[0..5] B 598324 A
Date: June 14, 1995 Sheet 14 of 17

Figure 4-24: Standard Speed Affixer CB Interconnect Diagram (Sheet 14 of 17)

4-35
4-36
+24V2

C79
C82 1.0
.22 U44
2 VS
9 VREF OUT1 3
STP7_C2 11
STP7_C0 ENABLE +24V2
5 IN1 OUT2 1
STP7_C1 7 IN2 10 2
SENSE CR13
4 BOOT1
8 BOOT2 MBR1545
6 GND
C80 C81 1 3 JP17
.01 .01 L6203 1
2
CONN 2

STP7_C2 R101
.499
R100
4.7K

STP5_C[0..2]
STP7_C[0..2]

STEPPER 7

DataCard Corp.
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV
B 598324 A
Date: June 14, 1995 Sheet 15 of 17

Figure 4-25: Standard Speed Affixer CB Interconnect Diagram (Sheet 15 of 17)

Theory of Operation
 +5V +5V

R136 R137
4.7K 4.7K

S1
SW_1
SW PUSHBUTTON

S2
SW_2
SW PUSHBUTTON
C99 C100
.01 .01

DIS_B[0..7]
DIS_B[0..7]
R121

Card Affixer Module Maintenance Manual

DIS_B0
1K
R120
DIS_B1
1K
R119
DIS_B2
U58
1K 10 A
R118 9 B
DIS_B3 8 C
5 D
1K 4 E
R117 2 F
DIS_B4 3 G
1K 7 DP
R116
DIS_B5 1 CA
6 CA
1K
R115 +5V
DIS_B6 F111
1K
R114
DIS_B7
1K

SWITCH AND LED CONTROL

DataCard Corp.
Title
SCHEMATIC, PWB, COMMON BOARD
Size Document Number REV

Figure 4-26: Standard Speed Affixer CB Interconnect Diagram (Sheet 16 of 17)

B 598324 A
Date: June 14, 1995 Sheet 16 of 17

4-37
4-38
INTERLOCK

+24V +24V
RST_301

+24V2 +24V1 R110 R99 +5V RST_186

2K 3K +24V
INT_LCK1
D15 R98 INT_LCK2
8 U42A 10K
1N914 3 U41A
D14 1 +24V
2 1 2 CB36
.01UF JP2
1N914 LM393 L15 1
4 74LS04 L11 2
R109 R97 L17 3
3K 2K L14 4
L10 5
L16 6
D16 CONN 6

PWR_CTL2 R131
1N4002 .01UF .01UF .499 .01UF .01UF
PWR_CTL1 K2 K1
+24V 8 +24V 8 CB38 CB37 CB39 CB40
+5V 1 +24V2 1 +24V1
U36 4 4
1 IN VCC 8 6 6
3 T RST 5 2 2
2 M RST 6
4 GND NMI 7 RELAY SPDT1 RELAY SPDT1
TP3 TP8 TP1 TP9 TP5
DS1231-20 R133 R130 TP TP TP TP TP
10 R135 10 R127
1/2W 4.7K 1/2W 4.7K
+24V

TP10
TP D22 D20
JP1 LED LED TP7
4 24V1 TP
TP6 +5v
3 +24V
2 TP
R132 +5V
1 4.7K U45
CONN 4 LT1074 L8
5 VIN VSW 4 CB1 CB2 CB3 CB4 CB5 CB6
C97 .01UF .01UF .01UF .01UF .01UF .01UF
.001UF 2 VCOMP G FB 1 50UH C86 R134
N D13 1K
D17 D USD945 R103 C85
LED R104 3.32K 470UF
24V 4.7K 3
.001UF
D21 +5v
LED
+5V
R102
C83 2.55K
.033 CB7 CB8 CB9 CB10 CB11 CB12
.01UF .01UF .01UF .01UF .01UF .01UF

+5V

CB13 CB14 CB15 CB16 CB17 CB18 CB19 CB20 CB21 CB22 CB23 CB24 CB25 CB26 CB27
.01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF .01UF

TP4 TP2
TP TP
+24V2 +24V1
+24V +24V +5V +5V +5V +5V +24V2 +24V1 +24V
POWER CONTROL
C96 C95 C84 C91 C92 C94 C98 C93 CB28 CB29 CB30 CB31 CB32 CB33 CB34 DataCard Corp.
1000UF 1000UF 10UF 10UF 10UF 10UF 100 100 .01UF .01UF .01UF .01UF .01UF .01UF .01UF
ELE ELE TAN TAN TAN TAN ELE ELE Title
SCHEMATIC, MFHS COMMON BOARD
Size Document Number REV
B 598324 A
Date: July 7, 1995 Sheet 17 of 17

Figure 4-27: Standard Speed Affixer CB Interconnect Diagram (Sheet 17 of 17)

Theory of Operation
 186_C[0..4]

MAIN_PROCESSOR_CONTROL_186 XILINX_1
PG_DONE WSI_T[0..3] WSI_T[0..3] WSI_T[0..3]
XIL_CCLK XIL_CCLK
XIL_DIN XIL_DIN PG_DONE
186_D[0..15] RST_186
RST_186 186_D[0..15] 186_D[0..15]
PULUP_0 186_A[0..17] PULUP_0
186_A[0..17] 186_A[0..17]
186_TO0 186_TO0 186_C[0..4]
186_C[0..4] 186_TO1 186_TO1
186_RD 186_RD
186_WR 186_WR
XIL_CS XIL_CS SON_DRIVE
CLOCK_8M CLOCK_8M
INTERLOCK
SEN_I[0..3] CS_SEN
PULUP_1 CS_B[0..4] PULUP_1

Card Affixer Module Maintenance Manual

CS_B[0..4] CS_B[0..4]
BUF_M1.SCH BUF_M2.SCH

SEN_I[0..3]

SENSOR_INTERFACE_UNIT
SON_DRIVE
186_WR
186_A[0..17]
POWER_CONTROL 186_D[0..15]
RST_186
INTERLOCK SEN_I[0..3]
CS_SEN
BUF_M3.SCH

BUF_M4.SCH

Figure 4-28: Form Buffer CB Interconnect Diagram (Sheet 1 of 9)

DataCard Corp.
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
B 598475 A
Date: March 22, 1996 Sheet 1 of 9

4-39
4-40
PG_DONE
+5V 186_TO0
LC5 186_TO1
2 1000pF CS_B[0..3] CS_B[0..3]
C36 186_A[0..17] 186_A[0..17]
1 3 .1UF

C35 4 +5V
1 3 .1UF 3 9 U12
59 X1 AD0 17 186_AD0 186_AD0 9 AD0/A0 VCC 18
LC4 V V 15 186_AD1 186_AD1 8 52
C C AD1 AD1/A1 VCC
2 1000pF C C AD2 13 186_AD2 186_AD2 7 AD2/A2
58 X2 AD3 11 186_AD3 186_AD3 6 AD3/A3 PC0 17 186_A0
AD4 8 186_AD4 186_AD4 5 AD4/A4 PC1 16 186_A1
186_C0 20 TI0 AD5 6 186_AD5 186_AD5 4 AD5/A5 PC2 15 186_A2
186_C1 21 TI1 AD6 4 186_AD6 186_AD6 3 AD6/A6 PC3 14 186_A3
AD7 2 186_AD7 186_AD7 2 AD7/A7 PC4 13 186_A4
RST_186 24 RES AD8 16 186_AD8 PC5 12 186_A5
47 TEST AD9 14 186_AD9 186_AD8 68 AD8/A8 PC6 11 186_A6
AD10 12 186_AD10 186_AD9 67 AD9/A9 PC7 10 186_A7
186_C2 18 DRQ0 AD11 10 186_AD11 186_AD10 66 AD10/A10
186_C3 19 DRQ1 AD12 7 186_AD12 186_AD11 65 AD11/A11 PD0 60 186_A8
AD13 5 186_AD13 186_AD12 64 AD12/A12 PD1 59 186_A9
186_C[0..4] 186_C4 45 INT0 AD14 3 186_AD14 186_AD13 63 AD13/A13 PD2 58 186_A10
44 INT1 AD15 1 186_AD15 186_AD14 62 AD14/A14 PD3 57 186_A11
A16/S3 68 186_AD15 61 AD15/A15 PD4 56 186_A12
COM_INT0 42 INT2/TA0 A17/S4 67 PD5 55 186_A13 R37
COM_INT1 41 INT3/TA1 A18/S5 66 38 PE0 PD6 54 186_A14 680
A19/S6 65 37 PE1/ALE PD7 53 186_A15
55 ARDY 36 PE2
49 SRDY BHE/S7 64 186_A16 34 PE3 PA0 27 WSI_T0
46 NMI ALE/QS0 61 33 PE4 PA1 26 WSI_T1 C40
50 HOLD WR/QS1 63 32 PE5 PA2 25 WSI_T2 220pF
RD/QSMD 62 186_A17 31 PE6 PA3 24 WSI_T3
38 MCS0 CS_B2 30 PE7 PA4 23 CS_B0
R34 37 MCS1 TO0 22 PA5 22
4.7K 36 MCS2 TO1 23 41 RD PA6 21
35 MCS3 UCS 34 29 WR PA7 20
LCS 33 40 RESET
PCS0 25 PCS0 S0 52 39 CSI PB0 50 WSI_T[0..3] WSI_T[0..3]
PCS1 27 PCS1 S1 53 42 CLKIN PB1 49
PCS2 28 PCS2 S2 54 PB2 48 PCS0
PCS3 29 PCS3 L4 1 GND PB3 47 PCS2
PCS4 30 PCS4 CLKO 56 35 GND PB4 46 PCS3
PCS5 31 PCS5/A1 RESET 57 19 GND PB5 45
PCS6 32 PCS6/A2 HLDA 51 51 GND PB6 44 CS_B3
DT/R 40 PB7 43 CS_B1
DEN 39 28 VSTDBY
LCK 48 XIL_CCLK
PSD503-12 CLOCK_8M
U13 XIL_DIN
80C186

PCS[0..6]

186_WR
186_RD
LC9
1000pF C41 U20 L5
+5V 1 3 14 8
U23 .1UF 186_MEMORY
186_AD0 2 A1 B1 18 186_D0 2 7 1 186_RD
186_AD1 3 A2 B2 17 186_D1 186_WR
186_AD2 4 16 186_D2 1 16Mhz
186_AD3 5 A3 B3 15 186_D3 234567890 186_A[0..17]
186_AD4 6 A4 B4 14 186_D4
COM_INT[0..2] 186_AD5 7 A5 B5 13 186_D5 186_LCS
186_AD6 8 A6 B6 12 186_D6
SERIAL_COMM 186_AD7 9 A7 B7 11 186_D7 186_UCS
A8 B8
PCS[0..6] 19 186_D[0..15]
186_RD 1 G
186_WR DIR 1 RP3 4.7K
RST_186 BUF_M10.SCH
186_A[0..17] 74LS245 PULUP_0
186_D[0..7] U22 +5V U24 PULUP_1

Figure 4-29: Form Buffer CB Interconnect Diagram (Sheet 2 of 9)

COM_INT[0..1] 186_AD8 2 A1 B1 18 186_D8 1 LD F0 12 186_D[0..15]
186_AD9 3 A2 B2 17 186_D9 2 I0 F1 13
BUF_M8.SCH 186_AD10 4 A3 B3 16 186_D10 PCS0 3 I1 F2 14
186_AD11 5 A4 B4 15 186_D11 PCS1 4 I2 F3 15
186_AD12 6 A5 B5 14 186_D12 PCS2 5 I3 F4 16 MAIN_PROCESSOR_CONTROL_186
186_AD13 7 A6 B6 13 186_D13 PCS3 6 I4 F5 17
186_AD14 8 A7 B7 12 186_D14 PCS4 7 I5 F6 18 DataCard Corp.
186_AD15 9 A8 B8 11 186_D15 PCS5 8 I6 F7 19
PCS6 9 I7 Title
19 G 11 OE SCHEMATIC, PWB, PAPER BUFFER
1 DIR
16V8 Size Document Number REV
74LS245 B 598475 A
Date: March 22, 1996 Sheet 2 of 9

Theory of Operation
 186_D[0..15] 186_D[0..15]

186_A[0..17] 186_A[0..17]

U15 U21
186_A1 12 A0 D0 13 186_D8 186_A1 12 A0 D0 13 186_D0
186_A2 11 A1 D1 14 186_D9 186_A2 11 A1 D1 14 186_D1
186_A3 10 A2 D2 15 186_D10 186_A3 10 A2 D2 15 186_D2
186_A4 9 A3 D3 17 186_D11 186_A4 9 A3 D3 17 186_D3
186_A5 8 A4 D4 18 186_D12 186_A5 8 A4 D4 18 186_D4
186_A6 7 A5 D5 19 186_D13 186_A6 7 A5 D5 19 186_D5
186_A7 6 A6 D6 20 186_D14 186_A7 6 A6 D6 20 186_D6
186_A8 5 A7 D7 21 186_D15 186_A8 5 A7 D7 21 186_D7
186_A9 27 186_A9 27

Card Affixer Module Maintenance Manual

186_A10 26 A8 186_A10 26 A8
186_A11 23 A9 186_A11 23 A9
186_A12 25 A10 186_A12 25 A10
186_A13 4 A11 186_A13 4 A11
186_A14 28 A12 186_A14 28 A12
186_A15 3 A13 186_A15 3 A13
186_A16 31 A14 186_A16 31 A14
186_A17 2 A15 186_A17 2 A15
A16 A16
186_UCS 22 CS1 22 CS1
+5V 30 CS2 +5V 30 CS2
186_RD 24 OE 24 OE
186_WR 29 WE 29 WE
186_LCS MB841000-80 MB841000-80

Figure 4-30: Form Buffer CB Interconnect Diagram (Sheet 3 of 9)

186 MEMORY

DataCard Corporation
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
B 598475 A
Date: March 22, 1996 Sheet 3 of 9

4-41
4-42
+5V +5V
LC10 LC6 LC7
1000pF 1000pF 1000pF
1 3 3 1 1 3
C42 C37 C38
2 .1UF .1UF 2 2 .1UF
U14
2 T1I T1O 5 JP6
1 T2I T2O 18 1
186_D[0..7] 186_D[0..7] 4 R1I R1O 3 2
U18 19 R2I R2O 20 3
23 VDD TXRDY0 22 4
40 VDD 24 +5V
64 VDD RTS0 25 5
DTR0 26 7 6
SOUT0 41 8 VCC 14 7
186_A[0..17] 186_D0 14 SIN0 29 13 C1+ V+ 8
186_A[0..17] 186_D1 15 DB0 DCD0 30 15 C1- 10 9
186_D2 16 DB1 RI0 31 11 C2+ C2- 16
DB2 DSR0 C2+ C2- CONN 9
186_D3 17 DB3 CTS0 28 6 GND V- 12
186_D4 18 DB4 RXRDY0 9 9 GND V- 17
186_D5 19 DB5
186_D6 20 DB6 TXRDY1 42 MAX233
186_D7 21 DB7 RTS1 12
DTR1 11
186_A1 35 A0 SOUT1 10
186_A2 34 A1 SIN1 62
PCS[0..6] PCS[0..6] 186_A3 33 A2 DCD1 8
RI1 6
RST_186 39 RESET DSR1 5
CTS1 13
PCS4 32 CS0 RXRDY1 61
PCS5 3 CS1
PCS6 38 CS2 PD0 53
COM_INT0 45 INT0 PD1 52
COM_INT1 60 INT1 PD2 51
59 INT2 PD3 50
PD4 49
186_WR 36 IOW PD5 48
186_RD 37 IOR PD6 47
44 BD0 PD7 46
43 ENIRQ ACK 68
COM_INT0 2 TRI PEMD 1
COM_INT1 PE 67
4 CLK BUSY 66
SLCT 65
R33 R38 ERR 63
4.7K 4.7K SLIN 58
54 GND INIT 57
27 GND AFD 56
7 GND STB 55
TL16C552

COM_INT[0..1] COM_INT[0..1]

+5V
LC8
1000pF U19 L3
1 3 14 8
C39 R39
2 .1UF 7 1 680
18.432M
C43
220pF

Figure 4-31: Form Buffer CB Interconnect Diagram (Sheet 4 of 9)

SERIAL COMM

DataCard Corp.
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
B 598475 A
Date: March 22, 1996 Sheet 4 of 9

Theory of Operation
 186_D[0..15] 186_D[0..15]
CUR_S[0..3]

SEN_I[0..3] SEN_I[0..3]
STEPPER_1_AND_2
STP1_C[0..5] STP1_C[0..5] CUR_B[0..3]

+5V STP2_C[0..5] STP2_C[0..5]

U6 BUF_M5.SCH
22 VCC RDATA/M1 31
64 VCC
IO* 38 186_D1
12 PWRDWN IO 39 STP1_C1
PULUP_0 32 RTRIG/M0 IO 40 CUR_B[0..3]
RST_186 54 RESET IO* 41 STP1_C0
PG_DONE 55 PG/DONE IO/INIT 42
XIL_CCLK 74 CCLK IO 44
IO 45 186_D6
186_TO1 2 IO IO 46 186_D7 CURRENT_SENSOR_INTERFACE
3 IO CUR_B[0..3]
4 IO IO 47 CUR_S[0..4]
186_TO0 STP1_C5 5 IO IO 48 186_WR
STP1_C4 6 IO* IO 49
186_A[0..17] 186_A[0..17] 186_D3 7 IO* IO* 50 186_D[0..15]
8 IO IO* 51 186_A[0..17]
WSI_T[0..3] WSI_T[0..3] SEN_I2 9 IO IO 52 STP1_C2
IO/XTL2 53 186_C0
SEN_I3 10 IO IO/D7 56 186_C1 CS_B[0..4]
11

Card Affixer Module Maintenance Manual

CLOCK_8M 186_A4 13 IO 57 STP1_C3
IO IO/XTL1 BUF_M7.SCH
186_RD 14 IO* IO/D6 58 STP2_C5
186_WR 15 IO IO 59 STP2_C4
186_A3 16 IO IO/D5 60
WSI_T0 17 IO IO/CS0 61
WSI_T1 18 IO IO/D4 62 STP2_C3
R32 IO 63
68 186_D2 19 IO IO/D3 65 186_C2 R12
SEN_I0 20 IO 1K
CS_B2 21 IO IO/CS1 66 STP2_C2
SEN_I1 23 IO IO/D2 67 CUR_S2
C34 186_A1 24 IO IO 68 CUR_S3
220pF 186_A6 25 IO IO* 69 STP2_C1 D7
WSI_T2 26 IO IO/D1 70 STP2_C0 ERROR
WSI_T3 27 IO IO/RDY/BUSY 71 LED
IO/DIN/D0 72
186_A2 28 IO IO 73
INTERLOCK 29 IO
186_C3 30 IO IO/WS 75 CS_SEN CS_SEN
33 IO/M2 IO/CS2 76
186_C4 34 IO/HDC IO 77
CUR_S0 35 IO IO 78 186_D5
CUR_S1 36 IO/LDC IO* 79 186_D4 186_C[0..4] 186_C[0..4]
186_D0 37 IO IO* 80 SON_DRIVE
IO 81
PULUP_1 1 GND IO 82 186_TO0
43 +5V
GND 83 186_TO1
IO 84 186_A5 +5V
IO
R27
XC3042-70 4.7K
R29
4.7K
J1

J2

Figure 4-32: Form Buffer CB Interconnect Diagram (Sheet 5 of 9)

CS_B[0..4] CS_B[0..4]
XLINIX 1

DataCard Corp.
XIL_DIN
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
B 598475 A
Date: March 22, 1996 Sheet 5 of 9

4-43
4-44
CUR_B[0..7] CUR_B[0..7]
+24V1
STP1_C4 R4
5 CUR_B0
RP1D C11
4.7K C8 1.0 100
.22 U2
1 2 VS R5 C7
9 VREF OUT1 3 .499 CUR_B0
STP1_C4 11 ENABLE
STP1_C0 5 IN1 1 .01 +24V1
OUT2
D5
STP1_C1 7 IN2 SENSE 10 CUR_B0 2
4 BOOT1 CR1
8 BOOT2 1N5818 MBR1545
6 GND
C9 C10 1 3 JP10
.01 .01 L6203 1
STP1_C5 2
4 3
R14 4
RP1C CUR_B1
4.7K +24V1 CONN 4
100
1 C24
.22 C21 R15 C25
1.0 .499 CUR_B1
U5
2 VS .01
9 3 D9 +24V1
STP1_C5 11 VREF OUT1 CUR_B1
STP1_C2 5 ENABLE 1 2
IN1 OUT2
1N5818 CR4
STP1_C3 7 IN2 SENSE 10 MBR1545
4 BOOT1
8 BOOT2 1 3
6 GND
C23 C22
.01 .01 L6203

R13
CUR_B2
STP1_C[0..5] STP1_C[0..5]
100
+24V1
STP2_C4 R11 C20
6 .499 CUR_B2
RP1E C15
4.7K 1.0 .01
C18 U4
1 .22 2 VS
9 VREF OUT1 3 D8
STP2_C4 11 ENABLE CUR_B2
STP2_C0 5 IN1 1 +24V1
OUT2
1N5818
STP2_C1 7 IN2 SENSE 10 2
4 BOOT1 CR2
8 BOOT2 MBR1545
6 GND
C17 C16 1 3 JP11
.01 .01 L6203 1
STP2_C5 2
7 3
R2 4
RP1F CUR_B3
4.7K +24V1 CONN 4
100
1 C3
.22 C6 R3 C2
1.0 .499 CUR_B3
U1
2 VS .01
9 3 +24V1
STP2_C5 11 VREF OUT1
ENABLE D4
STP2_C2 5 IN1 OUT2 1 CUR_B3 2
CR3
STP2_C3 7 IN2 SENSE 10 1N5818 MBR1545

Figure 4-33: Form Buffer CB Interconnect Diagram (Sheet 6 of 9)

4 BOOT1
8 BOOT2 1 3
6 GND
C4 C5 STEPPER 1 AND 2
.01 .01 L6203

DataCard Corp.
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
STP2_C[0..5] STP2_C[0..5]
B 598475 A
Date: March 22, 1996 Sheet 6 of 9

Theory of Operation
 +5V
CUR_S[0..3] CUR_S[0..3]
186_D[0..15] 186_D[0..15]
VREF
U7
3 VCC VREF 19
22 VDD
AIN0 5 CUR_B0
186_D0 18 D0 AIN1 4 CUR_B1
186_D1 17 D1 AIN2 21 CUR_B2
186_D2 16 D2 AIN3 20 CUR_B3
186_D3 15 D3
186_D4 14 D4 C0 2 CUR_S0
186_D5 13 D5 C1 1 CUR_S1
186_D6 12 D6 C2 24 CUR_S2
186_D7 11 D7 C3 23 CUR_S3
CS_B0 7 CS
8 WR
186_A1 10 A0
186_A2 9 A1
186_WR 6 GND
MAX516

Card Affixer Module Maintenance Manual

CS_B[0..4] CS_B[0..4]

186_A[0..17] 186_A[0..17]

CUR_B[0..3] CUR_B[0..3]

Figure 4-34: Form Buffer CB Interconnect Diagram (Sheet 7 of 9)

CURRENT_SENSOR_INTERFACE

DataCard Corp.
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
B 598475 A
Date: March 22, 1996 Sheet 7 of 9

4-45
4-46
LC3
1000pF
1 3 +5V SEN_I[0..3] SEN_I[0..3]
186_D[0..15] 186_D[0..15]
1 2
VR1 VR2 C33
2K 2K .1UF
RP2
4.7K
1 186_WR
098765432
R30 R35
200 200

+5V

U8
19 VREF VCC 3
VDD 22
5 AIN0
4 AIN1 D0 18 186_D0
21 AIN2 D1 17 186_D1
20 AIN3 D2 16 186_D2
D3 15 186_D3
SEN_I0 2 C0 D4 14 186_D4
SEN_I1 1 C1 D5 13 186_D5
SEN_I2 24 C2 D6 12 186_D6
24681111121111197531 SEN_I3 23 11 186_D7
02468097531 C3 D7
JP3 CS 7 CS_SEN
CONN 20SENSOR WR 8
A0 10 186_A1
186_A[0..17] 186_A[0..17] A1 9 186_A2

GND 6
CS_SEN
MAX516
L2 C28

20PF
R17

SON_DRIVE 30K

U9B
JP4 R18
1 6
2 R16
3 1K 7
4 5
5 1K
R20
CONN 5 MC34072

Figure 4-35: Form Buffer CB Interconnect Diagram (Sheet 8 of 9)

1K

R19
C29 30K SENOR INTERFACE UNIT
20PF
DataCard Corp.
Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
VREF B 598475 A
Date: March 22, 1996 Sheet 8 of 9

Theory of Operation
 INTERLOCK

+24V +24V
+5V
+24V1 +5V RST_186
R31 R28
2K 3K +24V
R36 +24V
D3 R24 4.7K
8 U10A 10K
R6
1N914 3 U16A 10
1 1/2W LC1
2 1 2 1000pF
1 3
LM393
4 U16F 74LS04
R25 R26 2
3K 2K 13 12 JP1
1 3 1
2
74LS04
U16E D1 LC2 CONN 2
2 1000pF
11 10
1N4002
K1
74LS04 +24V 8 TP1
+5V U16D 1 +24V1 TP
U17 4
1 IN VCC 8 9 8 6
3 T RST 5 2
2 M RST 6
4 GND NMI 7 74LS04 RELAY SPDT1
U16C

Card Affixer Module Maintenance Manual

DS1231-20 R7
5 6 10 R1
1/2W 4.7K
+5V
+24V 74LS04
U16B
TP4 R22
TP 3 4 D2 1K
JP2 LED
24V1 +5V
4 VREF
3 74LS04
+24V
2 +5V
1 R21 8 U9A
4.7K U3
CONN 4 LT1074 L1 3
5 VIN VSW 4 1
C12 2
.001UF 2 VCOMP G FB 1 50UH C19 R23 2 U11
N D6 1K MC34072
D10 D USD945 R10 C32 4
LED R8 3.32K 470UF
24V 4.7K 3 C27
.001UF 0.1 1
D11
LED LM336
+5V 3
R9
C13 2.55K
.033

8 U10B
TP5
5 +5V TP
7
6
LM393
4 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 CB9 CB10 CB11 CB12 CB13 CB14 CB15 CB16 CB17
.1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF

Figure 4-36: Form Buffer CB Interconnect Diagram (Sheet 9 of 9)

+24V +5V +5V +5V +5V +24V1 +24V
TP2 TP3 TP6 POWER CONTROL
TP TP TP
C14 C26 C30 C44 C31 C1 CB18 DataCard Corp.
1000UF 10UF 10UF 10UF 10UF 100UF .1UF
ELE TAN TAN TAN TAN ELE Title
SCHEMATIC, PWB, PAPER BUFFER
Size Document Number REV
B 598475 A
Date: March 22, 1996 Sheet 9 of 9

4-47
High Speed Card Affixer Module Electrical Block Diagrams
The electrical block diagrams for the High Speed Card Affixer module are described
in the following section. Figure 4-37 is a schematic of the PC board used for AC
power distribution.

JP4 JP2
AC Po wer Fo r
Aux. A.C. 132 321 DC Po wer
Sup p ly

4 5

7 6 K1 Rela y
10
TH1 TH2
4A 4A 1

2 CB1
5A
1

JP3 JP1
4 1
AC 3 2 AC
Po wer 2 3 Po wer
In 1 4 O ut

U1 16V
JP5
IN4745
24V Inp ut 0
Fo r 1
2 240
Interlo c k
Co ntro l 3 G 64350-1

Figure 4-37: High Speed Affixer 230V AC Power Schematic Diagram

4-48 Theory of Operation

High Speed UltraForm System Power Interconnect

Figure 4-37 and Figure 4-38 represent the system power interconnect wiring for the
Card Affixer module.

P/ N 806480-002
48V
Po wer
Sup p ly
Fo ld er
AC System AC Po wer Dist

560069-001
JP4

JP2
P/ N 806480-001 4 4
36V 3 3 TH1
Po wer 2 2 TH2
K1
Sup p ly JP5
1 1

JP3 JP1 T
Stic ker Ap p lic a to r G
O R1
D1
Ca rd Affixer
AC Po wer Dist AC p o wer Dist

560069-001 560069-001
JP4 JP4 P/ N 806480-001
36V
JP2 JP2 Po wer
4 4 4 4 Sup p ly
3 3 TH1 3 3 TH1
2 2 TH2 K1 2 2 TH2 K1
JP5 JP5
1 1 1 1

JP3 JP1 T JP3 JP1 T

G G
O R1 O R1
D1 D1

To Term ina l
Blo c k JP4
O n Ultra fo rm
64350-7
Ma in Po wer
Pa nel

Figure 4-38: High Speed UltraForm AC Power Interconnect Diagram

Card Affixer Module Maintenance Manual 4-49

High Speed UltraForm System DC Block Diagram

Figure 4-39 represents the High Speed UltraForm system DC distribution block
diagram.

System D.C.

P/ N 806480-001

AC AC
+36V
AC Stic ker
DC
Dis Ap p lic a to r
Pwr
MCB
Interlo c k Sup p ly
JP5
Co ntro l

Fo rm
Buffer
MCB

P/ N 806480-001

AC AC
AC +36V
DC Ca rd
Dis
Pwr Affixer
J9
Sup p ly MCB
Interlo c k JP5
Co ntro l 5V

J1
Byp a ss
Tra y
Step p er
Bo a rd

P/ N 806480-002 +5V Co ntro l

Line Fo r 48V
J1 P.S. O n/ O ff
AC AC +48V +24VDC To
AC
DC 48VDC Pro vid e +5VDC
Dis Fo ld er
Pwr To Co ntro l Lo g ic
MCB
Sup p ly And Pro c esso r
Interlo c k JP5 Fo r All Hig h
Co ntro l Sp eed Ultra fo rm
JP1
MCB's
64350-3

Figure 4-39: High Speed UltraForm System DC Power Diagram

4-50 Theory of Operation

High Speed UltraForm Interlock System Block Diagram

When UltraForm Interlocks are closed, +24 V is applied to JP5 on the AC

Distribution board. This allows K1 relay to be energized which allows AC to be
applied to JP2. The AC voltage on JP2 provides power to the module power supply.
Figure 4-29 represents the High Speed UltraForm system interlock block diagram.

If any of the interlock switches are opened, you lose AC Power that is applied to
the module power supplies.

BIF +24 Vo lts/ G ro und

Co ntro l Of The AC Distrib utio n

AC Distrib utio n Stic ker Mo d ule

Bo a rd 560069 Co ntro l Bo a rd
K1 JP5
321 BIF IN
+24 Vo lts DC +24 Vo lts DC
G ND G ND

G ND +24 Vo lts DC

AC Distrib utio n
Bo a rd 560069
6 Interlo c k
K1 JP5 Switc hes
321 JP2

G ND

+24 Vo lts DC

Fo ld er Mo d ule
AC Distrib utio n Co ntro l Bo a rd
Bo a rd 560069
K1 BIF IN
JP5
321 +24 Vo lts DC
G ND BIF
G ND +24 Vo lts DC Interlo c k
G ND +24 Vo lts DC

64350-2

Figure 4-40: High Speed UltraForm System Interlock Diagram

Card Affixer Module Maintenance Manual 4-51

High Speed UltraForm System Cabling Diagram
Figure 4-41 below represents the High Speed UltraForm system cabling block
diagram.

J1
Bypass Tray Board

Sticker Applicator Card Affixer MCB

High Speed
Ultraform System
Cable Interconnect
Diagram

Bif Board
JP8
Out
Output Stacker
In CAPC
MCB J19 Parallel
Port
Out In
Com1 Com2 LPT1

Folder Module
Control Board
Contactor Form Buffer Board
Board

JP4
JP2 JP6
In JP1
In Out
Sonic
Out JP8
Sensor
To JP20
JP5 On Ultrapac
From 9000 Ultraform
Modules Main Power
Panel

Printer

Figure 4-41: High Speed UltraForm System Cabling Diagram

4-52 Theory of Operation