İzmir Katip Çelebi University

Department of Electrical and Electronics Engineering EEE204

Electronics Laboratory
Spring 2023 - 2024Spring 2020
Lab Work IX
Junction Field Effect Transistor
The objective of this exercise is to examine the characteristics of JFET and AC/DC analysis of
JFET amplifiers.
Pre-Lab Report o Please study related topics in reference notes.

o Prepare report with simulation results and schematics, individually, o Submit your report
until May 19, 23:59 to CANVAS and mail to research assistants’ address. o Submit your
preliminary report individually.

References o

Lecture notes o Neamen, “Microelectronics Circuit Analysis and Design,” Chapter

4.9 Questions

1. Explain how you can determine the type of a JFET (n or p channel) and test it whether if
it is defected or not.
FETs are constructed differently to Bipolar Transistors then require a special testing
techniques. First consider the JFET diagrams in Figure which show the drain/source path
as a single block of either N type or P type silicon and the Gate as a simple diode which
has either it's anode (in P Channel JFETs) or cathode (in N Channel JFETs) connected
directly drain/source path. Therefore rather than having to check two PN junctions as in
BJTs, in JFETs we only got to test one [Link] first thing to understand before testing
a suspect JFET is that the pinout, like all other transistor this will be obtained by
downloading the info sheet for the actual JFET of interest.

PNINPggSSN Channel JFETP Channel JFETOnce the Source, Drain and Gate pins are
identified, the following digital meter tests should reveal the state of the JFET:Switch the
 meter to diode testing [Link] the resistance between Source and Drain with the
positive meter lead on the Drain [Link] the meter leads (positive to Source) and skim
the resistance [Link] results of tests 1. and 2. should typically be around 130Ω to 180Ω
but this can vary in different JFETS. If the resistance seems suspiciously low, it could mean
that there's a remnant of voltage on the very high impedance Gate thanks to the gate junction
capacitance. To remove this possibility short the Gate and Source by momentarily touching
both pins together then repeat tests 1. and 2. A reading of 0Ω or infinity means the JFET is
[Link] steps 2 and three are OK, check the resistance between Gate and Source
with the positive meter probe on the Gate pin. Expect a resistance of around 700Ω to 1KΩ.
This is the forward resistance of the Gate [Link] the positive meter probe on the
Gate, move the negative probe to the Drain and check the resistance between Gate and
Drain. Expect similar results to test [Link] reverse the meter connections and test the
reverse resistance of the Gate diode by placing the negative probe on the Gate pin and
therefore the positive probe on the Source pin. The resistance now should be [Link]
check the Gate to Drain resistance by leaving the negative probe on the Gate and moving
the positive probe to the Drain pin. Again the reading should be [Link] all of those
tests you ought to refrain from handling the JFET the maximum amount as is feasible .
Ideally, when working with any sort of field effect transistors you ought to be performing
at an ESD (Anti Static Discharge) workstation or be wearing an antistatic wrist strap.
Alternatively you'll a minimum of stick the pins (assuming they're long enough) during a
piece of anti static foam like FETs are normally stored in. The resistance between the pins
will then avoid the build from static voltages, but are going to be high enough to not greatly
affect the resistance readings you're taking during these tests.
2. Compare BJT and JFET, explain applications areas and advantages/disadvantages. BJTs
(Bipolar Junction Transistors) and JFETs (Junction Field-Effect Transistors) differ
primarily in operation and application. BJTs are current-controlled devices used extensively
in high-current applications like power regulation and audio amplifiers, benefiting from fast
switching but suffering from lower input impedance and higher power consumption.
Conversely, JFETs are voltage-controlled with very high input impedance and low power
consumption, making them ideal for RF amplifiers and analog buffers where minimal signal
distortion is crucial, though they are generally slower in switching and less suitable for
high-power tasks. Both have unique advantages, with BJTs offering robust current handling
and faster operation, and JFETs providing high linearity and low noise, guiding their
respective uses in electronic circuits.
3. Sketch 𝐼𝑑 − 𝑉𝑑𝑠 graph for 𝑉𝑔𝑠 = 0, −2, −4, −6, −8𝑉. Sketch 𝐼𝑑 − 𝑉𝑔𝑠 graph, indicate 𝐼𝑑𝑠𝑠
𝑎𝑛𝑑 𝑉𝑔𝑠(𝑜𝑓𝑓) using output characteristics above.
4. Explain pinch-off voltage and the relationship between drain current and pinch-off voltage.
Pinch-off voltage is the gate voltage at which the conductive channel in a field-effect
transistor (like a JFET or MOSFET) becomes so narrow that it restricts any further increase
in drain current despite increases in drain-source [Link] between drain
current and pinch-off voltage:Below Pinch-Off Voltage: The channel is fully open, and the
current increases with increasing [Link] Pinch-Off Voltage: The channel starts to close
off; beyond this point, increasing the drain-source voltage doesn't significantly increase the
current. The transistor enters saturation, where the drain current remains relatively constant,
determined mainly by the gate voltage.
5. Consider the circuit of Figure 1 with MPF102 JFET using 𝑉𝐷𝐷 = 15𝑉 𝑎𝑛𝑑 𝑉𝑔𝑔 = 0𝑉. With
nothing else in the circuit, the resulting drain current should equal to 𝐼𝐷𝑆𝑆. Similarly if 𝑉𝑔𝑔
is gradually changed to a value negative enough to drop the drain current to zero, 𝑉𝑔𝑔 must
be equal to 𝑉𝐺𝑆(𝑂𝐹𝐹). Build the circuit of Figure 1, simulate and measure the drain circuit
and record it in Table 1. Slowly increase the magnitude of 𝑉𝑔𝑔 until the drain current drops
to zero. Record this voltage in Table 1.

Figure 1 Determining 𝐼𝐷𝑆𝑆 and 𝑉𝐺𝑆(𝑂𝐹𝐹)

 Table 1

𝐼𝐷𝑆𝑆 𝑉𝐺𝑆(𝑂𝐹𝐹)
21.2779mA -1.7V

6. Consider the circuit of Figure 2 with MPF102 JFET using 𝑉𝐷𝐷 = 15𝑉 , 𝑅𝐷 = 4.7𝑘Ω, 𝑅𝐺 =
330𝑘Ω, 𝑅𝑆 = 2.2𝑘Ω. Using the values of Table 1, calculate and record the expected voltages
and drain current for JFET in Table 2. Build the circuit of Figure 2, simulate and measure
voltages for JFET in Table 2. Based on 𝑉𝐷, compute the experimental drain current. Record
this values in Table 2.
 Figure 2 Self Bias

Table 2
JFET Theoretical Experimental
𝑉𝐷 12.8636V 13.2716 V
𝑉𝑆 0.99V 0.8090V
𝑉𝑔 0V 0.6mV

𝐼𝐷 0.4545mA 0.3677mA

7. Consider the circuit of Figure 3 with MPF102 JFET using 𝑉𝐷𝐷 = 15𝑉, 𝑉𝑆𝑆 = −3𝑉, 𝑅𝐷 =
4.7𝑘Ω, 𝑅𝐺 = 330𝑘Ω, 𝑅𝑆 = 4.7𝑘Ω. A reasonable approximation for 𝑉𝐺𝑆 in this circuit is
2V. Based on this, calculate and record the expected voltages and drain current for JFET
in Table 3. Build the circuit of Figure 3, simulate and measure voltages for JFET in Table
3. Based on 𝑉𝐷, compute the experimental drain current. Record this values in Table 3.

Figure 3 Source Bias

 Table 3
JFET Theoretical Experimental
𝑉𝐷 10V 11.2805V
𝑉𝑆 2V 0.71V
𝑉𝑔 0V 0.6633mV

𝐼𝐷 1.0638mA 0.7913mA

AC/DC analysis of JFET Amplifiers (Common Source)

8. Consider the circuit of Figure 4 with MPF102 JFET using 𝑉𝐷𝐷 = 15𝑉, 𝑉𝑆𝑆 = −3𝑉, 𝑅𝐼𝑁 =
33𝑘Ω, 𝑅𝐷 = 4.7𝑘Ω, 𝑅𝐺 = 330𝑘Ω, 𝑅𝑆 = 4.7𝑘Ω, 𝑅𝐿 = 22𝑘Ω 𝑎𝑛𝑑 𝐶𝐼𝑁 = 𝐶𝑜𝑢𝑡 =
10𝑢𝐹, 𝐶𝑠 = 470𝑢𝐹. Assuming 𝑉𝐺𝑆 = −2𝑉 𝑎𝑛𝑑 𝑔𝑚 = 2𝑚𝑆, determine the theoretical gain
and input impedance of the circuit and record in Table 4.
a. Build the circuit and set 𝑉𝐼𝑁 = 100𝑚𝑉 𝑝𝑒𝑎𝑘 𝑠𝑖𝑛𝑒 𝑎𝑡 1𝑘𝐻𝑧. Measure the voltages at
the gate and load, and record these in Table 4. Show and save the input and gate signals,
and the gate and load signals. Note whether or not the load is inverted compared to the
gate signal. Comment on this.
b. Based on the measured gate and drain voltages, determine the resulting theoretical 𝐴𝑣
𝑎𝑛𝑑 𝑍𝑖𝑛, and record these in Table 4. Note that 𝑍𝑖𝑛 may be computed using the voltage
divider rule or Ohm’s law given the gate and input voltages along with the input resistor
value.
Figure 4 Common Source Voltage Amplifier
 Table 4
JFET Theoretical Experimental
𝑉𝐷 11.1V
𝑉𝐺 64.2mV
𝐴𝑣 19.25Vpp 19.25Vpp
𝑍𝑖𝑛 330kΩ 330kΩ