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Synchronous Up Counter Function

The document describes a function that simulates a synchronous up counter with enable and reset signals. The counter increments on the rising edge of an implicit clock when enabled and resets to an initial count when the reset signal is high. It includes validation checks for input parameters and provides an example usage with plots of the enable, reset, and counter output signals.

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3 views1 page

Synchronous Up Counter Function

The document describes a function that simulates a synchronous up counter with enable and reset signals. The counter increments on the rising edge of an implicit clock when enabled and resets to an initial count when the reset signal is high. It includes validation checks for input parameters and provides an example usage with plots of the enable, reset, and counter output signals.

Uploaded by

copeyic220
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

function count = basic_up_counter(enable_signal, reset_signal, num_bits, initial_count) %

basic_up_counter(enable_signal, reset_signal, num_bits, initial_count) % simulates a basic synchronous up counter. % %


What it does: This function simulates a synchronous up counter with an % enable and a reset input. The counter
increments its value by 1 on each % rising edge of an implicit clock (represented by the index of the input % signals)
when the enable signal is high. If the reset signal is high, the % counter is reset to the initial count. The counter has a
specified number % of bits, which determines its maximum count value. % % Theory: A synchronous up counter
increments its count value on each clock % pulse. The 'enable' signal controls whether the counter is active and should
% increment. The 'reset' signal forces the counter back to a predefined % starting value, typically zero or a specified
initial count. The number of % bits determines the range of values the counter can represent (from 0 to % 2^num_bits -
1). The modulo operation is used to implement the wrap-around % behavior when the counter reaches its maximum
value.

if ~islogical(enable_signal) || ~islogical(reset_signal) || length(enable_signal) ~= length(reset_signal)


error('Enable and reset signals must be logical vectors of the same length.');
end

if ~isscalar(num_bits) || num_bits <= 0 || num_bits ~= floor(num_bits)


error('Number of bits must be a positive integer scalar.');
end

if ~isscalar(initial_count) || initial_count < 0 || initial_count >= 2^num_bits || initial_count ~= floor(initial_count)


error('Initial count must be a non-negative integer scalar less than 2^num_bits.');
end

count = zeros(size(enable_signal));
current_count = initial_count;
max_count = 2^num_bits - 1;

for i = 1:length(enable_signal)
if reset_signal(i)
current_count = initial_count;
elseif enable_signal(i)
current_count = mod(current_count + 1, max_count + 1);
end
count(i) = current_count;
end

end

% Example usage: clock_cycles = 100; enable = [true(1, 50), false(1, 20), true(1, 30)]; % Enable for first 50 and last 30
cycles reset = [false(1, 10), true(1, 5), false(1, clock_cycles - 15)]; % Reset briefly bits = 4; initial = 5; counter_output =
basic_up_counter(enable, reset, bits, initial);

figure; subplot(3, 1, 1); plot(1:clock_cycles, enable); ylabel('Enable'); ylim([-0.5, 1.5]); grid on;

subplot(3, 1, 2); plot(1:clock_cycles, reset); ylabel('Reset'); ylim([-0.5, 1.5]); grid on;

subplot(3, 1, 3); plot(1:clock_cycles, counter_output); xlabel('Clock Cycle'); ylabel('Count'); title(['Basic Up Counter (',
num2str(bits), ' bits, Initial = ', num2str(initial), ')']); grid on;

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